Run IIb L1Cal Initialization procedure


Rev: 07-Mar-2006  as of L1Cal_IIb_TCS V4.0.A


0) Pre-Initialization 

    - Clear Bit3 error status
    
    - execute the PRE-INIT AUXI command file (currently empty)
    
    - Flag system as non-operational, 
      which also temporarily suspends collecting monitoring data
    

I) Initialize all ADF Cards

    - positive eta, then negative eta sign
    - for each eta sign, in increasing eta magnitude 
    - for each eta magnitude, in increasing phi
    
    - the procedure is detailed in adf_initialization.txt in 
    http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/tcc/l1cal_iib_tcs/


II) Initialize all TAB Cards 

    - in increasing Phi order i.e. increasing TAB module number
    
    - call the Tab_Initialize function from the tabgab library

    - Mike should provide the details of what is done here


III) Initialize the GAB

    - call the Gab_Initialize function from the tabgab library
    
    - Mike should provide the details of what is done here


IV) Verify proper ADF-to_TAB Channel Link operation and re-de-skew as needed


   1) Prepare all ADF Cards to send Pseudo-Random Data
        - Stop Pseudo-Random Generator, 
        - Load Pseudo-Random seeds, 
        - Start Pseudo-Random Generator, 
        - Send the Pseudo-Random Data to the TABs

   2) Go over all TAB cards up to N times (initially N=50)
      or untill all report that all their Channel Links operate properly
      
      2.a) Read the TAB status once (which clears the status), 
           and ignore that first reading

      2.b) Wait one second while the TABs are actively watching the data
      
      2.c) Read the status word from all TABs 
           i.e. take a snapshot before any de-skewing action could cause more errors

      2.d) Verify each TAB 
      
          - in increasing Phi order, i.e. increasing TAB module number

          2.d.1) verify each TAB Algorithm FPGA Status
        
            - positive eta, then negative eta sign
            - for each eta sign, in increasing eta magnitude 
            - i.e. TAB Chip Number 5, 6, 7, 8, 9, 4, 3, 2, 1, 0
            
            - Examine the FPGA status word (cf. 2.c), and for each of the 3 Channel Links
              monitored by this FPGA, form the .OR. of the bitfields for 
              "parity error" (bit 0:2), "data sync error" (bit 3:5)
              and "BC mismatch" (bit 6:8)
              cf. http://www.nevis.columbia.edu/~evans/l1cal/hardware/tab/status_regs.html
              
          2.d.2) for each TAB Input Channel Link that shows a problem
                 (i.e. when the 3-way OR-ed Status Bit in 2.d.1 is found asserted) 
                 
            - tell the corresponding ADF-2 Card to initiate a De-Skew
              on its outputs, i.e. it will de-skew all 3 of its outputs.
              
        2.e) Stop early if all TAB FPGAs reported that all their Channel Link are ok
             or repeat step IV.2 up to N times
             

    3) Final verification (with no more de-skewing performed)

      3.a) Read the TAB status once, and ignore that first reading

      3.b) Wait one second while the TABs actively watch the data
      
      3.c) Read the status word from all TABs 

      3.d) Verify each TAB 
      
          - in increasing Phi order, i.e. increasing TAB module number

          3.d.1) verify each TAB Algorithm FPGA Status
        
            - positive eta, then negative eta sign
            - for each eta sign, in increasing eta magnitude 
            - i.e. TAB Chip Number 5, 6, 7, 8, 9, 4, 3, 2, 1, 0
            
            - Examine the FPGA status word (cf. 3.c), and for each of the 3 Channel Links
              monitored by this FPGA, form the .OR. of the bitfields for 
              "parity error" (bit 0:2), "data sync error" (bit 3:5)
              and "BC mismatch" ( bit 6:8)
              
       3.e) If no FPGA from any of the TABs is found complaining, we have succeeded
       3.f) but if any one of the TAB's FPGAs is complaining, a failure will be returned back to COOR


    4) Return the ADF cards to desired inititalization 
       - send BLS Data to TABs
       - pseudo-random pattern stopped
       - pseudo-random seeds reloaded to the non-evolving value 0xffff
       

V) Initialize the Trigger Tower objects

    - the procedure is detailed in adf_initialization.txt in 
    http://www.pa.msu.edu/hep/d0/ftp/run2b/l1cal/tcc/l1cal_iib_tcs/


VI) Verify ADF-2 Et Lookup table 

    - done separately from and after (V) for added robustness
    

VII) Initialize the data structures that will hold high level programming

    - RefSet Allocation flags
    - RefSet Thresholds  
    - EM Isolation Ratios
    - EM/HD Fractions


VIII) Post- Initialization

    - execute the POST-INIT AUXI command file 
          e.g. that is where we will be excluding sick Trigger Towers
    
    - Re-Enable monitoring (if it was found disabled)
    
    - If Initialization was successful, declare L1Cal operational