////////////////////////////////////////////////////////////////////////////// // File: L1CalTcc_MonitData_TabGab_Status.hpp // // Monitoring block type: L1Cal TAB and GAB Status // // Created: 11-Oct-2005 Philippe Laurens ////////////////////////////////////////////////////////////////////////////// #ifndef __L1CalTcc_MonitData_TabGab_Status__ #define __L1CalTcc_MonitData_TabGab_Status__ ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// // Variable Size Definitions ////////////////////////////////////////////////////////////////////////////// #include "trigmon/L1CalTcc_MonitData_BasicTypes.hpp" ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// // All Data Blocks returned by TCC start with a Simple Header ////////////////////////////////////////////////////////////////////////////// #include "trigmon/L1CalTcc_MonitData_Header.hpp" ////////////////////////////////////////////////////////////////////////////// // Beam Crossing Number Monitoring (Sub-)Structure ////////////////////////////////////////////////////////////////////////////// #include "trigmon/L1CalTcc_MonitData_BeamX.hpp" //////////////////////////////////////////////////////////////////////////////// #define kL1CalTcc_Tot_Tab_Card 8 // Total Number of TAB Cards #define kL1CalTcc_Tot_Tab_Algo_Fpga 10 // Total Number of TAB Algorithm FPGA, i.e. "Chip 0-9" #define kL1CalTcc_Tot_Tab_Algo_ErrCounter 16 // Total Number of Error Counter per TAB Algorithm FPGA #define kL1CalTcc_Tot_Tab_Glob_ErrCounter 16 // Total Number of Error Counter per TAB Global FPGA #define kL1CalTcc_Tot_Gab_Rec_Fpga 4 // Total Number of GAB Receiver FPGA, i.e. "LVDS Chip 1-4" #define kL1CalTcc_Tot_Gab_Rec_ErrCounter 16 // Total Number of Error Counter per GAB Receiver FPGA #define kL1CalTcc_Tot_Gab_Glob_ErrCounter 16 // Total Number of Error Counter per GAB Global FPGA #define kL1CalTcc_Tab_Algo_IncrNegBitMask 0x0000 // which TAB Algorithm FPGA Error Counters are incremented // when the corresponding status bit is found negated #define kL1CalTcc_Tab_Glob_IncrNegBitMask 0x000e // ditto for the Global FPGA Error Counters #define kL1CalTcc_Gab_Rec_IncrNegBitMask 0x0000 // ditto for the GAB Receiver FPGA Error Counters #define kL1CalTcc_Gab_Glob_IncrNegBitMask 0x0006 // ditto for the GAB Global FPGA error Error Counters get incremented /////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////// // This is the Data Block Content Definition for Type "L1Cal TAB and GAB Status" // cf. http://www.nevis.columbia.edu/~evans/l1cal/hardware/tab/status_regs.html /////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////// // This structure describes the content of the Opaque ITC message received from TCC // A block of this type (eL1CalTcc_BlockType_Adf_OutputEt) can be requested on the // Monitoring Server Port #52348. struct L1CalTcc_Block_TabGab_Status { L1CalTcc_Block_Header xHeader ; L1CalTcc_BeamX_Number xBeamX ; // These are the Algorithm TAB FPGA Status words, // with the second index of the array (0-9) corresponds to TAB "Chips 0-9" // // Each FPGA has 3 cable inputs, lablelled A,B, and C, to provide // phi overlap data. The definition is as follows: // // Cable A: (nominal eta, nominal phi + 4) // Cable B: (nominal eta, nominal phi ) // Cable C: (nominal eta, nominal phi - 4) // // Bit Number Bit Meaning // // 0 parity error on input cables C // 1 parity error on input cables B // 2 parity error on input cables A // 3 data sync error on input cables C // 4 data sync error on input cables B // 5 data sync error on input cables A // 6 BC mismatch on input cables C // 7 BC mismatch on input cables B // 8 BC mismatch on input cables A // 9 PLL lost lock // 10 mode_ff // 11 PRN test data error on cables C // 12 PRN test data error on cables B // 13 PRN test data error on cables A // 14 Expert Bit 1 (changes for spec tests) // 15 Expert Bit 2 (changes for spec tests) // uint16 a2uwTabAlgo_Status [kL1CalTcc_Tot_Tab_Card] [kL1CalTcc_Tot_Tab_Algo_Fpga] ; // These are the Global FPGA Status words from the TAB Global FPGA, i.e. TAB "Chip 10" // // Bit Number Bit Meaning // // 0 testmode data // 1 cp90 locked // 2 cp53 locked // 3 run (saw init and turn) // 4:15 Unused // uint16 auwTabGlob_Status [kL1CalTcc_Tot_Tab_Card] ; // These are the Receiver GAB FPGA Status words, // with the array index (0-3) corresponding to the GAB "LVDS Chips 1-4" // // Bit Number Bit Meaning // // 0 pulse: diagnostic pulse signal is present // 1 PLL not locked // 2 latched parity error on input cable 1 // 3 latched parity error on input cable 2 // 4 unlatched parity error on input cable 1 // 5 unlatched parity error on input cable 2 // 6 sync_error: if sync signal on two cables differs // 7 bc_error: if bc signal on two cables differs // 8 valid_error: if valid signal on two cables differs // 9 sclbc_error: if chip10 BC on two cables differs // 10 sclturn_error: if turn on two cables differs // 11-15 Unused // uint16 auwGabRec_Status [kL1CalTcc_Tot_Gab_Rec_Fpga] ; // This is the Global GAB FPGA Status words, i.e. GAB "S-30 FPGA" // // Bit Number Bit Meaning // // 0 init init signal is present // 1 sclrun: saw init and turn // 2 locked: PLLs locked // 3 sclerror: SCL Init requested // 4:15 Unused // uint16 uwGabGlob_Status ; // Place Holder to reach next 32 bit boundary uint16 uwReserved ; // Place Holder to reach next 64 bit boundary uint32 ulReserved ; // These are the counters attached to the bits of the TAB Algorithm FPGA Status words, i.e. "Chips 0-9" // There are only 14 "latched" status bits, but we keep track of all 16 status bits, // for simplicity, and so that the array index matches the bit position in the status word. // // Array 3rd Index Error Counter // // 0 parity errors on input cables 1 // 1 parity errors on input cables 2 // 2 parity errors on input cables 3 // 3 data sync errors on input cables 1 // 4 data sync errors on input cables 2 // 5 data sync errors on input cables 3 // 6 BC mismatch on input cables 1 // 7 BC mismatch on input cables 2 // 8 BC mismatch on input cables 3 // 9 PLL lost lock // 10 mode_ff // 11 PRN test data error on cables 1 // 12 PRN test data error on cables 2 // 13 PRN test data error on cables 3 // 14 serial data alignment error // 15 (*) PLL *NOT* Locked // // Note: All counters are incremented when L1Cal TCC finds the corresponding // a2uwTabAlgo_Status status bit asserted except for the items marked with a (*) // for which the counter is incremented when the corresponding bit is found negated. uint16 a3uwTabAlgo_ErrCnt [kL1CalTcc_Tot_Tab_Card] [kL1CalTcc_Tot_Tab_Algo_Fpga] [kL1CalTcc_Tot_Tab_Algo_ErrCounter] ; // These are the counters attached to the bits of TAB Global FPGA Status word, i.e. "Chip 10" // There are no "latched" bit in the TAB Global Chip, // but we keep track of all 16 status bits, for simplicity, and symmetry with the rest. // // Array 2nd Index Error Counter // // 0 testmode data // 1 (*) cp90 *NOT* locked // 2 (*) cp53 *NOT* locked // 3 (*) *NOT* running // 4:15 Unused // // Note: All counters are incremented when L1Cal TCC finds the corresponding // auwTabGlob_Status status bit asserted except for the items marked with a (*) // for which the counter is incremented when the corresponding bit is found negated. uint16 a2uwTabGlob_ErrCnt [kL1CalTcc_Tot_Tab_Card] [kL1CalTcc_Tot_Tab_Glob_ErrCounter] ; // These are the counters attached to the bits of GAB Receiver Status words, i.e. "Chips 1-4" // There are only 7 "latched" status bits per GAB Receiver Chip, // but we keep track of all 16 status bits, for simplicity, // and so that the array index matches the bit position in the status word. // // Array 2nd Index Error Counter // // 0 parity errors on input cables 1 // 1 parity errors on input cables 2 // 2 bc_error: XOR of BC error on two cables // 3 sync_error: XOR of serial data sync error on two cables // 4 valid_error: XOR of data not valid on two cables // 5 sclbc_error: XOR of chip10 BC error on two cables // 6 sclturn_error: XOR of Turn error on two cables // 7 Unused // 8 Unused // 9 pll_lock_error: XOR of PLL lock error on two cables // 10:14 Unused // 15 (*) PLL *NOT* Locked // // Note: All counters are incremented when L1Cal TCC finds the corresponding // auwGabRec_Status status bit asserted except for the items marked with a (*) // for which the counter is incremented when the corresponding bit is found negated. uint16 a2uwGabRec_ErrCnt [kL1CalTcc_Tot_Gab_Rec_Fpga] [kL1CalTcc_Tot_Gab_Rec_ErrCounter] ; // This is the counter attached to the GAB status word for the "S-30 FPGA" // There is only 1 "latched" bit per GAB Global Satus Chip, // but we keep track of all 16 status bits, for simplicity, // and so that the array index matches the bit position in the status word. // // Array Index Error Counter // // 0 (*) init: *NOT* initialized? // 1 (*) sclrun: *NOT* running // 2 (*) locked: *NOT* PLLs locked // 3 sclerror: SCL Init requested // 4:15 Unused // // Note: All counters are incremented when L1Cal TCC finds the corresponding // auwGabGlob_Status status bit asserted except for the items marked with a (*) // for which the counter is incremented when the corresponding bit is found negated. uint16 auwGabGlob_ErrCnt [kL1CalTcc_Tot_Gab_Glob_ErrCounter] ; } ; ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// #endif // __L1CalTcc_MonitData_TabGab_Status__