Control of the SVX Sequencer Controller L1_Busy "Delay" in the SCL Hub-End Status Concentrator Module --------------------------------------------------------- Original Rev. 20-DEC-2004 Current Rev. 18-MAR-2005 This document describes modifications to the Trigger Status Concentrator (TSC) hardware and firmware to extend the Level 1 Busy (Status 0) to the trigger frameworks. This modified version of the TSC will only be used for Geographic Sections 0:7, i.e. the Platform Sequencer Controllers. This modification is part of a larger effort to reduce the L1_Busy deadtime from the SMT and CFT systems. Each TSC receives 8 channels of status information from the front end and each channel includes one Level 1 Busy signal as part of this status. The purpose of the modifications is to extend the time that each Level 1 Busy signal is held active to the trigger frameworks even after the signal has been negated by the sender. In order to do this, the PCB and firmware are changed to route the Level 1 Busy(s (Status 0) onto the spare 2 (status 7) signals. Thus, an extended version of each of the Level 1 Busy signals are re-routed out through the TSC spare 2 connector. This modification also adds 4, 16-bit registers to the TSC VME address space. These 4 registers hold values for the 8, 6-bit timers that control the length of time that the Level 1 Busy is extended. The range of values that each timer will extend the Level 1 Busy are listed in the following table. Timer The end of 6-bit L1 Busy is hex value extended by Remarks ----------- ----------- ----------------------------------------- 0x00 ~15 ns Is the prop delay through the Altera logic Plus synchronization time to the 10MHz oscillator 0x01 100 ns . 0x02 200 ns . 0x03 300 ns . 0x04 400 ns . 0x05 500 ns . 0x06 600 ns . .... In 100 ns increments (timer runs at 10MHz) 0x3e 6.1 us . 0x3e 6.2 us . 0x3f 6.3 us Maximum extend time The 4 new TSC registers are VME 16 bit read/write accessible. On power-up or system reset the register value defaults to 0x0000. Each byte of the 16 bit data field corresponds to one of the timers. Thus, the value of Timer 0 extends the Level 1 Busy that arrives on TSC channel 0 and so on. The register addresses and the four 16-bit registers for each TSC in the system are listed in the table below. The VME address assumes that the Trigger Hub Controller has a base address of 0x800000. TSC VME address data[15..8] data[7..0] Hex Value Range --- ----------- ----------- ---------- --------------- 0 0x800416 Timer 1 Timer 0 0x0000 - 0x3f3f 0 0x80041e Timer 3 Timer 2 0x0000 - 0x3f3f 0 0x800436 Timer 5 Timer 4 0x0000 - 0x3f3f 0 0x80043e Timer 7 Timer 6 0x0000 - 0x3f3f 1 0x800456 Timer 1 Timer 0 0x0000 - 0x3f3f 1 0x80045e Timer 3 Timer 2 0x0000 - 0x3f3f 1 0x800476 Timer 5 Timer 4 0x0000 - 0x3f3f 1 0x80047e Timer 7 Timer 6 0x0000 - 0x3f3f 2 0x800496 Timer 1 Timer 0 0x0000 - 0x3f3f 2 0x80049e Timer 3 Timer 2 0x0000 - 0x3f3f 2 0x8004b6 Timer 5 Timer 4 0x0000 - 0x3f3f 2 0x8004be Timer 7 Timer 6 0x0000 - 0x3f3f 3 0x8004d6 Timer 1 Timer 0 0x0000 - 0x3f3f 3 0x8004de Timer 3 Timer 2 0x0000 - 0x3f3f 3 0x8004f6 Timer 5 Timer 4 0x0000 - 0x3f3f 3 0x8004fe Timer 7 Timer 6 0x0000 - 0x3f3f 4 0x800516 Timer 1 Timer 0 0x0000 - 0x3f3f 4 0x80051e Timer 3 Timer 2 0x0000 - 0x3f3f 4 0x800536 Timer 5 Timer 4 0x0000 - 0x3f3f 4 0x80053e Timer 7 Timer 6 0x0000 - 0x3f3f 5 0x800556 Timer 1 Timer 0 0x0000 - 0x3f3f 5 0x80055e Timer 3 Timer 2 0x0000 - 0x3f3f 5 0x800576 Timer 5 Timer 4 0x0000 - 0x3f3f 5 0x80057e Timer 7 Timer 6 0x0000 - 0x3f3f 6 0x800596 Timer 1 Timer 0 0x0000 - 0x3f3f 6 0x80059e Timer 3 Timer 2 0x0000 - 0x3f3f 6 0x8005b6 Timer 5 Timer 4 0x0000 - 0x3f3f 6 0x8005be Timer 7 Timer 6 0x0000 - 0x3f3f 7 0x8005d6 Timer 1 Timer 0 0x0000 - 0x3f3f 7 0x8005de Timer 3 Timer 2 0x0000 - 0x3f3f 7 0x8005f6 Timer 5 Timer 4 0x0000 - 0x3f3f 7 0x8005fe Timer 7 Timer 6 0x0000 - 0x3f3f 8 0x800616 Timer 1 Timer 0 0x0000 - 0x3f3f 8 0x80061e Timer 3 Timer 2 0x0000 - 0x3f3f 8 0x800636 Timer 5 Timer 4 0x0000 - 0x3f3f 8 0x80063e Timer 7 Timer 6 0x0000 - 0x3f3f 9 0x800656 Timer 1 Timer 0 0x0000 - 0x3f3f 9 0x80065e Timer 3 Timer 2 0x0000 - 0x3f3f 9 0x800676 Timer 5 Timer 4 0x0000 - 0x3f3f 9 0x80067e Timer 7 Timer 6 0x0000 - 0x3f3f 10 0x800696 Timer 1 Timer 0 0x0000 - 0x3f3f 10 0x80069e Timer 3 Timer 2 0x0000 - 0x3f3f 10 0x8006b6 Timer 5 Timer 4 0x0000 - 0x3f3f 10 0x8006be Timer 7 Timer 6 0x0000 - 0x3f3f 11 0x8006d6 Timer 1 Timer 0 0x0000 - 0x3f3f 11 0x8006de Timer 3 Timer 2 0x0000 - 0x3f3f 11 0x8006f6 Timer 5 Timer 4 0x0000 - 0x3f3f 11 0x8006fe Timer 7 Timer 6 0x0000 - 0x3f3f 12 0x800716 Timer 1 Timer 0 0x0000 - 0x3f3f 12 0x80071e Timer 3 Timer 2 0x0000 - 0x3f3f 12 0x800736 Timer 5 Timer 4 0x0000 - 0x3f3f 12 0x80073e Timer 7 Timer 6 0x0000 - 0x3f3f 13 0x800756 Timer 1 Timer 0 0x0000 - 0x3f3f 13 0x80075e Timer 3 Timer 2 0x0000 - 0x3f3f 13 0x800776 Timer 5 Timer 4 0x0000 - 0x3f3f 13 0x80077e Timer 7 Timer 6 0x0000 - 0x3f3f 14 0x800796 Timer 1 Timer 0 0x0000 - 0x3f3f 14 0x80079e Timer 3 Timer 2 0x0000 - 0x3f3f 14 0x8007b6 Timer 5 Timer 4 0x0000 - 0x3f3f 14 0x8007be Timer 7 Timer 6 0x0000 - 0x3f3f 15 0x8007d6 Timer 1 Timer 0 0x0000 - 0x3f3f 15 0x8007de Timer 3 Timer 2 0x0000 - 0x3f3f 15 0x8007f6 Timer 5 Timer 4 0x0000 - 0x3f3f 15 0x8007fe Timer 7 Timer 6 0x0000 - 0x3f3f The following is an example. To extend the Level 1 Busy for TSC 0: on channel 0 by 0.6 us, on channel 1 by 1.0 us, on channel 2 by 1.6 us, on channel 3 by 2.0 us, on channel 4 by 2.5 us, on channel 5 by 3.2 us, on channel 6 by 4.0 us, on channel 7 by 5.2 us. Load the following data into the VME registers: TSC VME Address VME data[15..0] --- ----------- --------------- 0 0x800416 0x0a06 0 0x80041e 0x1410 0 0x800436 0x2019 0 0x80043e 0x3428 To accomplish this modification to extend the trailing edge of the L1_Busy the following is done. The JTAG configuration file setup for the 3 Altera parts on the Status Concentrator is as follows. 1 EPM9560A addtop.pof checksum A19634 2 EPM9560A status_top.pof checksum 9F7A04 3 EPM9560A status_top.pof checksum 9F7A04 The modifications to the printed circuit board are as follows. Each pin 8 of ICs U39, U38, U37, U36, U35, U34, U33, and U24 is unsoldered and lifted so that the DS36950 is no longer driving the status 7 signal. The status 0 signals are routed internally through Altera U11 and U14 to the status 7 signals which then become outputs. The extended versions of the Level 1 Busy(s) will end up at the spare 2 connector which is the 4th edge connector from the top on the TSC. Normal Level 1 Busy(s) continue to come from the 3rd edge connector from the top on the TSC. These instructions for the TSC modification and the control of the SVX Sequencer Controller L1_Busy "Delay" in the SCL Hub-End Status Concentrator module were written by Ted Zmuda (along with the firmware to accomplish this function).