Using SCL Receivers --------------------- Rev. 29-NOV-2000 Now that most systems have some experience using the SCL Receiver I wanted to send out a summary of what we have learned working with this board. The current version (6-JUNE-2000) of the SCL Receiver documentation is on the web at: http://www-ese.fnal.gov/d0trig/default.htm Points to check when using the SCL Receiver: 1. All data comes out the the SCL Receiver with zero setup time with respect to the rising edge of the 7 MHz Clk. Most systems will be routing this SCL data to an FPGA where it is ingested by latches in the input cells of this FPGA. These input latches can be clocked by a delayed version of the 7 MHz Clk or by the falling edge of this clock. 2. You need to AND L1_Period with L1_ACCEPT to this Geo Section. L1_Period (P1 pin 40) is asserted anytime the Trigger FW issues a L1 Accept. You need to AND this with the L1_Accept (P1 pin 41) to make the appropriate signal to indicate that an L1 Accept has been issued and it is to your Geographic Section. 3. You need to AND L2_Period with L2_Accept to this Geo Section. You need to AND L2_Period with L2_Reject to this Geo Section. L2_Period (P1 pin 44) is asserted anytime the Trigger FW issues a L2 Decision. You need to AND the L2_Period with L2_Accept (P1 pin 47) and with L2_Reject (P1 pin 46) to make the appropriate signals to indicate that your Geographic Section is being told to L2 Accept or L2 Reject the oldest event in its FIFO of events awaiting their L2 Decisions. 4. Connect SCL_SYNCERROR to SYNC_LOST SCL_SYNCERROR (P1 pin 4) is an output from the SCL Receiver that goes high when the SCL Receiver has lost synchronization with the incoming serial data stream. It will remain high until the SCL Receiver is reset with the SCL_ACK signal (see below). SYNC_LOSS (P1 pin 57) is an input to the SCL Receiver. This signal is returned to the SCL Hub-End on the flat Status Cable. By connecting SCL_SYNCERROR to SYNC_LOST you allow the Trigger Control Computer to determine which Geographic Sections are currently receiving a good stream of SCL data. This is useful in the overall management of the DAQ System in D-Zero. For example when the COOR program tells the Trigger Control Computer to "Begin Run", TCC can first verify that all of the required Geographic Sections are currently receiving a good SCL signal before issuing any triggers. 5. Reset of the SCL Receiver with the SCL_ACK signal At power up the SCL Receiver must be told to lock on to the serial input data stream and to clear its error flags. If at anytime during operation the SCL Receiver should lose lock with its serial input data stream then it needs to be told again to lock on and clear its error flags. The way that you tell the SCL Receiver to try to lock onto the serial input stream is to pulse the SCL_ACK input (P2 pin 4) high for a minimum of 38 nsec (132 nsec is a rational length pulse). The SCL Receiver will perform a 12 msec long initialization process during which it should be able to lock on to the input serial data stream. Once the receiver is locked on it will drop its SCL_SYNCERROR signal to let you know that it has locked and it will start sending out the 7 MHz clock and parallel SCL data. 6. Automatic Re-Lock to the Serial Data Stream If lock is ever lost during normal operation then it is useful to have designed your system to enable automatic re-locking to the serial input stream. Dean Schamberger has developed and implemented this in his controller and it works very nicely. The setup in Dean's system is the following: o If SCL_SYNCERROR has been asserted for longer than some minimum period (Dean looks for 5 consecutive ticks of 132 nsec with SYNCERROR asserted, about 660 nsec, before he declares that synchronization has been lost) then o Pulse the SCL_ACK high for a minimum of 38 nsec (132 nsec is a rational length pulse) then o Wait to give the SCL Receiver time to lock onto the serial input data and drop its SYNCERROR signal. This should only take 12 msec. Right now Dean is giving the SCL Receiver about 100 msec to lock onto the serial input stream before he checks the SYNCERROR signal again. The big advantage of being able to automatically re-lock to the SCL signal is that if lock is ever lost this gives us the fastest way possible to get the system going again. Remember that if lock is lost you will not get a 7 MHz clock output from the SCL Receiver to step your FPGA through a re-lock sequence. You do get the 50.103 MHz output from the SCL Receiver even when lock is lost. Without the SCL Receiver being locked to the Serial Data Stream, the Trigger FW can not even tell the Geographic Section to Initialize, i.e. we could not even begin a recovery from the errors caused when lock is lost.