// THE Card "Seed" MSA FPGA User Constraint File (good for FM and not FM) // MSU HEP 23 October 1996 // Last edit 26 November 1997 setup for FIRC FM MSA #4 // Last edit 1 December 1997 set MSA pins for FM MSA #4 // Last edit 1 December 1997 add timing constraints // Last edit 6 December 1997 constrain Quad_Done // Last edit 20 December 1997 must move Quad Done to 37 ns for Frame Enb Blk // Last edit 16 September1998 modified for helper function // 4 December 1998 modified to track helper fn changes // 8 December 1999 modified for L2 Helper Function // 21 April 2000 add Waiting_for_L2BAD output // 1 JULY 2002 D.E. just clean up the format // 1 JULY 2002 D.E. Tighten the Helper Clock Timing // -------------------------------------------------------------------------- // Timing Constraints // -------------------------------------------------------------------------- // The main clock in this design is the L2_Helper_Clock, running at // 7 * 18.8 ns = 136 ns = 7.6 MHz. NET "L2_Helper_Clock" TNM = Helper_Clk ; TIMESPEC TS_Helper_Clk = PERIOD Helper_Clk 85.0 ns high 15.0 ns ; // Additional constraints to cover the OCB. Each state in the state // engine lasts for 75 ns. // Writing. The data is input 75 ns before the write strobe is asserted. NET OCB_Data_PAD* OFFSET = IN 75 ns BEFORE "OCB_Write_Strobe_PAD*" ; // Reading. The request must propagate from the VME interface FPGA to the // PBS FPGA (estimate 25 ns), and the data must propagate back to the VME // interface FPGA (estimate 25 ns). // This leaves 100 ns for the data to be retrieved and put on to the OCB. TIMEGRP Direct_Pad = PADS ( "OCB_Direction_PAD" ) ; TIMEGRP Data_Out_Pads = PADS ( OCB_Data_PAD* ) ; // Only consider the paths through the register address decoder. NET Read_Reg* TPTHRU = Read_Reg ; TIMESPEC TS_Direct_In_to_Data_Out = FROM Direct_Pad THRU Read_Reg TO Data_Out_Pads 100 ns ; // -------------------------------------------------------------------------- // Special Characteristics Constraints // -------------------------------------------------------------------------- NET "Input_TRM_Read_Enable_PAD*" FAST; NET "Send_L2_Decision_PAD*" FAST; NET "Send_L2_Decision_to_SCL_PAD*" FAST; NET "L3_Cont_Data_Latch_Enable_PAD*" FAST; NET "L3_Data_Strobe_Inc_Xfr_Num_PAD*" FAST; NET "L2_Maginot_Line_PAD*" FAST; NET "L2_Capture_Monitor_Data_PAD*" FAST; NET "L2_Answer_TRM_Write_Clock_PAD*" FAST; // -------------------------------------------------------------------------- // Pinout Constraints // -------------------------------------------------------------------------- // Note: It is necessary to comment out certain lines to use this file // in the FM, and to comment out other lines to use this file in // non-FM cards. See comments at end of lines. // On-Card Bus and Timing Signals: DO NOT MODIFY (except FM/not FM changes) // note: OCB_Reg_Addr_PAD(8) present only on FM but not used on any card NET "OCB_Chip_Sel_PAD*" LOC = "P142" ; NET "OCB_Write_Strobe_PAD*" LOC = "P183" ; NET "OCB_Direction_PAD" LOC = "P136" ; NET "OCB_Reg_Addr_PAD(0)" LOC = "P169" ; NET "OCB_Reg_Addr_PAD(1)" LOC = "P168" ; NET "OCB_Reg_Addr_PAD(2)" LOC = "P167" ; NET "OCB_Reg_Addr_PAD(3)" LOC = "P165" ; NET "OCB_Reg_Addr_PAD(4)" LOC = "P164" ; NET "OCB_Reg_Addr_PAD(5)" LOC = "P163" ; NET "OCB_Reg_Addr_PAD(6)" LOC = "P162" ; NET "OCB_Reg_Addr_PAD(7)" LOC = "P160" ; NET "OCB_Data_PAD(0)" LOC = "P177" ; NET "OCB_Data_PAD(1)" LOC = "P173" ; NET "OCB_Data_PAD(2)" LOC = "P159" ; NET "OCB_Data_PAD(3)" LOC = "P152" ; NET "OCB_Data_PAD(4)" LOC = "P148" ; NET "OCB_Data_PAD(5)" LOC = "P141" ; NET "OCB_Data_PAD(6)" LOC = "P129" ; NET "OCB_Data_PAD(7)" LOC = "P123" ; NET "OCB_Data_PAD(8)" LOC = "P176" ; NET "OCB_Data_PAD(9)" LOC = "P172" ; NET "OCB_Data_PAD(10)" LOC = "P155" ; NET "OCB_Data_PAD(11)" LOC = "P154" ; NET "OCB_Data_PAD(12)" LOC = "P145" ; NET "OCB_Data_PAD(13)" LOC = "P138" ; NET "OCB_Data_PAD(14)" LOC = "P131" ; NET "OCB_Data_PAD(15)" LOC = "P126" ; NET "FPGA_OE_PAD*" LOC = "P187" ; NET "Chip_Status_PAD*" LOC = "P174" ; // MSA Input Signals, // these are specific to this particular FPGA design NET "L2_BAD_PAD(0)" LOC = "P54" ; # MS_I 16 NET "L2_BAD_PAD(1)" LOC = "P55" ; # MS_I 17 NET "Live_Crossing_PAD" LOC = "P66" ; # MS_I 21 NET "L1_STF_FIFO_Not_Empty_PAD" LOC = "P69" ; # MS_I 23 NET "L2_Ans_FIFO_Not_Empty_PAD" LOC = "P71" ; # MS_I 25 NET "Transfer_to_L3_Reqd_PAD" LOC = "P73" ; # MS_I 27 NET "L2_Cap_Monit_Data_Request_PAD" LOC = "P76" ; # MS_I 29 NET "L2_Global_Answer_Strobe_PAD" LOC = "P78" ; # MS_I 31 NET "L2_Helper_Clock_PAD" LOC = "P239" ; # MS_I 51 (SGCK) // MSA Output signals, // these are specific to this particular FPGA design NET "Input_TRM_Read_Enable_PAD(0)" LOC = "P100" ; # MS_O 0 NET "Input_TRM_Read_Enable_PAD(1)" LOC = "P99" ; # MS_O 1 NET "Send_L2_Decision_PAD(0)" LOC = "P97" ; # MS_O 2 NET "Send_L2_Decision_PAD(1)" LOC = "P96" ; # MS_O 3 NET "L3_Cont_Data_Latch_Enable_PAD(0)" LOC = "P95" ; # MS_O 4 NET "L3_Cont_Data_Latch_Enable_PAD(1)" LOC = "P94" ; # MS_O 5 NET "L3_Data_Strobe_Inc_Xfr_Num_PAD(0)" LOC = "P93" ; # MS_O 6 NET "L2_Maginot_Line_PAD(0)" LOC = "P92" ; # MS_O 7 NET "L2_Maginot_Line_PAD(1)" LOC = "P88" ; # MS_O 8 NET "L2_Capture_Monitor_Data_PAD(0)" LOC = "P87" ; # MS_O 9 NET "Waiting_for_L2BAD_PAD" LOC = "P86" ; # MS_O 10 // following 5 signals are only temporary for commissioning testing NET "Send_L2_Decision_PAD(3)" LOC = "P85" ; # MS_O 11 NET "L3_Cont_Data_Latch_Enable_PAD(2)" LOC = "P84" ; # MS_O 12 NET "L3_Data_Strobe_Inc_Xfr_Num_PAD(3)" LOC = "P82" ; # MS_O 13 NET "L2_Capture_Monitor_Data_PAD(4)" LOC = "P81" ; # MS_O 14 NET "L2_Answer_TRM_Write_Clock_PAD(8)" LOC = "P79" ; # MS_O 15 // end of temporary signals NET "L2_Answer_TRM_Write_Clock_PAD(0)" LOC = "P225" ; # MS_O 16 NET "L2_Answer_TRM_Write_Clock_PAD(1)" LOC = "P224" ; # MS_O 17 NET "L2_Answer_TRM_Write_Clock_PAD(2)" LOC = "P223" ; # MS_O 18 NET "L2_Answer_TRM_Write_Clock_PAD(3)" LOC = "P221" ; # MS_O 19 NET "L2_Answer_TRM_Write_Clock_PAD(4)" LOC = "P220" ; # MS_O 20 NET "L2_Answer_TRM_Write_Clock_PAD(5)" LOC = "P218" ; # MS_O 21 NET "L2_Answer_TRM_Write_Clock_PAD(6)" LOC = "P217" ; # MS_O 22 NET "L2_Answer_TRM_Write_Clock_PAD(7)" LOC = "P216" ; # MS_O 23 NET "Send_L2_Decision_PAD(2)" LOC = "P214" ; # MS_O 25 NET "Send_L2_Decision_to_SCL_PAD" LOC = "P213" ; # MS_O 26 NET "L3_Data_Strobe_Inc_Xfr_Num_PAD(1)" LOC = "P210" ; # MS_O 27 NET "L3_Data_Strobe_Inc_Xfr_Num_PAD(2)" LOC = "P209" ; # MS_O 28 NET "L2_Capture_Monitor_Data_PAD(1)" LOC = "P208" ; # MS_O 29 NET "L2_Capture_Monitor_Data_PAD(2)" LOC = "P207" ; # MS_O 30 NET "L2_Capture_Monitor_Data_PAD(3)" LOC = "P206" ; # MS_O 31 // Everything Bellow Here Is Signals That Are Not Used In This Design // NET "OCB_Reg_Addr_PAD(8)" LOC = "P157" ; # not used // NET "HQ_Timing_PAD(0)" LOC = "P2" ; // NET "HQ_Timing_PAD(1)" LOC = "P63" ; // NET "HQ_Timing_PAD(2)" LOC = "P124" ; // NET "HQ_Timing_PAD(3)" LOC = "P184" ; // High-Speed Read Out Signals: DO NOT MODIFY (except FM/not FM changes) // High Speed Readout Control and Data Bus Lines, Capture Control Lines // DO NOT MODIFY (except FM/not FM changes) and to exclude // NET "Capture_HSRO_Data_PAD*" LOC = "P133" ; # not on FM // NET "Capture_Monitor_Data_PAD*" LOC = "P134" ; # not on FM // NET "HSRO_DCE_In_PAD*" LOC = "P89" ; # FM only // NET "HSRO_DCE_In_PAD*" LOC = "P28" ; # not on FM // NET "HSRO_DCE_Out_PAD*" LOC = "P64" ; // NET "HSRO_Data_PAD(0)" LOC = "P178" ; // NET "HSRO_Data_PAD(1)" LOC = "P171" ; // NET "HSRO_Data_PAD(2)" LOC = "P156" ; // NET "HSRO_Data_PAD(3)" LOC = "P147" ; // NET "HSRO_Data_PAD(4)" LOC = "P146" ; // NET "HSRO_Data_PAD(5)" LOC = "P139" ; // NET "HSRO_Data_PAD(6)" LOC = "P128" ; // NET "HSRO_Data_PAD(7)" LOC = "P125" ; // NET "HSRO_Data_PAD(8)" LOC = "P175" ; // NET "HSRO_Data_PAD(9)" LOC = "P170" ; // NET "HSRO_Data_PAD(10)" LOC = "P153" ; // NET "HSRO_Data_PAD(11)" LOC = "P149" ; // NET "HSRO_Data_PAD(12)" LOC = "P144" ; // NET "HSRO_Data_PAD(13)" LOC = "P137" ; // NET "HSRO_Data_PAD(14)" LOC = "P130" ; // NET "HSRO_Data_PAD(15)" LOC = "P127" ; // NET "HSRO_Data_Valid_PAD*" LOC = "P132" ; // Dedicated and/or Reserved Signals: DO NOT MODIFY // (note: these signals not explicitly called out in FPGA design) // NET "CCLK goes here" LOC = "P179" ; // NET "DONE -- Chip_Configed" LOC = "P120" ; // NET "ERR/INIT* goes here" LOC = "P89" ; # HDI* on FM // NET "LDC* goes here" LOC = "P68" ; // NET "M0 -- VDD" LOC = "P60" ; // NET "M1 -- GROUND" LOC = "P58" ; // NET "M2 -- VDD" LOC = "P62" ; // NET "PROG* -- Config_Chip*" LOC = "P122" ; // NET "TCK goes here" LOC = "P7" ; // NET "TDI goes here" LOC = "P6" ; // NET "TDO goes here" LOC = "P181" ; // NET "TMS goes here" LOC = "P17" ; // NET "formerly OCB_Reg_Addr_PAD(8)" LOC = "P157" ; // MSA Input and MSA Output signals, these are specific to this // particular FPGA design // NET LOC = "P35" ; # MS_I 0 // NET LOC = "P36" ; # MS_I 1 // NET LOC = "P38" ; # MS_I 2 // NET LOC = "P39" ; # MS_I 3 // NET LOC = "P41" ; # MS_I 4 // NET LOC = "P42" ; # MS_I 5 // NET LOC = "P43" ; # MS_I 6 // NET LOC = "P44" ; # MS_I 7 // NET LOC = "P46" ; # MS_I 8 // NET LOC = "P47" ; # MS_I 9 // NET LOC = "P48" ; # MS_I 10 // NET LOC = "P49" ; # MS_I 11 // NET LOC = "P50" ; # MS_I 12 // NET LOC = "P51" ; # MS_I 13 // NET LOC = "P52" ; # MS_I 14 // NET LOC = "P53" ; # MS_I 15 // NET LOC = "P56" ; # MS_I 18 // NET "Tick_Clock_PAD" LOC = "P57" ; # MS_I 19 (SGCK) // NET LOC = "P65" ; # MS_I 20 // NET LOC = "P67" ; # MS_I 22 // NET LOC = "P70" ; # MS_I 24 // NET LOC = "P72" ; # MS_I 26 // NET LOC = "P74" ; # MS_I 28 // NET LOC = "P77" ; # MS_I 30 // NET LOC = "P27" ; # MS_I 32 // NET LOC = "P26" ; # MS_I 33 // NET LOC = "P25" ; # MS_I 34 // NET LOC = "P24" ; # MS_I 35 // NET LOC = "P23" ; # MS_I 36 // NET LOC = "P21" ; # MS_I 37 // NET LOC = "P20" ; # MS_I 38 // NET LOC = "P18" ; # MS_I 39 // NET LOC = "P16" ; # MS_I 40 // NET LOC = "P15" ; # MS_I 41 // NET LOC = "P13" ; # MS_I 42 // NET LOC = "P12" ; # MS_I 43 // NET LOC = "P11" ; # MS_I 44 // NET LOC = "P10" ; # MS_I 45 // NET LOC = "P9" ; # MS_I 46 // NET LOC = "P8" ; # MS_I 47 // NET LOC = "P5" ; # MS_I 48 // NET LOC = "P4" ; # MS_I 49 // NET LOC = "P3" ; # MS_I 50 // NET LOC = "P238" ; # MS_I 52 // NET LOC = "P237" ; # MS_I 53 // NET LOC = "P236" ; # MS_I 54 // NET LOC = "P235" ; # MS_I 55 // NET LOC = "P234" ; # MS_I 56 // NET LOC = "P233" ; # MS_I 57 // NET LOC = "P232" ; # MS_I 58 // NET LOC = "P231" ; # MS_I 59 // NET LOC = "P230" ; # MS_I 60 // NET LOC = "P229" ; # MS_I 61 // NET LOC = "P228" ; # MS_I 62 // NET LOC = "P226" ; # MS_I 63 // NET LOC = "P215" ; # MS_O 24