# This Command File is called match_on_ten.cmd # This Command File will cause the ADF to send the digital Et # value of 0x00 from all its channel to the TABs on all Ticks # except for Tick 10. Tick 10 is the 2nd Live Beam Crossing. # # On Tick 10 the Et value for channels 0,0 EM and 0,0 HD # will be 0xff. # # On Tick 10 all other ADF channels will continue to output # the Et value 0x00. # This Command File is executed after the ADF has been setup # to provide normal real BLS signal data to the TABs. # This file does the following: # # 1. The Simulation data value 0xff is loaded into the Raw ADC # Memory Block for Tick 10 for just channels 0,0 EM and 0,0 HD. # All other locations in the Raw ADC Memory Block remain at the # value zero which is how they were initialized. # # 2. This file starts all 32 channels on the ADF-2 card sending out # Simulation Data from their Raw ADC Memory Blocks (instead of # real BLS signal data). i.e.: # # set each channel so that its Raw ADC Mem Blk data is NOT overwritten # then set each channel's Input Mux to select Simulation Data # then start the Address Generator for the Raw ADC Mem Blk. # # Original Date: 26-JULY-2005 Use common utility to get Card # Coordinates, etc. # Current Ver: import GetCardCoord #------------------------------------------------------------------------ # These coordinates select the location of the ADF card to setup MasterNum = GetCardCoord.MasterNum ( ArgDict ) SlaveNum = GetCardCoord.SlaveNum ( ArgDict ) SlotNum = GetCardCoord.SlotNum ( ArgDict ) #------------------------------------------------------------------------ # The Simulation data value 0xff is loaded into the Raw ADC Memory Block # for Tick 10 for just channels 0,0 EM and 0,0 HD. # The Raw ADC Memory Block for 0,0 EM starts at address 2048. # The simulation data for the 2nd LvBX is stored at address 2084. Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 2084, DataOut = 255 ) # The Raw ADC Memory Block for 0,0 HD starts at address 3072. # The simulation data for the 2nd LvBX is stored at address 3108. Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 3108, DataOut = 255 ) # Next setup the "Input Section control register" for all 32 channels # so that the Simulation Data from the Raw ADC Memory Block is selected, # that is: # # set the Stop Comparators Reference Threshold to 0 # set the ADC Data Delay to mid scale i.e. 8 # set the 0,0 EM Input Multiplexer to select Simulation Data # set the Write Enable for the Raw ADC Mem Blk to directly follow the # Global Write Enable signal from the Raw ADC Mem Blk Address Generator # The first 8 Trigger Towers are on Data Path FPGA F0. # 0,0 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0x0302, DataOut = 0x1800 ) # 0,0 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0x0303, DataOut = 0x1800 ) # 0,1 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0x2302, DataOut = 0x1800 ) # 0,1 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0x2303, DataOut = 0x1800 ) # 0,2 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0x4302, DataOut = 0x1800 ) # 0,2 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0x4303, DataOut = 0x1800 ) # 0,3 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0x6302, DataOut = 0x1800 ) # 0,3 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0x6303, DataOut = 0x1800 ) # 1,0 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0x8302, DataOut = 0x1800 ) # 1,0 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0x8303, DataOut = 0x1800 ) # 1,1 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0xa302, DataOut = 0x1800 ) # 1,1 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0xa303, DataOut = 0x1800 ) # 1,2 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0xc302, DataOut = 0x1800 ) # 1,2 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0xc303, DataOut = 0x1800 ) # 1,3 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0xe302, DataOut = 0x1800 ) # 1,3 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 0xe303, DataOut = 0x1800 ) # The final 8 Trigger Towers are on Data Path FPGA F1. # 2,0 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0x0302, DataOut = 0x1800 ) # 2,0 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0x0303, DataOut = 0x1800 ) # 2,1 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0x2302, DataOut = 0x1800 ) # 2,1 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0x2303, DataOut = 0x1800 ) # 2,2 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0x4302, DataOut = 0x1800 ) # 2,2 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0x4303, DataOut = 0x1800 ) # 2,3 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0x6302, DataOut = 0x1800 ) # 2,3 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0x6303, DataOut = 0x1800 ) # 3,0 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0x8302, DataOut = 0x1800 ) # 3,0 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0x8303, DataOut = 0x1800 ) # 3,1 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0xa302, DataOut = 0x1800 ) # 3,1 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0xa303, DataOut = 0x1800 ) # 3,2 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0xc302, DataOut = 0x1800 ) # 3,2 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0xc303, DataOut = 0x1800 ) # 3,3 EM Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0xe302, DataOut = 0x1800 ) # 3,3 HD Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 0xe303, DataOut = 0x1800 ) # The final step is to setup and then start running the Address Generator # for the Raw ADC Memory Block. This will need to be done for both of # the Data Path FPGA's on the ADF-2 card. # Start with Data Path FPGA F0, # Set the highest address that the Address Generator will make # in its sequence of Raw ADC Memory Block Addresses. # # Recall that the Address Generator always starts with address = 0 # Recall that the value loaded into this "highest address" register # must be 1 less than the highest address that the Generator will # issue. # Recall Ticks are numbered 1:159 4 x 159 = 636 636 - 2 = 634 # Recall this is Global Register #1 Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 513, DataOut = 634 ) # Now work with the control register for the Raw ADC Memory Block # Address Generator. This is Global Register #0. # Get the Raw ADC Mem Blk Address Generator ready to start: # repeat the Address Sequence until told to stop i.e. bit #1 hi # do not stop on Save_Mon_Data i.e. bit #2 low # do NOT assert the Global Raw ADC Mem Blk Write Enable i.e. bit #3 low Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 512, DataOut = 0x0002 ) # Trigger the Raw ADC Mem Blk Address Generator to start running Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 512, DataOut = 0x0003 ) # Stop triggering the Raw ADC Mem Blk Address Generator Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 0, RegAddr = 512, DataOut = 0x0002 ) # Data Path FPGA F0 now has its Raw ADC Memory Block Address Generator # setup and running correctly. Now do the same steps for Data Path # FPGA F1. # Set the highest address that the Address Generator will make # in its sequence of Raw ADC Memory Block Addresses. Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 513, DataOut = 634 ) # Now setup the control register for this Address Generator and # start it running. Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 512, DataOut = 0x0002 ) # Trigger the Raw ADC Mem Blk Address Generator to start running Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 512, DataOut = 0x0003 ) # Stop triggering the Raw ADC Mem Blk Address Generator Rio_Write( MasterNum = MasterNum, SlaveNum = SlaveNum, SlotNum = SlotNum, ChipNum = 1, RegAddr = 512, DataOut = 0x0002 )