// SCL Helper FPGA User Constraint File // ------------ // This is a XC4013L design for FPGA Site #13 on an FM THE-Card. // Last edit 16 Sep 1999 Set up for SCL Helper // 27-AUG-02 Clean up the format of this file. // Tighten up all the timing. // -------------------------------------------------------------------------- // Timing Constraints // -------------------------------------------------------------------------- // There is a Beam Crossing Clock in this design. Most things run on it. NET "SCL_Helper_Clock" TNM = BX_Clock ; TIMESPEC TS_BX_Clock = PERIOD BX_Clock 80.0 ns high 15.5 ns ; // Constrain theCMC Markers vs. BX_Clock arrival time. We guarantee // externally that the CMC Markers arrive 30 ns before the BX_Clock NET CMC*Marker_PAD OFFSET = IN 20 ns BEFORE SCL_Helper_Clock_PAD ; // Additional constraints to cover the OCB. Each state in the state // engine lasts for 75 ns. // Writing. The data is input 75 ns before the write strobe is asserted. NET OCB_Data_PAD* OFFSET = IN 25 ns BEFORE "OCB_Write_Strobe_PAD*" ; // Reading. The request must propagate from the VME interface FPGA to the // PBS FPGA (estimate 25 ns), and the data must propagate back to the VME // interface FPGA (estimate 25 ns). // This leaves 100 ns for the data to be retrieved and put on to the OCB. TIMEGRP Direct_Pad = PADS ( "OCB_Direction_PAD" ) ; TIMEGRP Data_Out_Pads = PADS ( OCB_Data_PAD* ) ; // Only consider the paths through the register address decoder. NET Read_Reg* TPTHRU = Read_Reg ; TIMESPEC TS_Direct_In_to_Data_Out = FROM Direct_Pad THRU Read_Reg TO Data_Out_Pads 80 ns ; // -------------------------------------------------------------------------- // Special Characteristics Constraints // -------------------------------------------------------------------------- NET SCL_BOT_Marker_PAD FAST; NET SCL_BX_Marker_PAD FAST; NET SCL_SyncG_Marker_PAD FAST; NET SCL_Cos_Marker_PAD FAST; NET SCL_Spare_Marker_PAD FAST; NET SCL_L1_Accept_PAD FAST; NET SCL_L2_Decision_PAD FAST; // * = wild card NET SCL_Initialize_PAD* FAST; NET FW_BOT_Marker_PAD FAST; NET FW_BX_Marker_PAD FAST; NET FW_SyncG_Marker_PAD FAST; NET FW_Cos_Marker_PAD FAST; NET FW_Spare_Marker_PAD FAST; // -------------------------------------------------------------------------- // Pinout Constraints // -------------------------------------------------------------------------- // Note: This is a XC4013L design for FPGA Site #13 on an FM THE-Card. NET "OCB_Chip_Sel_PAD*" LOC = "P142" ; NET "OCB_Write_Strobe_PAD*" LOC = "P183" ; NET "OCB_Direction_PAD" LOC = "P136" ; NET "OCB_Reg_Addr_PAD(0)" LOC = "P169" ; NET "OCB_Reg_Addr_PAD(1)" LOC = "P168" ; NET "OCB_Reg_Addr_PAD(2)" LOC = "P167" ; NET "OCB_Reg_Addr_PAD(3)" LOC = "P165" ; NET "OCB_Reg_Addr_PAD(4)" LOC = "P164" ; NET "OCB_Reg_Addr_PAD(5)" LOC = "P163" ; NET "OCB_Reg_Addr_PAD(6)" LOC = "P162" ; NET "OCB_Reg_Addr_PAD(7)" LOC = "P160" ; NET "OCB_Data_PAD(0)" LOC = "P177" ; NET "OCB_Data_PAD(1)" LOC = "P173" ; NET "OCB_Data_PAD(2)" LOC = "P159" ; NET "OCB_Data_PAD(3)" LOC = "P152" ; NET "OCB_Data_PAD(4)" LOC = "P148" ; NET "OCB_Data_PAD(5)" LOC = "P141" ; NET "OCB_Data_PAD(6)" LOC = "P129" ; NET "OCB_Data_PAD(7)" LOC = "P123" ; NET "OCB_Data_PAD(8)" LOC = "P176" ; NET "OCB_Data_PAD(9)" LOC = "P172" ; NET "OCB_Data_PAD(10)" LOC = "P155" ; NET "OCB_Data_PAD(11)" LOC = "P154" ; NET "OCB_Data_PAD(12)" LOC = "P145" ; NET "OCB_Data_PAD(13)" LOC = "P138" ; NET "OCB_Data_PAD(14)" LOC = "P131" ; NET "OCB_Data_PAD(15)" LOC = "P126" ; NET "FPGA_OE_PAD*" LOC = "P187" ; NET "Chip_Status_PAD*" LOC = "P174" ; // MSA Input and MSA Output signals, these are specific to this // SCL Helper FPGA design // Here we refer to signal NOT by MSA Number but by functional // name // MSA Inputs // No MSA Inputs go *only* to FM Card FPGA Site #13 // The cleanest MSA Inputs available to this FPGA also go to MSA // FPGA #1 (which is in the same column). Those MSA inputs all // come from P3, and are: // 79:71 (9 inputs) - on one Rear PB conn // 87:81 (7 inputs) - these 2 groups are on a // 95:90 (6 inputs) - single Rear PB conn // 103:101 (3 inputs) - on one Rear PB conn // 127:112 (16 inputs) - a full Rear PB conn // Note that MSA Input 95 is an SGCLK input // MSA Inputs MSA_In NET "FW_L1_Accept_PAD" LOC = "P97" ; #77 NET "FW_L2_Decision_PAD" LOC = "P100" ; #79 NET "CMC_BX_Marker_PAD" LOC = "P114" ; #91 NET "CMC_BOT_Marker_PAD" LOC = "P116" ; #93 NET "SCL_Helper_Clock_PAD" LOC = "P118" ; #95 NET "SCL_Init_Ack_PAD" LOC = "P218" ; #101 NET "SCL_GB_SynErr_PAD" LOC = "P217" ; #102 NET "SCL_IRQ_PAD" LOC = "P216" ; #103 NET "CMC_Spare_Marker_PAD" LOC = "P198" ; #117 NET "CMC_SyncG_Marker_PAD" LOC = "P194" ; #119 NET "CMC_Cos_Marker_PAD" LOC = "P192" ; #121 // MSA Outputs // 8 outputs to SCL MSA_Out NET "SCL_BOT_Marker_PAD" LOC = "P39" ; #32 NET "SCL_BX_Marker_PAD" LOC = "P38" ; #33 NET "SCL_SyncG_Marker_PAD" LOC = "P36" ; #34 NET "SCL_Cos_Marker_PAD" LOC = "P35" ; #35 NET "SCL_Spare_Marker_PAD" LOC = "P27" ; #36 NET "SCL_L1_Accept_PAD" LOC = "P44" ; #40 NET "SCL_Initialize_PAD(0)" LOC = "P43" ; #41 NET "SCL_L2_Decision_PAD" LOC = "P42" ; #42 NET "SCL_Initialize_PAD(1)" LOC = "P18" ; #47 // 5 outputs to Framework NET "FW_BOT_Marker_PAD" LOC = "P49" ; #48 NET "FW_BX_Marker_PAD" LOC = "P48" ; #49 NET "FW_SyncG_Marker_PAD" LOC = "P47" ; #50 NET "FW_Cos_Marker_PAD" LOC = "P46" ; #51 NET "FW_Spare_Marker_PAD" LOC = "P16" ; #52 // -------------------------------------------------------------------- // Below here are only pins that are not used in the SCL_Helper design. // NET "OCB_Reg_Addr_PAD(8)" LOC = "P157" ; # not used // the following signals are NOT used on the SCL Helper FPGA // NET "HQ_Timing_PAD(0)" LOC = "P2" ; // NET "HQ_Timing_PAD(1)" LOC = "P63" ; // NET "HQ_Timing_PAD(2)" LOC = "P124" ; // NET "HQ_Timing_PAD(3)" LOC = "P184" ; // High-Speed Read Out Signals: DO NOT MODIFY (except FM/not FM changes) // High Speed Readout Control and Data Bus Lines, Capture Control Lines // DO NOT MODIFY (except FM/not FM changes) and to exclude // HSRO NOT USED on SCL Helper FPGA // NET "Capture_HSRO_Data_PAD*" LOC = "P133" ; # not on FM // NET "Capture_Monitor_Data_PAD*" LOC = "P134" ; # not on FM // NET "HSRO_DCE_In_PAD*" LOC = "P89" ; # FM only // NET "HSRO_DCE_In_PAD*" LOC = "P28" ; # not on FM // NET "HSRO_DCE_Out_PAD*" LOC = "P64" ; // NET "HSRO_Data_PAD(0)" LOC = "P178" ; // NET "HSRO_Data_PAD(1)" LOC = "P171" ; // NET "HSRO_Data_PAD(2)" LOC = "P156" ; // NET "HSRO_Data_PAD(3)" LOC = "P147" ; // NET "HSRO_Data_PAD(4)" LOC = "P146" ; // NET "HSRO_Data_PAD(5)" LOC = "P139" ; // NET "HSRO_Data_PAD(6)" LOC = "P128" ; // NET "HSRO_Data_PAD(7)" LOC = "P125" ; // NET "HSRO_Data_PAD(8)" LOC = "P175" ; // NET "HSRO_Data_PAD(9)" LOC = "P170" ; // NET "HSRO_Data_PAD(10)" LOC = "P153" ; // NET "HSRO_Data_PAD(11)" LOC = "P149" ; // NET "HSRO_Data_PAD(12)" LOC = "P144" ; // NET "HSRO_Data_PAD(13)" LOC = "P137" ; // NET "HSRO_Data_PAD(14)" LOC = "P130" ; // NET "HSRO_Data_PAD(15)" LOC = "P127" ; // NET "HSRO_Data_Valid_PAD*" LOC = "P132" ; // Dedicated and/or Reserved Signals: DO NOT MODIFY // (note: these signals not explicitly called out in FPGA design) // NET "CCLK goes here" LOC = "P179" ; // NET "DONE -- Chip_Configed" LOC = "P120" ; // NET "ERR/INIT* goes here" LOC = "P89" ; # HDI* on FM // NET "LDC* goes here" LOC = "P68" ; // NET "M0 -- VDD" LOC = "P60" ; // NET "M1 -- GROUND" LOC = "P58" ; // NET "M2 -- VDD" LOC = "P62" ; // NET "PROG* -- Config_Chip*" LOC = "P122" ; // NET "TCK goes here" LOC = "P7" ; // NET "TDI goes here" LOC = "P6" ; // NET "TDO goes here" LOC = "P181" ; // NET "TMS goes here" LOC = "P17" ; // NET "formerly OCB_Reg_Addr_PAD(8)" LOC = "P157" ; // NET "MSA_Input_PAD(37)" LOC = "P26" ; #37 // NET "MSA_Input_PAD(38)" LOC = "P25" ; #38 // NET "MSA_Input_PAD(39)" LOC = "P24" ; #39 // NET "MSA_Input_PAD(64)" LOC = "P79" ; #64 // NET "MSA_Input_PAD(65)" LOC = "P81" ; #65 // NET "MSA_Input_PAD(66)" LOC = "P82" ; #66 // NET "MSA_Input_PAD(67)" LOC = "P84" ; #67 // NET "MSA_Input_PAD(68)" LOC = "P85" ; #68 // NET "MSA_Input_PAD(69)" LOC = "P86" ; #69 // NET "MSA_Input_PAD(70)" LOC = "P87" ; #70 // NET "MSA_Input_PAD(71)" LOC = "P88" ; #71 // NET "MSA_Input_PAD(72)" LOC = "P92" ; #72 // NET "MSA_Input_PAD(73)" LOC = "P93" ; #73 // NET "MSA_Input_PAD(74)" LOC = "P94" ; #74 // NET "MSA_Input_PAD(75)" LOC = "P95" ; #75 // NET "MSA_Input_PAD(76)" LOC = "P96" ; #76 // NET "MSA_Input_PAD(78)" LOC = "P99" ; #78 // NET "MSA_Input_PAD(80)" LOC = "P102" ; #80 // NET "MSA_Input_PAD(81)" LOC = "P103" ; #81 // NET "MSA_Input_PAD(82)" LOC = "P104" ; #82 // NET "MSA_Input_PAD(83)" LOC = "P105" ; #83 // NET "MSA_Input_PAD(84)" LOC = "P107" ; #84 // NET "MSA_Input_PAD(85)" LOC = "P108" ; #85 // NET "MSA_Input_PAD(86)" LOC = "P109" ; #86 // NET "MSA_Input_PAD(87)" LOC = "P110" ; #87 // NET "MSA_Input_PAD(88)" LOC = "P111" ; #88 // NET "MSA_Input_PAD(89)" LOC = "P112" ; #89 // NET "MSA_Input_PAD(90)" LOC = "P113" ; #90 // NET "MSA_Input_PAD(92)" LOC = "P115" ; #92 // NET "MSA_Input_PAD(94)" LOC = "P117" ; #94 // NET "MSA_Input_PAD(96)" LOC = "P225" ; #96 // NET "MSA_Input_PAD(97)" LOC = "P224" ; #97 // NET "MSA_Input_PAD(98)" LOC = "P223" ; #98 // NET "MSA_Input_PAD(99)" LOC = "P221" ; #99 // NET "MSA_Input_PAD(100)" LOC = "P220" ; #100 // NET "MSA_Input_PAD(104)" LOC = "P215" ; #104 // NET "MSA_Input_PAD(105)" LOC = "P214" ; #105 // NET "MSA_Input_PAD(106)" LOC = "P213" ; #106 // NET "MSA_Input_PAD(107)" LOC = "P210" ; #107 // NET "MSA_Input_PAD(108)" LOC = "P209" ; #108 // NET "MSA_Input_PAD(109)" LOC = "P208" ; #109 // NET "MSA_Input_PAD(110)" LOC = "P207" ; #110 // NET "MSA_Input_PAD(111)" LOC = "P206" ; #111 // NET "MSA_Input_PAD(112)" LOC = "P205" ; #112 // NET "MSA_Input_PAD(113)" LOC = "P203" ; #113 // NET "MSA_Input_PAD(114)" LOC = "P202" ; #114 // NET "MSA_Input_PAD(115)" LOC = "P200" ; #115 // NET "MSA_Input_PAD(116)" LOC = "P199" ; #116 // NET "MSA_Input_PAD(118)" LOC = "P197" ; #118 // NET "MSA_Input_PAD(120)" LOC = "P193" ; #120 // NET "MSA_Input_PAD(122)" LOC = "P191" ; #122 // NET "MSA_Input_PAD(123)" LOC = "P190" ; #123 // NET "MSA_Input_PAD(124)" LOC = "P189" ; #124 // NET "MSA_Input_PAD(125)" LOC = "P188" ; #125 // NET "MSA_Input_PAD(126)" LOC = "P186" ; #126 // NET "MSA_Input_PAD(127)" LOC = "P185" ; #127 // NET "MSA_Output_PAD(43)" LOC = "P41" ; #43 // NET "MSA_Output_PAD(44)" LOC = "P23" ; #44 // NET "MSA_Output_PAD(45)" LOC = "P21" ; #45 // NET "MSA_Output_PAD(46)" LOC = "P20" ; #46 // NET "MSA_Output_PAD(53)" LOC = "P15" ; #53 // NET "MSA_Output_PAD(54)" LOC = "P13" ; #54 // NET "MSA_Output_PAD(55)" LOC = "P12" ; #55 // BG-I/O not used in this design // NET "Board_Global_IO_PAD(0)" LOC = "P52" ; // NET "Board_Global_IO_PAD(1)" LOC = "P53" ; // NET "Board_Global_IO_PAD(2)" LOC = "P54" ; // NET "Board_Global_IO_PAD(3)" LOC = "P55" ; // NET "Board_Global_IO_PAD(4)" LOC = "P56" ; // NET "Board_Global_IO_PAD(5)" LOC = "P65" ; // NET "Board_Global_IO_PAD(6)" LOC = "P66" ; // NET "Board_Global_IO_PAD(7)" LOC = "P67" ; // NET "Board_Global_IO_PAD(8)" LOC = "P69" ; // NET "Board_Global_IO_PAD(9)" LOC = "P70" ; // NET "Board_Global_IO_PAD(10)" LOC = "P71" ; // NET "Board_Global_IO_PAD(11)" LOC = "P72" ; // NET "Board_Global_IO_PAD(12)" LOC = "P73" ; // NET "Board_Global_IO_PAD(13)" LOC = "P74" ; // NET "Board_Global_IO_PAD(14)" LOC = "P76" ; // NET "Board_Global_IO_PAD(15)" LOC = "P77" ; // NET "Board_Global_IO_PAD(16)" LOC = "P78" ;