Notes on 21164 memory and cache system
11/11/97

cf. "21164(366-433MHz) Hardware Reference Manual"
hardcopy manual or online in PDF/PS format at
ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html


Glossary (cf. glossary from hardware reference book)
========

    Direct-Mapped
    -------------
A Main Memory address can be placed in only one place in the cache.
Only one address comparison is needed (only one tag to check) to determine cache
miss vs cache hit.

    Fully Associative
    -----------------
Data from anywhere in main memory can be placed anywhere in cache.
Hard to determine if a given piece of data is currently cached.

    Set-Associative
    ---------------
compromise between direct-mapped and fully associative.
n-way set associative means that that a given address can be cached in only 'n'
possible places.

    Write-Through
    -------------
writing to cache writes to main memory (or is it only to the next level cache?)
in the same operation that writes the cache.

    Write-Back
    ----------
writing to cache does NOT write to main memory in same operation.  Instead, the
information will be written when that line of cache is needed to store some
other new piece of information.

    Cache Line or Cache Block
    -------------------------
Whenever there is a cache miss, the cache system gets the memory information
requested AND, in the same memory transfer, updates more information in the
cache.  This minimum size of cache data update is called the cache line; this is
also the minimum size of data transfer on the memory bus.  This helps by
increasing the chances of a cache hit later on when the program tries to access
neigboring information.  This also diminishes the amount of bookkeeping to keep
track of which piece of information is cached (there is only one cache tag per
cache line).

    Virtual Cache
    -------------
a virtual cache is addressed directly with virtual addresses.  The tag
information is in virtual space. No translation buffer is needed.

    Physical Cache
    --------------
addresses cached are physical memory addresses.

    Cache Tag
    ---------
holds address information to determine if there is a cache hit/miss, and whether
the information is valid, clean, dirty...
Instruction cache tags hold more information about branch prediction...

    Clean
    -----
The cache line is valid but has not been written to by processor.

    Dirty
    ----
The cache line is valid and some of its data has been written to by processor.
Cached data may now differ from main memory.

    Victim
    ------
valid but about to be replaced due to cache resource conflict. It is going to be
replaced with some data from some other main memory location

21164 Implementation  (see chapter 2.1 for L1+L2 cache, chapter 4 for L3 cache)
====================

    I-Cache
    -------
On-chip Level 1 Instruction cache; 8 kByte; direct-mapped; virtual; 32 byte
cache line; with 8 bit branch history field

    D-Cache
    -------
On-chip Level 1 Data cache; 8 kByte; Dual-read-ported (two reads per clock
cycle); write through; direct-mapped; physical; 32 byte cache line; read
allocate (reading main memory allocates a line of cache).

    S-Cache
    -------
On-chip Level 2 unified data+instruction cache; 96 kByte; 3-way set-associative;
write-back; physical; 32 or 64 byte per line.

    B-Cache
    -------
Off-chip Level 3 cache; optional; 0, 1, 2, 4,..64 MByte; direct-mapped;
physical; write-allocate.


    The D-Cache is kept as a subset of the S-Cache; the S-cache a subset of the
B-cache.

    The I-Cache is not a subset of anything and is not kept coherent with main
memory.  (meaning one cannot expect to change the program on the fly)