/*-------------------------------------------------------------------------------*/ /* HsroRawTestEvent.h 25-Sept-00 stuff the VBD Buffer with fixed data This file is called from dlg_test_hsro.cpp to help debugging the HSRO Test when TRICS_IO_FAKE is set 04-Apr-2006 Update for SBC format (add a word before every VRB section) */ /*-------------------------------------------------------------------------------*/ // Event Captured 13-Jul-2001 23:09:13.374 in TRICS_II_20010712_V9_2_J.LOG;1 // This even has been manually modified to add the longword inserted by the SBC before each section // and copy the VBD header from what it looks like on 04-Apr-2006 pxVbdBase->aulBulk[0x000] = 0x000002bc ; // VBD Header first word pxVbdBase->aulBulk[0x001] = 0x7d01001f ; // VBD Header (unused now) pxVbdBase->aulBulk[0x002] = 0xdeadbeef ; // VBD Header (unused now) pxVbdBase->aulBulk[0x003] = 0x00000000 ; // VBD Header (unused now) pxVbdBase->aulBulk[0x004] = 0x00000000 ; // VBD Header (unused now) pxVbdBase->aulBulk[0x005] = 0x00000000 ; // VBD Header (unused now) pxVbdBase->aulBulk[0x006] = 0x00000000 ; // VBD Header (unused now) pxVbdBase->aulBulk[0x007] = 0x00000000 ; // VBD header last word pxVbdBase->aulBulk[0x008] = 0x00000000 ; // **** alignement word introduced by SBC **** pxVbdBase->aulBulk[0x009] = 0x99990058 ; // longword count for 1st VRB section pxVbdBase->aulBulk[0x00a] = 0x00000160 ; // VRB Header:byte count pxVbdBase->aulBulk[0x00b] = 0xb1011300 ; // user info word & slot num byte & event num byte pxVbdBase->aulBulk[0x00c] = 0x0a250002 ; // firmware version word & config info word pxVbdBase->aulBulk[0x00d] = 0x00000000 ; // status word pxVbdBase->aulBulk[0x00e] = 0x00280028 ; // byte count 1st channel pair pxVbdBase->aulBulk[0x00f] = 0x00280028 ; // byte count 2nd channel pair pxVbdBase->aulBulk[0x010] = 0x00280028 ; // byte count 3rd channel pair pxVbdBase->aulBulk[0x011] = 0x00280028 ; // byte count 4th channel pair pxVbdBase->aulBulk[0x012] = 0x8a010030 ; // 1 st longword from Low half of 1st channel pair pxVbdBase->aulBulk[0x013] = 0x001e0000 ; // 2 pxVbdBase->aulBulk[0x014] = 0x000000b0 ; // 3 pxVbdBase->aulBulk[0x015] = 0x001e0000 ; // 4 pxVbdBase->aulBulk[0x016] = 0x000000b0 ; // 5 pxVbdBase->aulBulk[0x017] = 0x001e0000 ; // 6 pxVbdBase->aulBulk[0x018] = 0x00000070 ; // 7 pxVbdBase->aulBulk[0x019] = 0x001e0000 ; // 8 pxVbdBase->aulBulk[0x01a] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x01b] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 (lower byte is BSF event number) pxVbdBase->aulBulk[0x01c] = 0x72060028 ; // 1 st longword from High half of 1st channel pair pxVbdBase->aulBulk[0x01d] = 0x000d0082 ; // 2 pxVbdBase->aulBulk[0x01e] = 0x00820068 ; // 3 pxVbdBase->aulBulk[0x01f] = 0x000d0082 ; // 4 pxVbdBase->aulBulk[0x020] = 0x00820049 ; // 5 pxVbdBase->aulBulk[0x021] = 0x000d0082 ; // 6 pxVbdBase->aulBulk[0x022] = 0x00820011 ; // 7 pxVbdBase->aulBulk[0x023] = 0x000d0082 ; // 8 pxVbdBase->aulBulk[0x024] = 0x00820000 ; // 9 pxVbdBase->aulBulk[0x025] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x026] = 0x89010000 ; // 1 st longword from Low half of 2nd channel pair pxVbdBase->aulBulk[0x027] = 0x00e70000 ; // 2 pxVbdBase->aulBulk[0x028] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x029] = 0x00e70000 ; // 4 pxVbdBase->aulBulk[0x02a] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x02b] = 0x00e70000 ; // 6 pxVbdBase->aulBulk[0x02c] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x02d] = 0x00e70000 ; // 8 pxVbdBase->aulBulk[0x02e] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x02f] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 (lower byte is BSF event number) pxVbdBase->aulBulk[0x030] = 0x72060082 ; // 1 st longword from High half of 2nd channel pair pxVbdBase->aulBulk[0x031] = 0x00800082 ; // 2 pxVbdBase->aulBulk[0x032] = 0x00820082 ; // 3 pxVbdBase->aulBulk[0x033] = 0x00800082 ; // 4 pxVbdBase->aulBulk[0x034] = 0x00820082 ; // 5 pxVbdBase->aulBulk[0x035] = 0x00800082 ; // 6 pxVbdBase->aulBulk[0x036] = 0x00820082 ; // 7 pxVbdBase->aulBulk[0x037] = 0x00800082 ; // 8 pxVbdBase->aulBulk[0x038] = 0x00820000 ; // 9 pxVbdBase->aulBulk[0x039] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x03a] = 0x830100e4 ; // 1 st longword from Low half of 3rd channel pair pxVbdBase->aulBulk[0x03b] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x03c] = 0x000000e4 ; // 3 pxVbdBase->aulBulk[0x03d] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x03e] = 0x000000e4 ; // 5 pxVbdBase->aulBulk[0x03f] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x040] = 0x000000e4 ; // 7 pxVbdBase->aulBulk[0x041] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x042] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x043] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 (lower byte is BSF event number) pxVbdBase->aulBulk[0x044] = 0x72060004 ; // 1 st longword from High half of 3rd channel pair pxVbdBase->aulBulk[0x045] = 0x00820082 ; // 2 pxVbdBase->aulBulk[0x046] = 0x00820004 ; // 3 pxVbdBase->aulBulk[0x047] = 0x00820082 ; // 4 pxVbdBase->aulBulk[0x048] = 0x00820004 ; // 5 pxVbdBase->aulBulk[0x049] = 0x00820082 ; // 6 pxVbdBase->aulBulk[0x04a] = 0x00820004 ; // 7 pxVbdBase->aulBulk[0x04b] = 0x00820082 ; // 8 pxVbdBase->aulBulk[0x04c] = 0x00820000 ; // 9 pxVbdBase->aulBulk[0x04d] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x04e] = 0x820100e7 ; // 1 st longword from Low half of 4th channel pair pxVbdBase->aulBulk[0x04f] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x050] = 0x000000e7 ; // 3 pxVbdBase->aulBulk[0x051] = 0x00800000 ; // 4 pxVbdBase->aulBulk[0x052] = 0x620000e7 ; // 5 pxVbdBase->aulBulk[0x053] = 0xcc900000 ; // 6 pxVbdBase->aulBulk[0x054] = 0x000000e7 ; // 7 pxVbdBase->aulBulk[0x055] = 0x33100000 ; // 8 pxVbdBase->aulBulk[0x056] = 0x88000000 ; // 9 pxVbdBase->aulBulk[0x057] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 (lower byte is BSF event number) pxVbdBase->aulBulk[0x058] = 0x72060080 ; // 1 st longword from High half of 4th channel pair pxVbdBase->aulBulk[0x059] = 0x00340082 ; // 2 pxVbdBase->aulBulk[0x05a] = 0x00820080 ; // 3 pxVbdBase->aulBulk[0x05b] = 0x00740082 ; // 4 pxVbdBase->aulBulk[0x05c] = 0x62820080 ; // 5 pxVbdBase->aulBulk[0x05d] = 0xcc490082 ; // 6 pxVbdBase->aulBulk[0x05e] = 0x00820080 ; // 7 pxVbdBase->aulBulk[0x05f] = 0x33090082 ; // 8 pxVbdBase->aulBulk[0x060] = 0x88820000 ; // 9 pxVbdBase->aulBulk[0x061] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x062] = 0x00000000 ; // **** alignement word introduced by SBC **** pxVbdBase->aulBulk[0x063] = 0x88820058 ; // longword count for 1st VRB section pxVbdBase->aulBulk[0x064] = 0x00000160 ; // VRB Header:byte count pxVbdBase->aulBulk[0x065] = 0x11010900 ; // user info word & slot num byte & event num byte pxVbdBase->aulBulk[0x066] = 0x0a250002 ; // firmware version word & config info word pxVbdBase->aulBulk[0x067] = 0x00000000 ; // status word pxVbdBase->aulBulk[0x068] = 0x00280028 ; // byte count 1st channel pair pxVbdBase->aulBulk[0x069] = 0x00280028 ; // byte count 2nd channel pair pxVbdBase->aulBulk[0x06a] = 0x00280028 ; // byte count 3rd channel pair pxVbdBase->aulBulk[0x06b] = 0x00280028 ; // byte count 4th channel pair pxVbdBase->aulBulk[0x06c] = 0x8e03ffff ; // 1 st longword from Low half of 1st channel pair pxVbdBase->aulBulk[0x06d] = 0xffffffff ; // 2 pxVbdBase->aulBulk[0x06e] = 0xffffffff ; // 3 pxVbdBase->aulBulk[0x06f] = 0xffffffff ; // 4 pxVbdBase->aulBulk[0x070] = 0xffffffff ; // 5 pxVbdBase->aulBulk[0x071] = 0xffffffff ; // 6 pxVbdBase->aulBulk[0x072] = 0xffffffff ; // 7 pxVbdBase->aulBulk[0x073] = 0xffffffff ; // 8 pxVbdBase->aulBulk[0x074] = 0xffff0000 ; // 9 pxVbdBase->aulBulk[0x075] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x076] = 0x7220ffff ; // 1 st longword from High half of 1st channel pair pxVbdBase->aulBulk[0x077] = 0xffffffff ; // 2 pxVbdBase->aulBulk[0x078] = 0xffffffff ; // 3 pxVbdBase->aulBulk[0x079] = 0xffffffff ; // 4 pxVbdBase->aulBulk[0x07a] = 0xffffffff ; // 5 pxVbdBase->aulBulk[0x07b] = 0xffffffff ; // 6 pxVbdBase->aulBulk[0x07c] = 0xffffffff ; // 7 pxVbdBase->aulBulk[0x07d] = 0xffffffff ; // 8 pxVbdBase->aulBulk[0x07e] = 0xffff0000 ; // 9 pxVbdBase->aulBulk[0x07f] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x080] = 0x8d03ffff ; // 1 st longword from Low half of 2nd channel pair pxVbdBase->aulBulk[0x081] = 0xffffffff ; // 2 pxVbdBase->aulBulk[0x082] = 0xffffffff ; // 3 pxVbdBase->aulBulk[0x083] = 0xffffffff ; // 4 pxVbdBase->aulBulk[0x084] = 0xffffffff ; // 5 pxVbdBase->aulBulk[0x085] = 0xffffffff ; // 6 pxVbdBase->aulBulk[0x086] = 0xffffffff ; // 7 pxVbdBase->aulBulk[0x087] = 0xffffffff ; // 8 pxVbdBase->aulBulk[0x088] = 0xffff0000 ; // 9 pxVbdBase->aulBulk[0x089] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x08a] = 0x7220ffff ; // 1 st longword from High half of 2nd channel pair pxVbdBase->aulBulk[0x08b] = 0xffffffff ; // 2 pxVbdBase->aulBulk[0x08c] = 0xffffffff ; // 3 pxVbdBase->aulBulk[0x08d] = 0xffffffff ; // 4 pxVbdBase->aulBulk[0x08e] = 0xffffffff ; // 5 pxVbdBase->aulBulk[0x08f] = 0xffffffff ; // 6 pxVbdBase->aulBulk[0x090] = 0xffffffff ; // 7 pxVbdBase->aulBulk[0x091] = 0xffffffff ; // 8 pxVbdBase->aulBulk[0x092] = 0xffff0000 ; // 9 pxVbdBase->aulBulk[0x093] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x094] = 0x87031111 ; // 1 st longword from Low half of 3rd channel pair pxVbdBase->aulBulk[0x095] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x096] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x097] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x098] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x099] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x09a] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x09b] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x09c] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x09d] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x09e] = 0x72201111 ; // 1 st longword from High half of 3rd channel pair pxVbdBase->aulBulk[0x09f] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x0a0] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x0a1] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x0a2] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x0a3] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x0a4] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x0a5] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x0a6] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x0a7] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x0a8] = 0x86030000 ; // 1 st longword from Low half of 4th channel pair pxVbdBase->aulBulk[0x0a9] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x0aa] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x0ab] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x0ac] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x0ad] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x0ae] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x0af] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x0b0] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x0b1] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x0b2] = 0x72200000 ; // 1 st longword from High half of 4th channel pair pxVbdBase->aulBulk[0x0b3] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x0b4] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x0b5] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x0b6] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x0b7] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x0b8] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x0b9] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x0ba] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x0bb] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x0bc] = 0x00000000 ; // **** alignement word introduced by SBC **** pxVbdBase->aulBulk[0x0bd] = 0x776b0044 ; // longword count for 1st VRB section pxVbdBase->aulBulk[0x0be] = 0x00000110 ; // VRB Header:byte count pxVbdBase->aulBulk[0x0bf] = 0x21010a00 ; // user info word & slot num byte & event num byte pxVbdBase->aulBulk[0x0c0] = 0x0a250002 ; // firmware version word & config info word pxVbdBase->aulBulk[0x0c1] = 0x00000000 ; // status word pxVbdBase->aulBulk[0x0c2] = 0x00280028 ; // byte count 1st channel pair pxVbdBase->aulBulk[0x0c3] = 0x00280028 ; // byte count 2nd channel pair pxVbdBase->aulBulk[0x0c4] = 0x00280028 ; // byte count 3rd channel pair pxVbdBase->aulBulk[0x0c5] = 0x00000000 ; // byte count 4th channel pair pxVbdBase->aulBulk[0x0c6] = 0x8c03ffff ; // 1 st longword from Low half of 1st channel pair pxVbdBase->aulBulk[0x0c7] = 0xffffffff ; // 2 pxVbdBase->aulBulk[0x0c8] = 0xffff0000 ; // 3 pxVbdBase->aulBulk[0x0c9] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x0ca] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x0cb] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x0cc] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x0cd] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x0ce] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x0cf] = 0xff000172 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x0d0] = 0x7220ffff ; // 1 st longword from High half of 1st channel pair pxVbdBase->aulBulk[0x0d1] = 0xffffffff ; // 2 pxVbdBase->aulBulk[0x0d2] = 0xffff0000 ; // 3 pxVbdBase->aulBulk[0x0d3] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x0d4] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x0d5] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x0d6] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x0d7] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x0d8] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x0d9] = 0xff000503 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x0da] = 0x85033333 ; // 1 st longword from Low half of 2nd channel pair pxVbdBase->aulBulk[0x0db] = 0x00003333 ; // 2 pxVbdBase->aulBulk[0x0dc] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x0dd] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x0de] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x0df] = 0x00000060 ; // 6 pxVbdBase->aulBulk[0x0e0] = 0x00200000 ; // 7 pxVbdBase->aulBulk[0x0e1] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x0e2] = 0x00600000 ; // 9 pxVbdBase->aulBulk[0x0e3] = 0xff000172 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x0e4] = 0x72203333 ; // 1 st longword from High half of 2nd channel pair pxVbdBase->aulBulk[0x0e5] = 0x00003333 ; // 2 pxVbdBase->aulBulk[0x0e6] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x0e7] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x0e8] = 0x0000003c ; // 5 pxVbdBase->aulBulk[0x0e9] = 0x003c0080 ; // 6 pxVbdBase->aulBulk[0x0ea] = 0x00800000 ; // 7 pxVbdBase->aulBulk[0x0eb] = 0x0000003c ; // 8 pxVbdBase->aulBulk[0x0ec] = 0x00800000 ; // 9 pxVbdBase->aulBulk[0x0ed] = 0xff000503 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x0ee] = 0x94010000 ; // 1 st longword from Low half of 3rd channel pair pxVbdBase->aulBulk[0x0ef] = 0x000009fe ; // 2 pxVbdBase->aulBulk[0x0f0] = 0x41060000 ; // 3 pxVbdBase->aulBulk[0x0f1] = 0x00000102 ; // 4 pxVbdBase->aulBulk[0x0f2] = 0x00008284 ; // 5 pxVbdBase->aulBulk[0x0f3] = 0x9294a2a4 ; // 6 pxVbdBase->aulBulk[0x0f4] = 0xb2b4c2c4 ; // 7 pxVbdBase->aulBulk[0x0f5] = 0xd2d4e2e4 ; // 8 pxVbdBase->aulBulk[0x0f6] = 0xf2f40000 ; // 9 pxVbdBase->aulBulk[0x0f7] = 0x9f000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x0f8] = 0x72010000 ; // 1 st longword from High half of 3rd channel pair pxVbdBase->aulBulk[0x0f9] = 0x000092ca ; // 2 pxVbdBase->aulBulk[0x0fa] = 0x04000000 ; // 3 pxVbdBase->aulBulk[0x0fb] = 0x00001b1b ; // 4 pxVbdBase->aulBulk[0x0fc] = 0x00008183 ; // 5 pxVbdBase->aulBulk[0x0fd] = 0x9193a1a3 ; // 6 pxVbdBase->aulBulk[0x0fe] = 0xb1b3c1c3 ; // 7 pxVbdBase->aulBulk[0x0ff] = 0xd1d3e1e3 ; // 8 pxVbdBase->aulBulk[0x100] = 0xf1f30000 ; // 9 pxVbdBase->aulBulk[0x101] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x102] = 0x00000000 ; // **** alignement word introduced by SBC **** pxVbdBase->aulBulk[0x103] = 0x11000044 ; // longword count for 1st VRB section pxVbdBase->aulBulk[0x104] = 0x00000110 ; // VRB Header:byte count pxVbdBase->aulBulk[0x105] = 0x31010b00 ; // user info word & slot num byte & event num byte pxVbdBase->aulBulk[0x106] = 0x0a250002 ; // firmware version word & config info word pxVbdBase->aulBulk[0x107] = 0x00000000 ; // status word pxVbdBase->aulBulk[0x108] = 0x00280028 ; // byte count 1st channel pair pxVbdBase->aulBulk[0x109] = 0x00280028 ; // byte count 2nd channel pair pxVbdBase->aulBulk[0x10a] = 0x00280028 ; // byte count 3rd channel pair pxVbdBase->aulBulk[0x10b] = 0x00000000 ; // byte count 4th channel pair pxVbdBase->aulBulk[0x10c] = 0x91010000 ; // 1 st longword from Low half of 1st channel pair pxVbdBase->aulBulk[0x10d] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x10e] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x10f] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x110] = 0x22000000 ; // 5 pxVbdBase->aulBulk[0x111] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x112] = 0x44000000 ; // 7 pxVbdBase->aulBulk[0x113] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x114] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x115] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x116] = 0x72060082 ; // 1 st longword from High half of 1st channel pair pxVbdBase->aulBulk[0x117] = 0x00820082 ; // 2 pxVbdBase->aulBulk[0x118] = 0x00820082 ; // 3 pxVbdBase->aulBulk[0x119] = 0x00820082 ; // 4 pxVbdBase->aulBulk[0x11a] = 0x22820082 ; // 5 pxVbdBase->aulBulk[0x11b] = 0x00820082 ; // 6 pxVbdBase->aulBulk[0x11c] = 0x44820082 ; // 7 pxVbdBase->aulBulk[0x11d] = 0x00820082 ; // 8 pxVbdBase->aulBulk[0x11e] = 0x00820000 ; // 9 pxVbdBase->aulBulk[0x11f] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x120] = 0x90010000 ; // 1 st longword from Low half of 2nd channel pair pxVbdBase->aulBulk[0x121] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x122] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x123] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x124] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x125] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x126] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x127] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x128] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x129] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x12a] = 0x72060082 ; // 1 st longword from High half of 2nd channel pair pxVbdBase->aulBulk[0x12b] = 0x00820082 ; // 2 pxVbdBase->aulBulk[0x12c] = 0x00820082 ; // 3 pxVbdBase->aulBulk[0x12d] = 0x00820082 ; // 4 pxVbdBase->aulBulk[0x12e] = 0x00820082 ; // 5 pxVbdBase->aulBulk[0x12f] = 0x00820082 ; // 6 pxVbdBase->aulBulk[0x130] = 0x00820082 ; // 7 pxVbdBase->aulBulk[0x131] = 0x00820082 ; // 8 pxVbdBase->aulBulk[0x132] = 0x00820000 ; // 9 pxVbdBase->aulBulk[0x133] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x134] = 0x93020000 ; // 1 st longword from Low half of 3rd channel pair pxVbdBase->aulBulk[0x135] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x136] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x137] = 0x00000020 ; // 4 pxVbdBase->aulBulk[0x138] = 0x00200000 ; // 5 pxVbdBase->aulBulk[0x139] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x13a] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x13b] = 0x00200000 ; // 8 pxVbdBase->aulBulk[0x13c] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x13d] = 0xdf000172 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x13e] = 0x72010000 ; // 1 st longword from High half of 3rd channel pair pxVbdBase->aulBulk[0x13f] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x140] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x141] = 0x00000004 ; // 4 pxVbdBase->aulBulk[0x142] = 0x00040000 ; // 5 pxVbdBase->aulBulk[0x143] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x144] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x145] = 0x00040000 ; // 8 pxVbdBase->aulBulk[0x146] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x147] = 0x7e000503 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x148] = 0x00000000 ; // **** alignement word introduced by SBC **** pxVbdBase->aulBulk[0x149] = 0xaa950058 ; // longword count for 1st VRB section pxVbdBase->aulBulk[0x14a] = 0x00000160 ; // VRB Header:byte count pxVbdBase->aulBulk[0x14b] = 0x41010c00 ; // user info word & slot num byte & event num byte pxVbdBase->aulBulk[0x14c] = 0x0a250002 ; // firmware version word & config info word pxVbdBase->aulBulk[0x14d] = 0x00000000 ; // status word pxVbdBase->aulBulk[0x14e] = 0x00280028 ; // byte count 1st channel pair pxVbdBase->aulBulk[0x14f] = 0x00280028 ; // byte count 2nd channel pair pxVbdBase->aulBulk[0x150] = 0x00280028 ; // byte count 3rd channel pair pxVbdBase->aulBulk[0x151] = 0x00280028 ; // byte count 4th channel pair pxVbdBase->aulBulk[0x152] = 0xab01f900 ; // 1 st longword from Low half of 1st channel pair pxVbdBase->aulBulk[0x153] = 0xa001a001 ; // 2 pxVbdBase->aulBulk[0x154] = 0xa001a001 ; // 3 pxVbdBase->aulBulk[0x155] = 0xa001a001 ; // 4 pxVbdBase->aulBulk[0x156] = 0xa001a001 ; // 5 pxVbdBase->aulBulk[0x157] = 0xa001a001 ; // 6 pxVbdBase->aulBulk[0x158] = 0xa001a001 ; // 7 pxVbdBase->aulBulk[0x159] = 0xa001a001 ; // 8 pxVbdBase->aulBulk[0x15a] = 0xa0010100 ; // 9 pxVbdBase->aulBulk[0x15b] = 0xff010072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x15c] = 0x72185760 ; // 1 st longword from High half of 1st channel pair pxVbdBase->aulBulk[0x15d] = 0x47204720 ; // 2 pxVbdBase->aulBulk[0x15e] = 0x47204720 ; // 3 pxVbdBase->aulBulk[0x15f] = 0x47204720 ; // 4 pxVbdBase->aulBulk[0x160] = 0x47204720 ; // 5 pxVbdBase->aulBulk[0x161] = 0x47204720 ; // 6 pxVbdBase->aulBulk[0x162] = 0x47204720 ; // 7 pxVbdBase->aulBulk[0x163] = 0x47204720 ; // 8 pxVbdBase->aulBulk[0x164] = 0x47200000 ; // 9 pxVbdBase->aulBulk[0x165] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x166] = 0xaa01a001 ; // 1 st longword from Low half of 2nd channel pair pxVbdBase->aulBulk[0x167] = 0xa001a001 ; // 2 pxVbdBase->aulBulk[0x168] = 0xa001a001 ; // 3 pxVbdBase->aulBulk[0x169] = 0xa001a001 ; // 4 pxVbdBase->aulBulk[0x16a] = 0xa001a001 ; // 5 pxVbdBase->aulBulk[0x16b] = 0xa001a001 ; // 6 pxVbdBase->aulBulk[0x16c] = 0xa001a001 ; // 7 pxVbdBase->aulBulk[0x16d] = 0xa001a001 ; // 8 pxVbdBase->aulBulk[0x16e] = 0xa0010000 ; // 9 pxVbdBase->aulBulk[0x16f] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x170] = 0x72184720 ; // 1 st longword from High half of 2nd channel pair pxVbdBase->aulBulk[0x171] = 0x47204720 ; // 2 pxVbdBase->aulBulk[0x172] = 0x47204720 ; // 3 pxVbdBase->aulBulk[0x173] = 0x47204720 ; // 4 pxVbdBase->aulBulk[0x174] = 0x47204720 ; // 5 pxVbdBase->aulBulk[0x175] = 0x47204720 ; // 6 pxVbdBase->aulBulk[0x176] = 0x47204720 ; // 7 pxVbdBase->aulBulk[0x177] = 0x47204720 ; // 8 pxVbdBase->aulBulk[0x178] = 0x47200000 ; // 9 pxVbdBase->aulBulk[0x179] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x17a] = 0xa901a001 ; // 1 st longword from Low half of 3rd channel pair pxVbdBase->aulBulk[0x17b] = 0xa001a001 ; // 2 pxVbdBase->aulBulk[0x17c] = 0xa001a001 ; // 3 pxVbdBase->aulBulk[0x17d] = 0xa001a001 ; // 4 pxVbdBase->aulBulk[0x17e] = 0xa001a001 ; // 5 pxVbdBase->aulBulk[0x17f] = 0xa001a001 ; // 6 pxVbdBase->aulBulk[0x180] = 0xa001a001 ; // 7 pxVbdBase->aulBulk[0x181] = 0xa001a001 ; // 8 pxVbdBase->aulBulk[0x182] = 0xa0010000 ; // 9 pxVbdBase->aulBulk[0x183] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x184] = 0x72184720 ; // 1 st longword from High half of 3rd channel pair pxVbdBase->aulBulk[0x185] = 0x47204720 ; // 2 pxVbdBase->aulBulk[0x186] = 0x47204720 ; // 3 pxVbdBase->aulBulk[0x187] = 0x47204720 ; // 4 pxVbdBase->aulBulk[0x188] = 0x47204720 ; // 5 pxVbdBase->aulBulk[0x189] = 0x47204720 ; // 6 pxVbdBase->aulBulk[0x18a] = 0x47204720 ; // 7 pxVbdBase->aulBulk[0x18b] = 0x47204720 ; // 8 pxVbdBase->aulBulk[0x18c] = 0x47200000 ; // 9 pxVbdBase->aulBulk[0x18d] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x18e] = 0xa801a001 ; // 1 st longword from Low half of 4th channel pair pxVbdBase->aulBulk[0x18f] = 0xa001a001 ; // 2 pxVbdBase->aulBulk[0x190] = 0xa001a001 ; // 3 pxVbdBase->aulBulk[0x191] = 0xa001a001 ; // 4 pxVbdBase->aulBulk[0x192] = 0xa001a001 ; // 5 pxVbdBase->aulBulk[0x193] = 0xa001a001 ; // 6 pxVbdBase->aulBulk[0x194] = 0xa001a001 ; // 7 pxVbdBase->aulBulk[0x195] = 0xa001a001 ; // 8 pxVbdBase->aulBulk[0x196] = 0xa0010000 ; // 9 pxVbdBase->aulBulk[0x197] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x198] = 0x72184720 ; // 1 st longword from High half of 4th channel pair pxVbdBase->aulBulk[0x199] = 0x47204720 ; // 2 pxVbdBase->aulBulk[0x19a] = 0x47204720 ; // 3 pxVbdBase->aulBulk[0x19b] = 0x47204720 ; // 4 pxVbdBase->aulBulk[0x19c] = 0x47204720 ; // 5 pxVbdBase->aulBulk[0x19d] = 0x47204720 ; // 6 pxVbdBase->aulBulk[0x19e] = 0x47204720 ; // 7 pxVbdBase->aulBulk[0x19f] = 0x47204720 ; // 8 pxVbdBase->aulBulk[0x1a0] = 0x47200000 ; // 9 pxVbdBase->aulBulk[0x1a1] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x1a2] = 0x00000000 ; // **** alignement word introduced by SBC **** pxVbdBase->aulBulk[0x1a3] = 0x997e0058 ; // longword count for 1st VRB section pxVbdBase->aulBulk[0x1a4] = 0x00000160 ; // VRB Header:byte count pxVbdBase->aulBulk[0x1a5] = 0x51010d00 ; // user info word & slot num byte & event num byte pxVbdBase->aulBulk[0x1a6] = 0x0a250002 ; // firmware version word & config info word pxVbdBase->aulBulk[0x1a7] = 0x00000000 ; // status word pxVbdBase->aulBulk[0x1a8] = 0x00280028 ; // byte count 1st channel pair pxVbdBase->aulBulk[0x1a9] = 0x00280028 ; // byte count 2nd channel pair pxVbdBase->aulBulk[0x1aa] = 0x00280028 ; // byte count 3rd channel pair pxVbdBase->aulBulk[0x1ab] = 0x00280028 ; // byte count 4th channel pair pxVbdBase->aulBulk[0x1ac] = 0xa701a001 ; // 1 st longword from Low half of 1st channel pair pxVbdBase->aulBulk[0x1ad] = 0xa001a001 ; // 2 pxVbdBase->aulBulk[0x1ae] = 0xa001a001 ; // 3 pxVbdBase->aulBulk[0x1af] = 0xa001a001 ; // 4 pxVbdBase->aulBulk[0x1b0] = 0xa001a001 ; // 5 pxVbdBase->aulBulk[0x1b1] = 0xa001a001 ; // 6 pxVbdBase->aulBulk[0x1b2] = 0xa001a001 ; // 7 pxVbdBase->aulBulk[0x1b3] = 0xa001a001 ; // 8 pxVbdBase->aulBulk[0x1b4] = 0xa0010000 ; // 9 pxVbdBase->aulBulk[0x1b5] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x1b6] = 0x72184720 ; // 1 st longword from High half of 1st channel pair pxVbdBase->aulBulk[0x1b7] = 0x47204720 ; // 2 pxVbdBase->aulBulk[0x1b8] = 0x47204720 ; // 3 pxVbdBase->aulBulk[0x1b9] = 0x47204720 ; // 4 pxVbdBase->aulBulk[0x1ba] = 0x47204720 ; // 5 pxVbdBase->aulBulk[0x1bb] = 0x47204720 ; // 6 pxVbdBase->aulBulk[0x1bc] = 0x47204720 ; // 7 pxVbdBase->aulBulk[0x1bd] = 0x47204720 ; // 8 pxVbdBase->aulBulk[0x1be] = 0x47200000 ; // 9 pxVbdBase->aulBulk[0x1bf] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x1c0] = 0xa601a001 ; // 1 st longword from Low half of 2nd channel pair pxVbdBase->aulBulk[0x1c1] = 0xa001a001 ; // 2 pxVbdBase->aulBulk[0x1c2] = 0xa001a001 ; // 3 pxVbdBase->aulBulk[0x1c3] = 0xa001a001 ; // 4 pxVbdBase->aulBulk[0x1c4] = 0xa001a001 ; // 5 pxVbdBase->aulBulk[0x1c5] = 0xa001a001 ; // 6 pxVbdBase->aulBulk[0x1c6] = 0xa001a001 ; // 7 pxVbdBase->aulBulk[0x1c7] = 0xa001a001 ; // 8 pxVbdBase->aulBulk[0x1c8] = 0xa0010000 ; // 9 pxVbdBase->aulBulk[0x1c9] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x1ca] = 0x72184720 ; // 1 st longword from High half of 2nd channel pair pxVbdBase->aulBulk[0x1cb] = 0x47204720 ; // 2 pxVbdBase->aulBulk[0x1cc] = 0x47204720 ; // 3 pxVbdBase->aulBulk[0x1cd] = 0x47204720 ; // 4 pxVbdBase->aulBulk[0x1ce] = 0x47204720 ; // 5 pxVbdBase->aulBulk[0x1cf] = 0x47204720 ; // 6 pxVbdBase->aulBulk[0x1d0] = 0x47204720 ; // 7 pxVbdBase->aulBulk[0x1d1] = 0x47204720 ; // 8 pxVbdBase->aulBulk[0x1d2] = 0x47200000 ; // 9 pxVbdBase->aulBulk[0x1d3] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x1d4] = 0xa501a001 ; // 1 st longword from Low half of 3rd channel pair pxVbdBase->aulBulk[0x1d5] = 0xa001a001 ; // 2 pxVbdBase->aulBulk[0x1d6] = 0xa001a001 ; // 3 pxVbdBase->aulBulk[0x1d7] = 0xa001a001 ; // 4 pxVbdBase->aulBulk[0x1d8] = 0xa001a001 ; // 5 pxVbdBase->aulBulk[0x1d9] = 0xa001a001 ; // 6 pxVbdBase->aulBulk[0x1da] = 0xa001a001 ; // 7 pxVbdBase->aulBulk[0x1db] = 0xa001a001 ; // 8 pxVbdBase->aulBulk[0x1dc] = 0xa0010000 ; // 9 pxVbdBase->aulBulk[0x1dd] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x1de] = 0x72184720 ; // 1 st longword from High half of 3rd channel pair pxVbdBase->aulBulk[0x1df] = 0x47204720 ; // 2 pxVbdBase->aulBulk[0x1e0] = 0x47204720 ; // 3 pxVbdBase->aulBulk[0x1e1] = 0x47204720 ; // 4 pxVbdBase->aulBulk[0x1e2] = 0x47204720 ; // 5 pxVbdBase->aulBulk[0x1e3] = 0x47204720 ; // 6 pxVbdBase->aulBulk[0x1e4] = 0x47204720 ; // 7 pxVbdBase->aulBulk[0x1e5] = 0x47204720 ; // 8 pxVbdBase->aulBulk[0x1e6] = 0x47200000 ; // 9 pxVbdBase->aulBulk[0x1e7] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x1e8] = 0xa401a001 ; // 1 st longword from Low half of 4th channel pair pxVbdBase->aulBulk[0x1e9] = 0xa001a001 ; // 2 pxVbdBase->aulBulk[0x1ea] = 0xa001a001 ; // 3 pxVbdBase->aulBulk[0x1eb] = 0xa001a001 ; // 4 pxVbdBase->aulBulk[0x1ec] = 0xa001a001 ; // 5 pxVbdBase->aulBulk[0x1ed] = 0xa001a001 ; // 6 pxVbdBase->aulBulk[0x1ee] = 0xa001a001 ; // 7 pxVbdBase->aulBulk[0x1ef] = 0xa001a001 ; // 8 pxVbdBase->aulBulk[0x1f0] = 0xa0010000 ; // 9 pxVbdBase->aulBulk[0x1f1] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x1f2] = 0x72184720 ; // 1 st longword from High half of 4th channel pair pxVbdBase->aulBulk[0x1f3] = 0x47204720 ; // 2 pxVbdBase->aulBulk[0x1f4] = 0x47204720 ; // 3 pxVbdBase->aulBulk[0x1f5] = 0x47204720 ; // 4 pxVbdBase->aulBulk[0x1f6] = 0x47204720 ; // 5 pxVbdBase->aulBulk[0x1f7] = 0x47204720 ; // 6 pxVbdBase->aulBulk[0x1f8] = 0x47204720 ; // 7 pxVbdBase->aulBulk[0x1f9] = 0x47204720 ; // 8 pxVbdBase->aulBulk[0x1fa] = 0x47200000 ; // 9 pxVbdBase->aulBulk[0x1fb] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x1fc] = 0x00000000 ; // **** alignement word introduced by SBC **** pxVbdBase->aulBulk[0x1fd] = 0x88670044 ; // longword count for 1st VRB section pxVbdBase->aulBulk[0x1fe] = 0x00000110 ; // VRB Header:byte count pxVbdBase->aulBulk[0x1ff] = 0x81011000 ; // user info word & slot num byte & event num byte pxVbdBase->aulBulk[0x200] = 0x0a250002 ; // firmware version word & config info word pxVbdBase->aulBulk[0x201] = 0x00000000 ; // status word pxVbdBase->aulBulk[0x202] = 0x00280028 ; // byte count 1st channel pair pxVbdBase->aulBulk[0x203] = 0x00280028 ; // byte count 2nd channel pair pxVbdBase->aulBulk[0x204] = 0x00280028 ; // byte count 3rd channel pair pxVbdBase->aulBulk[0x205] = 0x00000000 ; // byte count 4th channel pair pxVbdBase->aulBulk[0x206] = 0xaf020000 ; // 1 st longword from Low half of 1st channel pair pxVbdBase->aulBulk[0x207] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x208] = 0x00001010 ; // 3 pxVbdBase->aulBulk[0x209] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x20a] = 0x80800000 ; // 5 pxVbdBase->aulBulk[0x20b] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x20c] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x20d] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x20e] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x20f] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x210] = 0x72010000 ; // 1 st longword from High half of 1st channel pair pxVbdBase->aulBulk[0x211] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x212] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x213] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x214] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x215] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x216] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x217] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x218] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x219] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x21a] = 0xae020000 ; // 1 st longword from Low half of 2nd channel pair pxVbdBase->aulBulk[0x21b] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x21c] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x21d] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x21e] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x21f] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x220] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x221] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x222] = 0x80800000 ; // 9 pxVbdBase->aulBulk[0x223] = 0xff0000fc ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x224] = 0x72010000 ; // 1 st longword from High half of 2nd channel pair pxVbdBase->aulBulk[0x225] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x226] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x227] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x228] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x229] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x22a] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x22b] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x22c] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x22d] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x22e] = 0xb001002f ; // 1 st longword from Low half of 3rd channel pair pxVbdBase->aulBulk[0x22f] = 0x002f002f ; // 2 pxVbdBase->aulBulk[0x230] = 0x002f002f ; // 3 pxVbdBase->aulBulk[0x231] = 0x002f002f ; // 4 pxVbdBase->aulBulk[0x232] = 0x002ff02f ; // 5 pxVbdBase->aulBulk[0x233] = 0xf02ff02f ; // 6 pxVbdBase->aulBulk[0x234] = 0x002f0100 ; // 7 pxVbdBase->aulBulk[0x235] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x236] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x237] = 0xff000172 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x238] = 0x72030099 ; // 1 st longword from High half of 3rd channel pair pxVbdBase->aulBulk[0x239] = 0x00990099 ; // 2 pxVbdBase->aulBulk[0x23a] = 0x00990099 ; // 3 pxVbdBase->aulBulk[0x23b] = 0x00990099 ; // 4 pxVbdBase->aulBulk[0x23c] = 0x00990099 ; // 5 pxVbdBase->aulBulk[0x23d] = 0x00991f99 ; // 6 pxVbdBase->aulBulk[0x23e] = 0x00990000 ; // 7 pxVbdBase->aulBulk[0x23f] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x240] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x241] = 0xff000503 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x242] = 0x00000000 ; // **** alignement word introduced by SBC **** pxVbdBase->aulBulk[0x243] = 0x21fc0058 ; // longword count for 1st VRB section pxVbdBase->aulBulk[0x244] = 0x00000160 ; // VRB Header:byte count pxVbdBase->aulBulk[0x245] = 0x91011100 ; // user info word & slot num byte & event num byte pxVbdBase->aulBulk[0x246] = 0x0a250002 ; // firmware version word & config info word pxVbdBase->aulBulk[0x247] = 0x00000000 ; // status word pxVbdBase->aulBulk[0x248] = 0x00280028 ; // byte count 1st channel pair pxVbdBase->aulBulk[0x249] = 0x00280028 ; // byte count 2nd channel pair pxVbdBase->aulBulk[0x24a] = 0x00280028 ; // byte count 3rd channel pair pxVbdBase->aulBulk[0x24b] = 0x00280028 ; // byte count 4th channel pair pxVbdBase->aulBulk[0x24c] = 0xc6010000 ; // 1 st longword from Low half of 1st channel pair pxVbdBase->aulBulk[0x24d] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x24e] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x24f] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x250] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x251] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x252] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x253] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x254] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x255] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x256] = 0x72060082 ; // 1 st longword from High half of 1st channel pair pxVbdBase->aulBulk[0x257] = 0x00820082 ; // 2 pxVbdBase->aulBulk[0x258] = 0x00820082 ; // 3 pxVbdBase->aulBulk[0x259] = 0x00820082 ; // 4 pxVbdBase->aulBulk[0x25a] = 0x00820082 ; // 5 pxVbdBase->aulBulk[0x25b] = 0x00820082 ; // 6 pxVbdBase->aulBulk[0x25c] = 0x00820082 ; // 7 pxVbdBase->aulBulk[0x25d] = 0x00820082 ; // 8 pxVbdBase->aulBulk[0x25e] = 0x00820000 ; // 9 pxVbdBase->aulBulk[0x25f] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x260] = 0xc5010000 ; // 1 st longword from Low half of 2nd channel pair pxVbdBase->aulBulk[0x261] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x262] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x263] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x264] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x265] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x266] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x267] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x268] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x269] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x26a] = 0x72060082 ; // 1 st longword from High half of 2nd channel pair pxVbdBase->aulBulk[0x26b] = 0x00820082 ; // 2 pxVbdBase->aulBulk[0x26c] = 0x00820082 ; // 3 pxVbdBase->aulBulk[0x26d] = 0x00820082 ; // 4 pxVbdBase->aulBulk[0x26e] = 0x00820082 ; // 5 pxVbdBase->aulBulk[0x26f] = 0x00820082 ; // 6 pxVbdBase->aulBulk[0x270] = 0x00820082 ; // 7 pxVbdBase->aulBulk[0x271] = 0x00820082 ; // 8 pxVbdBase->aulBulk[0x272] = 0x00820000 ; // 9 pxVbdBase->aulBulk[0x273] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x274] = 0xc3010000 ; // 1 st longword from Low half of 3rd channel pair pxVbdBase->aulBulk[0x275] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x276] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x277] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x278] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x279] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x27a] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x27b] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x27c] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x27d] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x27e] = 0x72060082 ; // 1 st longword from High half of 3rd channel pair pxVbdBase->aulBulk[0x27f] = 0x00820082 ; // 2 pxVbdBase->aulBulk[0x280] = 0x00820082 ; // 3 pxVbdBase->aulBulk[0x281] = 0x00820082 ; // 4 pxVbdBase->aulBulk[0x282] = 0x00820082 ; // 5 pxVbdBase->aulBulk[0x283] = 0x00820082 ; // 6 pxVbdBase->aulBulk[0x284] = 0x00820082 ; // 7 pxVbdBase->aulBulk[0x285] = 0x00820082 ; // 8 pxVbdBase->aulBulk[0x286] = 0x00820000 ; // 9 pxVbdBase->aulBulk[0x287] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x288] = 0xc2010000 ; // 1 st longword from Low half of 4th channel pair pxVbdBase->aulBulk[0x289] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x28a] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x28b] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x28c] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x28d] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x28e] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x28f] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x290] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x291] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x292] = 0x72060082 ; // 1 st longword from High half of 4th channel pair pxVbdBase->aulBulk[0x293] = 0x00820082 ; // 2 pxVbdBase->aulBulk[0x294] = 0x00820082 ; // 3 pxVbdBase->aulBulk[0x295] = 0x00820082 ; // 4 pxVbdBase->aulBulk[0x296] = 0x00820082 ; // 5 pxVbdBase->aulBulk[0x297] = 0x00820082 ; // 6 pxVbdBase->aulBulk[0x298] = 0x00820082 ; // 7 pxVbdBase->aulBulk[0x299] = 0x00820082 ; // 8 pxVbdBase->aulBulk[0x29a] = 0x00820000 ; // 9 pxVbdBase->aulBulk[0x29b] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x29c] = 0x00000000 ; // **** alignement word introduced by SBC **** pxVbdBase->aulBulk[0x29d] = 0x10e50030 ; // longword count for 1st VRB section pxVbdBase->aulBulk[0x29e] = 0x000000c0 ; // VRB Header:byte count pxVbdBase->aulBulk[0x29f] = 0xa1011200 ; // user info word & slot num byte & event num byte pxVbdBase->aulBulk[0x2a0] = 0x0a250002 ; // firmware version word & config info word pxVbdBase->aulBulk[0x2a1] = 0x00000000 ; // status word pxVbdBase->aulBulk[0x2a2] = 0x00280028 ; // byte count 1st channel pair pxVbdBase->aulBulk[0x2a3] = 0x00280028 ; // byte count 2nd channel pair pxVbdBase->aulBulk[0x2a4] = 0x00000000 ; // byte count 3rd channel pair pxVbdBase->aulBulk[0x2a5] = 0x00000000 ; // byte count 4th channel pair pxVbdBase->aulBulk[0x2a6] = 0xd5011f1f ; // 1 st longword from Low half of 1st channel pair pxVbdBase->aulBulk[0x2a7] = 0x1f1f1f1f ; // 2 pxVbdBase->aulBulk[0x2a8] = 0x1f1f1f26 ; // 3 pxVbdBase->aulBulk[0x2a9] = 0x89001f26 ; // 4 pxVbdBase->aulBulk[0x2aa] = 0x89001f26 ; // 5 pxVbdBase->aulBulk[0x2ab] = 0x89001f26 ; // 6 pxVbdBase->aulBulk[0x2ac] = 0x89001f26 ; // 7 pxVbdBase->aulBulk[0x2ad] = 0x89001f26 ; // 8 pxVbdBase->aulBulk[0x2ae] = 0x66000000 ; // 9 pxVbdBase->aulBulk[0x2af] = 0xff000072 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x2b0] = 0x720f6e6e ; // 1 st longword from High half of 1st channel pair pxVbdBase->aulBulk[0x2b1] = 0x6e6e6e6e ; // 2 pxVbdBase->aulBulk[0x2b2] = 0x6e6e6e05 ; // 3 pxVbdBase->aulBulk[0x2b3] = 0x00006e05 ; // 4 pxVbdBase->aulBulk[0x2b4] = 0x00006e05 ; // 5 pxVbdBase->aulBulk[0x2b5] = 0x00006e05 ; // 6 pxVbdBase->aulBulk[0x2b6] = 0x00006e05 ; // 7 pxVbdBase->aulBulk[0x2b7] = 0x00006e05 ; // 8 pxVbdBase->aulBulk[0x2b8] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x2b9] = 0xff000003 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x2ba] = 0xd3017206 ; // 1 st longword from Low half of 2nd channel pair pxVbdBase->aulBulk[0x2bb] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x2bc] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x2bd] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x2be] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x2bf] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x2c0] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x2c1] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x2c2] = 0x01000000 ; // 9 pxVbdBase->aulBulk[0x2c3] = 0xff000272 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x2c4] = 0x72071500 ; // 1 st longword from High half of 2nd channel pair pxVbdBase->aulBulk[0x2c5] = 0x00000000 ; // 2 pxVbdBase->aulBulk[0x2c6] = 0x00000000 ; // 3 pxVbdBase->aulBulk[0x2c7] = 0x00000000 ; // 4 pxVbdBase->aulBulk[0x2c8] = 0x00000000 ; // 5 pxVbdBase->aulBulk[0x2c9] = 0x00000000 ; // 6 pxVbdBase->aulBulk[0x2ca] = 0x00000000 ; // 7 pxVbdBase->aulBulk[0x2cb] = 0x00000000 ; // 8 pxVbdBase->aulBulk[0x2cc] = 0x00000000 ; // 9 pxVbdBase->aulBulk[0x2cd] = 0xff000303 ; // 10 longwords = 40 bytes = 0x28 pxVbdBase->aulBulk[0x2ce] = 0x5526aad9 ; // pxVbdBase->aulBulk[0x2cf] = 0x663799c8 ; // /* This gives the following dump I$ -------- VBD Event Formatted Dump and Analysis -------- I$ I$ Dumping from VBD Card @Slot#4: I$ I$ VBD Header : Tot Event LongWord= 0x2bc Crate ID= 0x1f L3 Transfer Num= 0x7d01 I$ I$ VRB # 1 : Tot LongWord= 0x58 I$ VRB Header : Tot Byte= 0x160 Event Num= 0x00 Slot= 0x13 I$ : Slot= 19 Format= V1.1 Config= 0x0002 Firmware= 0x0a25 I$ : Unused Status Word= 0x00000000 I$ : Byte Count Ch # 1 = 0x0028 Ch # 0 = 0x0028 I$ : Byte Count Ch # 3 = 0x0028 Ch # 2 = 0x0028 I$ : Byte Count Ch # 5 = 0x0028 Ch # 4 = 0x0028 I$ : Byte Count Ch # 7 = 0x0028 Ch # 6 = 0x0028 I$ I$ Ch#0&1 : I$ HSRO Header : THE-Card= M123-Top-10 Event Num= 0x72 Primary FPGA= V6.1 I$ FPGA 1- 4 : 0x0000 0x2830 0x0000 0x0d1e 0x0000 0x8200 0x0000 0x8200 I$ FPGA 5- 8 : 0x0000 0x68b0 0x0000 0x0d1e 0x0000 0x8200 0x0000 0x8200 I$ FPGA 9-12 : 0x0000 0x49b0 0x0000 0x0d1e 0x0000 0x8200 0x0000 0x8200 I$ FPGA 13-16 : 0x0000 0x1170 0x0000 0x0d1e 0x0000 0x8200 0x0000 0x8200 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#2&3 : I$ HSRO Header : THE-Card= M123-Top-9 Event Num= 0x72 Primary FPGA= V6.1 I$ FPGA 1- 4 : 0x0000 0x8200 0x0000 0x80e7 0x0000 0x8200 0x0000 0x8200 I$ FPGA 5- 8 : 0x0000 0x8200 0x0000 0x80e7 0x0000 0x8200 0x0000 0x8200 I$ FPGA 9-12 : 0x0000 0x8200 0x0000 0x80e7 0x0000 0x8200 0x0000 0x8200 I$ FPGA 13-16 : 0x0000 0x8200 0x0000 0x80e7 0x0000 0x8200 0x0000 0x8200 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#4&5 : I$ HSRO Header : THE-Card= M123-Top-3 Event Num= 0x72 Primary FPGA= V6.1 I$ FPGA 1- 4 : 0x0000 0x04e4 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 5- 8 : 0x0000 0x04e4 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 9-12 : 0x0000 0x04e4 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 13-16 : 0x0000 0x04e4 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#6&7 : I$ HSRO Header : THE-Card= M123-Top-2 Event Num= 0x72 Primary FPGA= V6.1 I$ FPGA 1- 4 : 0x0000 0x80e7 0x0000 0x3400 0x0000 0x8200 0x0000 0x8200 I$ FPGA 5- 8 : 0x0000 0x80e7 0x0000 0x7480 0x0000 0x8200 0x6262 0x8200 I$ FPGA 9-12 : 0x0000 0x80e7 0xcccc 0x4990 0x0000 0x8200 0x0000 0x8200 I$ FPGA 13-16 : 0x0000 0x80e7 0x3333 0x0910 0x0000 0x8200 0x8888 0x8200 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ VRB # 2 : Tot LongWord= 0x58 I$ VRB Header : Tot Byte= 0x160 Event Num= 0x00 Slot= 0x09 I$ : Slot= 9 Format= V1.1 Config= 0x0002 Firmware= 0x0a25 I$ : Unused Status Word= 0x00000000 I$ : Byte Count Ch # 1 = 0x0028 Ch # 0 = 0x0028 I$ : Byte Count Ch # 3 = 0x0028 Ch # 2 = 0x0028 I$ : Byte Count Ch # 5 = 0x0028 Ch # 4 = 0x0028 I$ : Byte Count Ch # 7 = 0x0028 Ch # 6 = 0x0028 I$ I$ Ch#0&1 : I$ HSRO Header : THE-Card= M123-Top-14 Event Num= 0x72 Primary FPGA= V32.3 I$ FPGA 1- 4 : 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff I$ FPGA 5- 8 : 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff I$ FPGA 9-12 : 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff I$ FPGA 13-16 : 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#2&3 : I$ HSRO Header : THE-Card= M123-Top-13 Event Num= 0x72 Primary FPGA= V32.3 I$ FPGA 1- 4 : 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff I$ FPGA 5- 8 : 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff I$ FPGA 9-12 : 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff I$ FPGA 13-16 : 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff 0xffff I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#4&5 : I$ HSRO Header : THE-Card= M123-Top-7 Event Num= 0x72 Primary FPGA= V32.3 I$ FPGA 1- 4 : 0x1111 0x1111 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 5- 8 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 9-12 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 13-16 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#6&7 : I$ HSRO Header : THE-Card= M123-Top-6 Event Num= 0x72 Primary FPGA= V32.3 I$ FPGA 1- 4 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 5- 8 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 9-12 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 13-16 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ VRB # 3 : Tot LongWord= 0x44 I$ VRB Header : Tot Byte= 0x110 Event Num= 0x00 Slot= 0x0a I$ : Slot= 10 Format= V1.1 Config= 0x0002 Firmware= 0x0a25 I$ : Unused Status Word= 0x00000000 I$ : Byte Count Ch # 1 = 0x0028 Ch # 0 = 0x0028 I$ : Byte Count Ch # 3 = 0x0028 Ch # 2 = 0x0028 I$ : Byte Count Ch # 5 = 0x0028 Ch # 4 = 0x0028 I$ : Byte Count Ch # 7 = 0x0000 Ch # 6 = 0x0000 I$ I$ Ch#0&1 : I$ HSRO Header : THE-Card= M123-Top-20 Event Num= 0x72 Primary FPGA= V1.1 I$ FPGA 1- 4 : 0x0000 0x0000 0x0000 0x0000 0x9209 0xcafe 0x0441 0x0006 I$ FPGA 5- 8 : 0x0000 0x0000 0x0000 0x0000 0x1b01 0x1b02 0x0000 0x0000 I$ FPGA 9-12 : 0x8182 0x8384 0x9192 0x9394 0xa1a2 0xa3a4 0xb1b2 0xb3b4 I$ FPGA 13-16 : 0xc1c2 0xc3c4 0xd1d2 0xd3d4 0xe1e2 0xe3e4 0xf1f2 0xf3f4 I$ BSF Data : P5 I/O= 0x0000ff9f Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ I$ VRB # 4 : Tot LongWord= 0x44 I$ VRB Header : Tot Byte= 0x110 Event Num= 0x00 Slot= 0x0b I$ : Slot= 11 Format= V1.1 Config= 0x0002 Firmware= 0x0a25 I$ : Unused Status Word= 0x00000000 I$ : Byte Count Ch # 1 = 0x0028 Ch # 0 = 0x0028 I$ : Byte Count Ch # 3 = 0x0028 Ch # 2 = 0x0028 I$ : Byte Count Ch # 5 = 0x0028 Ch # 4 = 0x0028 I$ : Byte Count Ch # 7 = 0x0000 Ch # 6 = 0x0000 I$ I$ Ch#0&1 : I$ HSRO Header : THE-Card= M123-Top-17 Event Num= 0x72 Primary FPGA= V6.1 I$ FPGA 1- 4 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 5- 8 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x2222 0x8200 I$ FPGA 9-12 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x4444 0x8200 I$ FPGA 13-16 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#2&3 : I$ HSRO Header : THE-Card= M123-Top-16 Event Num= 0x72 Primary FPGA= V6.1 I$ FPGA 1- 4 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 5- 8 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 9-12 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 13-16 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#4&5 : I$ HSRO Header : THE-Card= M123-Top-19 Event Num= 0x72 Primary FPGA= V1.2 I$ FPGA 1- 4 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 5- 8 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0420 0x0000 0x0420 I$ FPGA 9-12 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 13-16 : 0x0000 0x0000 0x0000 0x0420 0x0000 0x0000 0x0000 0x0000 I$ BSF Data : P5 I/O= 0x00007edf Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V5.1 I$ I$ I$ VRB # 5 : Tot LongWord= 0x58 I$ VRB Header : Tot Byte= 0x160 Event Num= 0x00 Slot= 0x0c I$ : Slot= 12 Format= V1.1 Config= 0x0002 Firmware= 0x0a25 I$ : Unused Status Word= 0x00000000 I$ : Byte Count Ch # 1 = 0x0028 Ch # 0 = 0x0028 I$ : Byte Count Ch # 3 = 0x0028 Ch # 2 = 0x0028 I$ : Byte Count Ch # 5 = 0x0028 Ch # 4 = 0x0028 I$ : Byte Count Ch # 7 = 0x0028 Ch # 6 = 0x0028 I$ I$ Ch#0&1 : I$ HSRO Header : THE-Card= M123-Mid-11 Event Num= 0x72 Primary FPGA= V24.1 I$ FPGA 1- 4 : 0x57f9 0x6000 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 5- 8 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 9-12 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 13-16 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ BSF Data : P5 I/O= 0x0001ffff Global I/O= 0x00000001 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#2&3 : I$ HSRO Header : THE-Card= M123-Mid-10 Event Num= 0x72 Primary FPGA= V24.1 I$ FPGA 1- 4 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 5- 8 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 9-12 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 13-16 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#4&5 : I$ HSRO Header : THE-Card= M123-Mid-9 Event Num= 0x72 Primary FPGA= V24.1 I$ FPGA 1- 4 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 5- 8 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 9-12 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 13-16 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#6&7 : I$ HSRO Header : THE-Card= M123-Mid-8 Event Num= 0x72 Primary FPGA= V24.1 I$ FPGA 1- 4 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 5- 8 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 9-12 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 13-16 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ VRB # 6 : Tot LongWord= 0x58 I$ VRB Header : Tot Byte= 0x160 Event Num= 0x00 Slot= 0x0d I$ : Slot= 13 Format= V1.1 Config= 0x0002 Firmware= 0x0a25 I$ : Unused Status Word= 0x00000000 I$ : Byte Count Ch # 1 = 0x0028 Ch # 0 = 0x0028 I$ : Byte Count Ch # 3 = 0x0028 Ch # 2 = 0x0028 I$ : Byte Count Ch # 5 = 0x0028 Ch # 4 = 0x0028 I$ : Byte Count Ch # 7 = 0x0028 Ch # 6 = 0x0028 I$ I$ Ch#0&1 : I$ HSRO Header : THE-Card= M123-Mid-7 Event Num= 0x72 Primary FPGA= V24.1 I$ FPGA 1- 4 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 5- 8 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 9-12 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 13-16 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#2&3 : I$ HSRO Header : THE-Card= M123-Mid-6 Event Num= 0x72 Primary FPGA= V24.1 I$ FPGA 1- 4 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 5- 8 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 9-12 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 13-16 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#4&5 : I$ HSRO Header : THE-Card= M123-Mid-5 Event Num= 0x72 Primary FPGA= V24.1 I$ FPGA 1- 4 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 5- 8 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 9-12 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 13-16 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#6&7 : I$ HSRO Header : THE-Card= M123-Mid-4 Event Num= 0x72 Primary FPGA= V24.1 I$ FPGA 1- 4 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 5- 8 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 9-12 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ FPGA 13-16 : 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 0x47a0 0x2001 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ VRB # 7 : Tot LongWord= 0x44 I$ VRB Header : Tot Byte= 0x110 Event Num= 0x00 Slot= 0x10 I$ : Slot= 16 Format= V1.1 Config= 0x0002 Firmware= 0x0a25 I$ : Unused Status Word= 0x00000000 I$ : Byte Count Ch # 1 = 0x0028 Ch # 0 = 0x0028 I$ : Byte Count Ch # 3 = 0x0028 Ch # 2 = 0x0028 I$ : Byte Count Ch # 5 = 0x0028 Ch # 4 = 0x0028 I$ : Byte Count Ch # 7 = 0x0000 Ch # 6 = 0x0000 I$ I$ Ch#0&1 : I$ HSRO Header : THE-Card= M123-Mid-15 Event Num= 0x72 Primary FPGA= V1.2 I$ FPGA 1- 4 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 5- 8 : 0x0010 0x0010 0x0000 0x0000 0x0000 0x0000 0x0080 0x0080 I$ FPGA 9-12 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 13-16 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#2&3 : I$ HSRO Header : THE-Card= M123-Mid-14 Event Num= 0x72 Primary FPGA= V1.2 I$ FPGA 1- 4 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 5- 8 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 9-12 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 13-16 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0080 0x0080 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0xfc Secondary FPGA= V0.0 E$ : Event Number Mismatch between HSRO Header and Trailer I$ I$ Ch#4&5 : I$ HSRO Header : THE-Card= M123-Mid-16 Event Num= 0x72 Primary FPGA= V3.1 I$ FPGA 1- 4 : 0x0000 0x992f 0x0000 0x992f 0x0000 0x992f 0x0000 0x992f I$ FPGA 5- 8 : 0x0000 0x992f 0x0000 0x992f 0x0000 0x992f 0x0000 0x992f I$ FPGA 9-12 : 0x00f0 0x992f 0x00f0 0x992f 0x1ff0 0x992f 0x0000 0x992f I$ FPGA 13-16 : 0x0001 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V5.1 I$ I$ I$ VRB # 8 : Tot LongWord= 0x58 I$ VRB Header : Tot Byte= 0x160 Event Num= 0x00 Slot= 0x11 I$ : Slot= 17 Format= V1.1 Config= 0x0002 Firmware= 0x0a25 I$ : Unused Status Word= 0x00000000 I$ : Byte Count Ch # 1 = 0x0028 Ch # 0 = 0x0028 I$ : Byte Count Ch # 3 = 0x0028 Ch # 2 = 0x0028 I$ : Byte Count Ch # 5 = 0x0028 Ch # 4 = 0x0028 I$ : Byte Count Ch # 7 = 0x0028 Ch # 6 = 0x0028 I$ I$ Ch#0&1 : I$ HSRO Header : THE-Card= M123-Bot-6 Event Num= 0x72 Primary FPGA= V6.1 I$ FPGA 1- 4 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 5- 8 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 9-12 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 13-16 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#2&3 : I$ HSRO Header : THE-Card= M123-Bot-5 Event Num= 0x72 Primary FPGA= V6.1 I$ FPGA 1- 4 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 5- 8 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 9-12 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 13-16 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#4&5 : I$ HSRO Header : THE-Card= M123-Bot-3 Event Num= 0x72 Primary FPGA= V6.1 I$ FPGA 1- 4 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 5- 8 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 9-12 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 13-16 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#6&7 : I$ HSRO Header : THE-Card= M123-Bot-2 Event Num= 0x72 Primary FPGA= V6.1 I$ FPGA 1- 4 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 5- 8 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 9-12 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ FPGA 13-16 : 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 0x0000 0x8200 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ VRB # 9 : Tot LongWord= 0x30 I$ VRB Header : Tot Byte= 0xc0 Event Num= 0x00 Slot= 0x12 I$ : Slot= 18 Format= V1.1 Config= 0x0002 Firmware= 0x0a25 I$ : Unused Status Word= 0x00000000 I$ : Byte Count Ch # 1 = 0x0028 Ch # 0 = 0x0028 I$ : Byte Count Ch # 3 = 0x0028 Ch # 2 = 0x0028 I$ : Byte Count Ch # 5 = 0x0000 Ch # 4 = 0x0000 I$ : Byte Count Ch # 7 = 0x0000 Ch # 6 = 0x0000 I$ I$ Ch#0&1 : I$ HSRO Header : THE-Card= M123-Bot-21 Event Num= 0x72 Primary FPGA= V15.1 I$ FPGA 1- 4 : 0x6e1f 0x6e1f 0x6e1f 0x6e1f 0x6e1f 0x6e1f 0x6e1f 0x6e1f I$ FPGA 5- 8 : 0x6e1f 0x0526 0x0089 0x0000 0x6e1f 0x0526 0x0089 0x0000 I$ FPGA 9-12 : 0x6e1f 0x0526 0x0089 0x0000 0x6e1f 0x0526 0x0089 0x0000 I$ FPGA 13-16 : 0x6e1f 0x0526 0x0089 0x0000 0x6e1f 0x0526 0x0066 0x0000 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V0.0 I$ I$ Ch#2&3 : I$ HSRO Header : THE-Card= M123-Bot-19 Event Num= 0x72 Primary FPGA= V7.1 I$ FPGA 1- 4 : 0x1572 0x0006 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 5- 8 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 9-12 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 I$ FPGA 13-16 : 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001 0x0000 I$ BSF Data : P5 I/O= 0x0000ffff Global I/O= 0x00000000 I$ HSRO Trailer : Status Flags= 0x03 Event Num= 0x72 Secondary FPGA= V3.2 I$ E$ : Channel Pair #4&5 would be past the end of the Event in the VBD E$ Aborting VBD Event Dump Analysis */