////////////////////////////////////////////////////////////////////////////// // File: L1_Tcc_Monit_Data_SpTrg.hpp // Created: 07-OCT-2001 Philippe Laurens (split away from Tcc_Monit_Data.hpp) ////////////////////////////////////////////////////////////////////////////// #ifndef __L1_Tcc_Monit_Data_SpTrg__ #define __L1_Tcc_Monit_Data_SpTrg__ ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// // array dimension parameters (used in definition or usage of some of the structures Below) #define kTcc_L1fw_Tot_SpTrg 128 // Total Number of Specific Triggers #define kTcc_L1fw_Tot_IndivDis 2 // Total Number of Sources of Individual SpTrg Disable /////////////////////////////////////////////////////////////////////////////////// // Specific Trigger Monitoring Sub-Structure (used in definition of Monitoring Data Blocks) // This data structure is obsolete in implementation phase 6 // It is replaced by Tcc_Fw_Specific_Trigger below /////////////////////////////////////////////////////////////////////////////////// #ifdef TCC_SUPPORT_PHASE3_MONIT_DATA struct Tcc_L1fw_Specific_Trigger { // SpTrg Allocated: Non-Zero if COOR has allocated the specific trigger uint8 ubAllocated ; // ID Number of the Exposure Group this Spec Trig belongs to. uint8 ubExpGrpNum ; // Mask of which sources of disable are being obeyed // cf. compiler constants kTcc_SpTrg_Obey_** below for definition of bit location uint16 uwObeyDisableMask ; // SpTrg Fired Count uint64 uqSpTrgFired ; // SpTrg And-Or Fired Count uint64 uqAndOrFired ; // SpTrg Fired Exposed Count // this is the number of crossing for which the SpTrg was enabled to fire // with all possible sources of disable included // i.e. - Exposure Group Front End Busy // - All 4 Sources of Correlated Global Disable // - Coor Disable // - Both Sources of Individual Spec Trig Disable // - All 4 Sources of DeCorrelated Global Disable // - Auto Disable // - Prescaler Disable // - Exposure Group And-Or Requirement uint64 uqSpTrgExposed ; // SpTrg Fired DAQ Enable Count // this is the number of crossing for which the SpTrg was enabled to fire // with all possible sources of DAQ disable included // i.e. all sources of disable except the Exposure Group And-Or Fired // i.e. - Exposure Group Front End Busy // - All 4 Sources of Correlated Global Disable // - Coor Disable // - Both Sources of Individual Spec Trig Disable // - All 4 Sources of DeCorrelated Global Disable // - Auto Disable // - Prescaler Disable uint64 uqDaqEnable ; // SpTrg DAQ DeCorrelated Enable Count // this is the number of crossing for which the SpTrg was enabled to fire // with all possible sources of disable included // i.e. - Coor Disable // - Auto Disable // - Prescaler Disable // - Both Sources of Individual Spec Trig Disable // - All 4 Sources of DeCorrelated Global Disable uint64 uqDeCorrDaqEnable ; // SpTrg DAQ Correlated Enable Count // this is the number of crossing for which the SpTrg was enabled to fire // with all possible sources of disable included // i.e. all correlated sources except the Exposure Group And-Or Fired // i.e. - Exposure Group Front End Busy // - All 4 Sources of Correlated Global Disable uint64 uqCorrDaqEnable ; // SpTrg Individual Disable Count // Correlated Source #0: L3 Individual SpTrg Disable // Correlated Source #1: Unused uint64 auqIndivDisable[kTcc_L1fw_Tot_IndivDis] ; // SpTrg Prescaler Disable Count uint64 uqPrescalerDisable ; // SpTrg Auto Disable Count uint64 uqAutoDisable ; // SpTrg Coor Disable Count uint64 uqCoorDisable ; } ; #endif // TCC_SUPPORT_PHASE3_MONIT_DATA /////////////////////////////////////////////////////////////////////////////////// // Specific Trigger Monitoring Sub-Structure (used in definition of Monitoring Data Blocks) // This is the expanded definition for Phase 6 /////////////////////////////////////////////////////////////////////////////////// // cf. http://www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/tdm/tdm_fpga_description.txt // for details on the Andor Fired, Exposed, Daq Enable, Correlated and DeCorrelated Enable, // Coor Enable, Prescaler, and autodisable Scalers struct L1_Tcc_Fw_Spec_Trig_Brief // For general use, e.g. Daq Monitor { // SpTrg Allocated: Non-Zero if COOR has allocated the specific trigger uint8 ubAllocated ; // ID Number of the Exposure Group this Spec Trig belongs to. uint8 ubExpGrpNum ; // Reserved uint16 uwReserved ; // Specific Trigger Obey Disable Mask // bit #0 : 1 = Spec Trig is currently disabled by COOR // bit #1 : 1 = Spec Trig is Prescaled // bit #2 : 1 = Spec Trig is Auto Disabled // bit #3 : Unused // bit #4 : 1 = Spec Trig Obey Indiv Disable #0 // bit #5 : 1 = Spec Trig Obey Indiv Disable #1 // bit #6-7: Unused // bit #8 : 1 = Spec Trig Obey Global Correlated Disable #0 // bit #9 : 1 = Spec Trig Obey Global Correlated Disable #1 // bit #10 : 1 = Spec Trig Obey Global Correlated Disable #2 // bit #11 : 1 = Spec Trig Obey Global Correlated Disable #3 // bit #12 : 1 = Spec Trig Obey Global DeCorrelated Disable #0 // bit #13 : 1 = Spec Trig Obey Global DeCorrelated Disable #1 // bit #14 : 1 = Spec Trig Obey Global DeCorrelated Disable #2 // bit #15 : 1 = Spec Trig Obey Global DeCorrelated Disable #3 uint16 uwObeyDisableMask ; // Specific Trigger Programming Mask // bit #0 : 1 = Specific Trigger programmed for Force_l2Reject (SQAQ) // bit #1-7: Unused uint8 ubProgrMask ; // Prescaler Percentage uint8 ubPrescalerPercent ; // Prescaler Ratio uint32 ulPrescalerRatio ; // L1 SpTrg Fired Count uint32 ulL1Fired ; // SpTrg And-Or Fired Count uint64 uqAndOrFired ; // SpTrg Fired Exposed BeamX Count // this is the number of crossing for which the SpTrg was enabled to fire // with all possible sources of disable included // i.e. - Exposure Group Front End Busy // - All 4 Sources of Correlated Global Disable // - Coor Disable // - Both Sources of Individual Spec Trig Disable // - All 4 Sources of DeCorrelated Global Disable // - Auto Disable // - Prescaler Disable // - Exposure Group And-Or Requirement uint64 uqSpTrgExposed ; // SpTrg DAQ DeCorrelated Enable BeamX Count // this is the number of crossing for which the SpTrg was enabled to fire // with all possible sources of disable included // i.e. - Coor Disable // - Auto Disable // - Prescaler Disable // - Both Sources of Individual Spec Trig Disable // - All 4 Sources of DeCorrelated Global Disable uint64 uqDeCorrDaqEnable ; // L3 SpTrg Individual Disable BeamX Count uint64 uqL3Disable ; // SpTrg Coor Disable BeamX Count uint64 uqCoorDisable ; // Count of L1 SpTrg Fired Processed by the L2 FW. // This number may lag behind ulL1Fired as the events are FIFOed // coming into the L2 FW while the L2 Trigger processes previous events. // (this data is read from the L2FW L1 Fired TRM) uint32 ulL2fwProcessed ; // L2 Framework SpTrg Accept Count // This is the L2 Decision masked by the original L1 Fired Mask. // To compute a L2 Accept fraction, devide ulL2fwAccept by ulL2fwProcessed. // The L2 Reject fraction is the complement to 1 of the L2 Accept fraction. // This will always match the L2 Decision Scaler unless the L2 Global // tries to confirm L1 Spec Triggers that hadn't fired. // (this data is read from the L2FW L2 Accept AONM) uint32 ulL2fwAccept ; // L2 Unbiased Sample Ratio // This is the fraction of events (L1 Accepted by this Specific Trigger) // that will set the L2 Unbiased Sample L1 Qualifier // and will thus be Marked and Passed by the L2 Trigger uint32 ulL2UnbiasedSample ; // Reserved uint32 ulReserved1 ; uint32 ulReserved2 ; uint32 ulReserved3 ; } ; ////////////////////////////////////////////////////////////////////////////// struct L1_Tcc_Fw_Spec_Trig_Full // For the Trigger Expert { // SpTrg Allocated: Non-Zero if COOR has allocated the specific trigger uint8 ubAllocated ; // ID Number of the Exposure Group this Spec Trig belongs to. uint8 ubExpGrpNum ; // Reserved uint16 uwReserved ; // Specific Trigger Obey Disable Mask // bit #0 : 1 = Spec Trig is currently disabled by COOR // bit #1 : 1 = Spec Trig is Prescaled // bit #2 : 1 = Spec Trig is Auto Disabled // bit #3 : Unused // bit #4 : 1 = Spec Trig Obey Indiv Disable #0 // bit #5 : 1 = Spec Trig Obey Indiv Disable #1 // bit #6-7: Unused // bit #8 : 1 = Spec Trig Obey Global Correlated Disable #0 // bit #9 : 1 = Spec Trig Obey Global Correlated Disable #1 // bit #10 : 1 = Spec Trig Obey Global Correlated Disable #2 // bit #11 : 1 = Spec Trig Obey Global Correlated Disable #3 // bit #12 : 1 = Spec Trig Obey Global DeCorrelated Disable #0 // bit #13 : 1 = Spec Trig Obey Global DeCorrelated Disable #1 // bit #14 : 1 = Spec Trig Obey Global DeCorrelated Disable #2 // bit #15 : 1 = Spec Trig Obey Global DeCorrelated Disable #3 uint16 uwObeyDisableMask ; // Specific Trigger Programming Mask // bit #0 : 1 = Specific Trigger programmed for Force_l2Reject (SQAQ) // bit #1-7: Unused uint8 ubProgrMask ; // Prescaler Percentage uint8 ubPrescalerPercent ; // Prescaler Ratio uint32 ulPrescalerRatio ; // L1 SpTrg Fired Count uint32 ulL1Fired ; // Specific Trigger Programming of AndOr Input Term requirements // - bit #n of uqAoitRequiredAsserted_m_p is set to 1 // when the corresponding Andor Term (#m+n) // is required asserted by this Specific Trigger // - bit #n of uqAoitRequiredNegatedted_m_p is set to 1 // when the corresponding Andor Term (#m+n) // is required as veto by this Specific Trigger uint64 uqAoitRequiredAsserted_0_63 ; // LSB is AndOr Term #0 uint64 uqAoitRequiredAsserted_64_127 ; uint64 uqAoitRequiredAsserted_128_191 ; uint64 uqAoitRequiredAsserted_192_255 ; // MSB is AndOr Term #255 uint64 uqAoitRequiredNegated_0_63 ; // LSB is AndOr Term #0 uint64 uqAoitRequiredNegated_64_127 ; uint64 uqAoitRequiredNegated_128_191 ; uint64 uqAoitRequiredNegated_192_255 ; // MSB is AndOr Term #255 // SpTrg And-Or Fired Count uint64 uqAndOrFired ; // SpTrg Fired Exposed BeamX Count // this is the number of crossing for which the SpTrg was enabled to fire // with all possible sources of disable included // i.e. - Exposure Group Front End Busy // - All 4 Sources of Correlated Global Disable // - Coor Disable // - Both Sources of Individual Spec Trig Disable // - All 4 Sources of DeCorrelated Global Disable // - Auto Disable // - Prescaler Disable // - Exposure Group And-Or Requirement uint64 uqSpTrgExposed ; // SpTrg Fired DAQ Enable BeamX Count // this is the number of crossing for which the SpTrg was enabled to fire // with all possible sources of DAQ disable included // i.e. all sources of disable except the Exposure Group And-Or Fired // i.e. - Exposure Group Front End Busy // - All 4 Sources of Correlated Global Disable // - Coor Disable // - Both Sources of Individual Spec Trig Disable // - All 4 Sources of DeCorrelated Global Disable // - Auto Disable // - Prescaler Disable uint64 uqDaqEnable ; // SpTrg DAQ DeCorrelated Enable BeamX Count // this is the number of crossing for which the SpTrg was enabled to fire // with all possible sources of disable included // i.e. - Coor Disable // - Auto Disable // - Prescaler Disable // - Both Sources of Individual Spec Trig Disable // - All 4 Sources of DeCorrelated Global Disable uint64 uqDeCorrDaqEnable ; // SpTrg DAQ Correlated Enable BeamX Count // this is the number of crossing for which the SpTrg was enabled to fire // with all possible sources of disable included // i.e. all correlated sources except the Exposure Group And-Or Fired // i.e. - Exposure Group Front End Busy // - All 4 Sources of Correlated Global Disable uint64 uqCorrDaqEnable ; // SpTrg Individual Disable BeamX Count // Correlated Source #0: L3 Individual SpTrg Disable // Correlated Source #1: Unused uint64 auqIndivDisable[kTcc_L1fw_Tot_IndivDis] ; // SpTrg Prescaler Disable BeamX Count uint64 uqPrescalerDisable ; // SpTrg Auto Disable BeamX Count uint64 uqAutoDisable ; // SpTrg Coor Disable BeamX Count uint64 uqCoorDisable ; // Count of L1 SpTrg Fired Processed by the L2 FW // (this data is read from the L2FW L1 Fired TRM) uint32 ulL2fwProcessed ; // L2 GLobal SpTrg Accept Count // (this data is read from the L2FW L2 Global Answer TRM) uint32 ulL2GlbAccept ; // L2 Framework SpTrg Accept Count // This is the L2 Decision masked by the original L1 Fired Mask // This should match the L2 Decision Scaler unless the L2 Global // occasionally tries to confirm a L1 Spec Trigger that hadn't fired // (this data is read from the L2FW L2 Accept AONM) uint32 ulL2fwAccept ; // L2 Framework SpTrg Reject Count // (this data is read from the L2FW L2 Reject AONM) uint32 ulL2fwReject ; // Specific Trigger Programming of L1 Qualifier Requirements // - bit #0 (1,..15) of ulL1QualRequired0_31 is set to 1 // when the corresponding L1 Qualifier #0 (1,..15) of the Lower Set // of L1 Qualifiers is required to be sent by this Specific Trigger // - bit #16 (17,..31) of ulL1QualRequired0_31 is set to 1 // when the corresponding L1 Qualifier #0 (1,..15) of the Upper Set // of L1 Qualifiers is required to be sent by this Specific Trigger uint32 ulL1QualRequired0_31 ; // LSB is Lower Set L1 Qual #0 // MSB is Upper Set L1 Qual #15 // L2 Unbiased Sample Ratio // This is the fraction of events (L1 Accepted by this Specific Trigger) // that will set the L2 Unbiased Sample L1 Qualifier // and will thus be Marked and Passed by the L2 Trigger uint32 ulL2UnbiasedSample ; } ; ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// // constants to use to parse the uwObeyDisableMask field of // the Tcc_L1fw_Specific_Trigger structure above // if the AND of one of these constants with the uwObeyDisableMask field is not Zero, // the Specific Trigger is programmed to obey the corresponding source of disable #define kTcc_SpTrg_Coor_Disable 0x0001 // Spec Trig is currently disabled by COOR #define kTcc_SpTrg_Obey_Prescaler 0x0002 // Spec Trig is Prescaled #define kTcc_SpTrg_Obey_AutoDis 0x0004 // Spec Trig is Auto Disabled #define kTcc_SpTrg_Obey_IndivDis0 0x0010 // Spec Trig Obey Indiv Disable #0 #define kTcc_SpTrg_Obey_IndivDis1 0x0020 // Spec Trig Obey Indiv Disable #1 #define kTcc_SpTrg_Obey_CorrGlobDis0 0x0100 // Spec Trig Obey Global Correlated Disable #0 #define kTcc_SpTrg_Obey_CorrGlobDis1 0x0200 // Spec Trig Obey Global Correlated Disable #1 #define kTcc_SpTrg_Obey_CorrGlobDis2 0x0400 // Spec Trig Obey Global Correlated Disable #2 #define kTcc_SpTrg_Obey_CorrGlobDis3 0x0800 // Spec Trig Obey Global Correlated Disable #3 #define kTcc_SpTrg_Obey_DeCorrGlobDis0 0x1000 // Spec Trig Obey Global DeCorrelated Disable #0 #define kTcc_SpTrg_Obey_DeCorrGlobDis1 0x2000 // Spec Trig Obey Global DeCorrelated Disable #1 #define kTcc_SpTrg_Obey_DeCorrGlobDis2 0x4000 // Spec Trig Obey Global DeCorrelated Disable #2 #define kTcc_SpTrg_Obey_DeCorrGlobDis3 0x8000 // Spec Trig Obey Global DeCorrelated Disable #3 // parameter to use to parse the ubProgrMask field of // the L1_Tcc_Fw_Spec_Trig_Brief/Full structures above #define kTcc_SpTrg_Progr_ForceL2Reject 0X01 // Spec Trig programmed for Force_l2Reject (SQAQ) // parameter to use as an index with the auqIndivDisable field of the Tcc_L1fw_Specific_Trigger data structure #define kTcc_L1fw_IndivDisable_L3 0 ///////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// #endif // __L1_Tcc_Monit_Data_SpTrg__