-------------------------------------------------------------------------------- TRICS II Version 10.0 Release Notes ------------------------- 11-Apr-2002: (Rev H) General Switch from very old versions of libraries to current versions ITC v00-00-07 -> v02-14-00 Thread_Util v00-02-00 -> v00-10-01 Ace V5.0 -> V5.1.17 Change method of implementing Force L2 Reject (cf. below) Reset the L2 Answer TRM during SCL Init (cf. Below) Implement new Register Dump feature (cf. below) Implement the "L2 Unbiased Sample" control programming (cf. below) Initialize the new Tick and Turn Fpgas with control of which scalers get reset by the hardware SCL Initialize. The Download file will need to be updated to load new TTS FPGA in all sites, but this upgrade should be backwards compatible with the old TTS FPGA. New messages to siwtch Mode for Ignore/Obey L2 Global Answer (cf. below) New message to sepcify the L2 Data Path (cf. below) Add support for Sin(Phi) and Cos(Phi) function in slope of Momemtum Lookup PROMs (cf. below) Stir the soup, hopefully for increased long term ease of maintenance: Cleanup some COOR message names and command file names that have drifted enough from the original intention to become a possible source of confusion. (cf. COOR messages and Master Command File Menu below) COOR Messages: Rename the following messages to match reality "L1FW_Configure" -> "Configure_FPGAs" "L1FW_Initialize" -> "Full_Initialize" as both messages act on L1FW, L2FW, and L1CT Note that this is transparent to COOR which never sends the Configure message, and uses the COOR-imposed keyword "init" which was (as far as TRICS is concerned) made into a synonym to "L1FW_Initialize" and is now a synonym to "Full_Initialize". Rename the underlying Master Command file to match. Configure_L1FW.mcf -> Configure_FPGAs.mcf This file is executed when a "Configure_FPGAs" message is received. The Master Command Files associated with "Full_Initialize" haven't changed (Init_Pre_Auxi.mcf and Init_Post_Auxi_L1FW/L1CT.mcf). Also rename the Master Command File associated with SCL_Initialize Init_SCL.mcf -> SCL_Initialize.mcf since it arlready calls a file called SCL_Initialize.rio, and "Initialize SCL" gives the wrong idea as it only sends the "SCL_Init" flag but does not initialize the SCL Hub End (Full_Initialize does that). Update the TRICS menu to provide the correct message templates. Add some header comments to all these files. Master Command File Menu: Rename Buttons: "Configure L1&L2 Frameworks" -> "Configure All FPGAs" "Initialize L1&L2 Frameworks" -> "Initialize L1FW, L2FW, L1CT" Rename config_l1fw.mcf -> config_FPGAs.mcf in \trics\d0_config\ Rename the underlying Master Command files to match. Configure_Frameworks.mcf -> Request_Configure_FPGAs.mcf Init_Frameworks.mcf -> Request_Full_Initialize.mcf Init_SCL_with_Pause_Resume.mcf -> Request_SCL_Initialize.mcf These are the files that get executed to request the message to be sent. The name is changed to make the "request" part more explicit, and to match the command being requested. The former name was also too similar to the commands that get executed during command processing. Add some header comments to all these files Console and Logfile messages: Upgrade the Console Screen output and LogFile output utilities for two real purposes and for generic cleanup: - increase the maximum line length handled Some COOR messages were beeing truncated on the screen and logfile Strings still too long to be handled will get a '?' for the last character - replace the former continuation tag in the logfile ("_$" for the second part of a split line) with enough smarts to copy the original tag (M$, I$, E$, etc) but in lowercase (m$, i$, e$, etc). These two changes will help when using Textpad macros, e.g. to pick out the COOR messages out of a 40 MB logfile. Shorten the text of most messages reporting the actions interpreted and executed from COOR commands: - drop the words "COOR Set" - and abreviate e.g. Exposure Group -> Expo Group L2 Reject: Change the programming of the L2 Reject AONMs. They used to form an AND between the L1 Specific Trigger Fired and the Inverse of the L2 Answer. They now just copy (pipe trhough) the L1 Accept Specific Trigger Fired Mask. Change method of implementation of Force_L2Reject to make it compatible with running with L2 Global Answers. We no longer change (by clearing a bit) the simulated Pattern A in the L2 Answer receiving TRM, but we now use the L2 Accept AONM card to block (Mute) all positive L2 Accept decisions. Note that for all unused Specific Triggers both the L2 Accept and L2 Reject AONMs are programmed to force their output low (Mute). SCL Init: Reset the L2 Answer TRMs FIFOs during SCL Init. cf. www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/scl_initialization_steps.txt This is done using the Force Scaler Reset Register. All other L2 TRM cards were already reset, but the L2 Answer TRMs were not. Monitoring Data: Fill the Monitoring Information regarding the programming of Geographic Sections (And-Or Terms and GeoSect) and Sped Trig (And-Or Term and L1 Qualifier), as well as L2 Data Path. The space was already reserved. Fill the Monitoring Information flag to report the L2 Global Obey/Ignore Mode. The space was already reserved, the flag was constantly on. Take into account the Transposed order of the TRM Fpgas to fill in the Global Disable Scalers in the Monitoring Information. The symptom was that we were displaying the Decorrelated Disable a second time in place of the Correlated Disable. Fix the typo that was returning the L2 BAD Busy Delay a second time in place of the count of L2 Busys Cycles. COOR Command Parsing: Include an update necessary for L2 Relay Software message parsing: the pound character '#' is the comment flag, and the rest of the command is ignored. New Register Dump Sub-Sub-Dialog: The Register Dump Dialog is accessed via the "Dump..." button at the bottom of the the "Register IO" menu. This feature dumps TRICS' knowledge about one particular -- or a set of -- registers. The user can choose to dump TRICS' register information about - one Register - one FPGA - one Card - the L1FW - the L2FW The following information is presented: - The mother card descriptive name as known to Trics - The card, and/or Fpga Base address - Each Register's Read and Write Bit Mask identifying existing bits - Each Register's last Read and Write IO operation - Each Register's current content e.g. Reg# 2 @0x10020004 IOMask:R=0x1fff/W=0x037f Prev:R=0x007c/W=0x007c Now: 124 The register coordinates are entered via the dialog box, like for the "Register IO" menu. The register dump information is displayed on the dialog box and to the console screen. The dump information can INSTEAD be sent to a Result File (especially useful when dumping a whole card or the whole FW). The result file is automatically named, created and opened following the template: \trics\d0_log\REG_DUMP_Vvv_w_r_yyyymmdd.dmp;n The user may choose to skip read-only registers. L2 Unbiased Sample control programming: The syntax is "L1FW_Spec_Trig [S-S] L2_Unbiased_Sample [R]" cf. http://www.pa.msu.edu/hep/d0/ftp/tcc/coor/coor_to_tcc_l1fw_message_syntax.txt A template is available in the "Send COOR Message" menu. To program a new Unbiased sample N Trics takes the following steps - pick a random number P between 1 and N. - write to the 32 bit Mark and Force Pass Control Reg (reg 72:73) the value P-1 along with the Asynchronous Reset control bit. - clear the Asynchronous Reset bit (leaving the value P-1) - write the value N-1 (without the Asynchronous Reset bit) The default programming for un-allocated SpTrg is to write the maximum value (0x00ffffff) and the Asynchronous reset bit. How this circuitry works is not 100% clear, but this method hopefully keeps the count-down scaler at a non-zero value. Ignore/Obey the L2 Global Answer: The syntax is "L2_Global_Obeyed" "L2_Global_Ignored" A template is available in the "Send COOR Message" menu. The default after initialization is to be in the L2_Global_Ignored mode. TRICS takes the following three steps to switch to the L2_Global_Obeyed (respectively L2_Global_Ignored) mode - clear the Bypass mode bit of the L2 Helper State Engine Control Reg (respectively set the bit) - switch the L2 Answer TRMs to Normal FIFO Mode (respectively to Simu Mode) - execute the master command file \trics\d0_config\L2_Global_Obeyed.mcf (respectively \trics\d0_config\L2_Global_Ignored.mcf) L2 Data Path: The Syntax is "L2_Path_Geo_Sect_List [GG]" A template is available in the "Send COOR Message" menu. When receiving this message Trics takes the following steps for all geographic sections and exposure groups, as this may be a message giving us Less (or no) Geo Sect in the L2 Data Path. - rebuild the derived list of all allocated geogrpahic sections - reprogram the lookup of GeoSect Front-End Busy to Expo Group Front-End Busy. Now we include all the GeoSect explicitely in the Exposure Group *AND* all the GeoSects in the L2 Data Path. That's 2 copies times 8 FOM channels. - reprogram all L1 Ouput FOMs and the L2 Reject FOMs so that Geographic Sections in the L2 Data Path receive a L1 Accept or L2 Reject for All allocated Specific Triggers. Geographic Sections NOT in the L2 Data Path receive the normal programming. - The FOM++ (L1 Qualifiers and all other special channels) and the L2 Accept FOMs are left unchanged. That is only the GeoSect explicitely listed in each SpTrg Exposure Group can participate in their output. - update the L2BAD card to include these GeoSects. The (subsequent) programming of Exposure Groups and Specific Triggers also needs to follow the same receipe. Single Chance Test: Update to follow the new usage of L2 Accept/Reject AONM cards where the L2 Reject AONM card switches from Mute Ouput to Pass thru the L1 Fired and the L2 Accept switches from Mute Ouput to forming the L2 Accept Decision. Trigger Tower Info Files (.TTI) Add support for Sin(Phi) and Cos(Phi) function in slope of Momemtum Lookup PROMs. Method: add an alternate way to specify the Transfer_Slope coefficient by specifying a math function instead of explicit values of each Tower coefficient. Add new Keyword "Transfer_Math:" which can only take a value 0 or 1 0= |Sin(Phi)| 1= |Cos(Phi)| with Phi derived from the TT_Phi Index [1..32] as Phi = (2xPi) x (TT_Phi - 0.5) / 32 The "Transfer_Slope:" and "Transfer_Math:" are mutually exclusive, meaning that they override each other. Specifying a "Transfer_Math:" value will override any previously defined "Transfer_Slope:" value, and vice versa. cf. syntax_rules_trgtwr_info.tti in http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/ Add a warning message when a page is being re-defined. TrgTwr PROM Lookup Dialog: Add/Implement a button to generate one binary PROM file. The file name follows the template: \trics\d0_log\xxseeppva_yyyymmdd_Vvv_v_r.BIN;n with PROM identification information ------------------------------- xx = "EM", "HD", "PX" or "PY" s = "N" for negative eta = "P" for positive eta ee = "01" to "20" is the Trigger Tower Eta Index (note that some of eta 17-20 may receive signals that do not correspond to their "natural" eta value). pp = "01" to "32" is the Trigger Tower Phi Index a = PROM Version Number The first set of prom will be Rev "A" .BIN = File extension for raw binary file File Creation Date ------------------ yyyy = year [2002,2003,...] mm = month [01..12] dd = day [01..31] ;n = file version number default is ";1", but can be a higher number if several files would have the same name Trics Version Identification ---------------------------- vv_v = Trics Major & Minor version number [10.0,10.1,..,11.0,...] r = Trics Revision Number [A..Z] A copy of the final/official/archived set of file will be made with all names truncated (externally, by hand) down to "XXSEEPPV.BIN" for usage in the PROM programmer using legacy DOS 8+3 file name format. e.g. PXN0101A_20020401_V10_0_E.BIN;1 -> PXN0101A.BIN Add/Implement a button to generate All PROM files. This includes generating a checksum file \trics\d0_log\PROM_CheckSum_yyyymmdd_Vvv_v_r.BIN;n This includes checking that all pages of all generated PROM files have been prefiously defined. Internal: New function to ADD requirements to an AONM or FOM pre-programming. This is how we can program the regular Exposure Group Front-End Busy requirements and then ADD the L2_Data_Path requirements. Add a function to pre-programm one AONM/FOM output Low. This is how we can program the L2 Accept AONM to force_reject Update RegBase, FpgaBase, and CardBase. Many small fixes and upgrades to make the chain of registers, fpgas, and cards fully operational for the new register dump feature. Especially in the manner some non-existing registers are deleted, or some default FPGAs types are replaced with other species (Miguel, Shed, L1AL2,..) Modify AONM/FOM common low level programming code to support new functionality needed for L2_Data_Path and Force_L2Reject. Move the f_okDoForceFifoCounterReset function out of the common FpgaTRM and CardTRM code into the L2fwCardTRM code, as this method is specific to the L2 TRM. For the L1 TRM one forces the counter to trip and reset itself, while the L2 TRM needs an explicit reset via the computer controled scaler reset register. Upgrade HandleResultFile.cpp to handle binary files. This requires an additional parameter flag to open the file ('b') otherwise the default is the text ('t' aka "translated") mode which adds some unwanted line control characters. Also added a method WriteBinary to write an array of characters of given length to the already open file. The rest of the methods works unchanged to write binary files. -------------------------------------------------------------------------------- TRICS II Version 9.5 Release Notes ------------------------- 7-Dec-2001: (Rev B) Exposure Group Per Bunch Scaler Un-comment the definition of the expo group #3 upper PBS (slot 14). This scaler card was found sick when first installed in June 2000. Trics had been left skipping this card ever since. SCL Hub End: Remove the kludge that was skipping Trigger Status Concentrator #2, 9, 11. These modules were previously skipped because their registers were not answering VME bus cycles. The bad modules have been replaced, and the missing module was installed. L2 Hardware Scalers: Added 6 SM modules to implement the L2 Hardware Scalers. The L2 Hardware Scaler SM Card #0 (1,..5) is in slot 8 (9,..12) of M123-Bottom. These scalers are served by TCC's Monitoring server as a one-dimensional array of 6*64 scalers with the relative scaler #0 of the Fpga at site #1 (i.e. the first Main Signal Array Fpga) of the SM card #0 (i.e. slot #8). The fpga relative scaler number increments the fastest, and the card number increments the slowest. Note that this one-dimensional array definition [overal_scaler_num] in C is equivalent to a 3-dimenstional array [card_num][fpga_num][scaler_num]. cf. l1_tcc_monit_data_l2hardscalers.hpp in http://www.pa.msu.edu/hep/d0/ftp/tcc/monitoring/ Initialize: Initialize to zero the tick-and-turn scaler tick-select registers. Note that only the tick-select feature of FPGA #16 (the one keeping track of the Bean X processed by the L1FW) are connected to andor Terms. Note that two of these tick-select registers are programmed to a useful value by the init_auxi RIO file. Each L2 Hardware Scaler GS FPGA is initialized so that its relative scaler #n (n=0..3) listens only to the FPGA's private gate #n. Private gate #4 and #5 are thus left unused on each FPGA. To the L2 Helper Fpga class add the Global L2FW Scalers and reset all these scalers during initialize. Add the Mark and Force Pass Scaler to the TDM Fpga and force it in reset (and leave it that way) during Initialize. Nothing else talks to these scalers, still not used, but which will eventually drive one of the L1 Qualifiers. Time Zone Spread: Add a global variable to the L1FW class to remember the current Time Zone Spread. This CL1fw::mg_ubTimeZoneSpread variable is initialized with the constant KiTimeZoneSpreadTotTick (currently 35). This Time Zone Spread is used to initialize the exposure group PBS, specifically to line up each tick select, so that the accelerator bunches appear in their conventional places. This mechanism replaces the hardcoded initialization constants KiPbsExpGroupBaseTickSelectLower/Upper (which was off). CL1fw::mg_ubTimeZoneSpread can be changed with a new COOR-like command "TrgMgr_Time_Zone_Spread ". This command need only be executed once (not once per initialize). Moreover sending the command during initialize would get it executed only after the end of the initialize sequence and thus too late to influence the initialization of the PBS scalers for this initialize. Next Revision: add step BOOT_AUXI.MCF The next revision of Trics should add the new concept of a BOOT_AUXI file to be executed only once when TRICS starts up. Things to go in such a file: - The definition of this Time Zone Spread to setup Expo Group PBS - The tick alignement setup of the Foreign PBS (after adapting the meaning of the existing message from "do it now" to "remember how to do it during initialize") - Global L1CT included/excluded switch. - Coverage of L1CT currently instrumented. - Load a file of Trigger Tower Gain Control values - Load a file of Trigger Tower Pedestal Control values - Load a file of Trigger Tower PROM lookup coefficients Luminosity Server Luminosity server quits serving the per bunch scaler block that was used for an initial test (pull only) but is not used any more. Monitoring Server Upgrade: cf. new doc file 000_l1tcc_monitoring_server.txt in http://www.pa.msu.edu/hep/d0/ftp/tcc/monitoring/ The old file Tcc_Monit_Data.hpp that was describing all the simple Monitoring and Luminosity data was getting out of control. This old file has been replaced with a hierchical structure of many smaller files. All these definition files are available in http://www.pa.msu.edu/hep/d0/ftp/tcc/monitoring/ An official CVS D0 product will be created, called "trigmon", to hold all these header files which are referenced by the DAQ_monitor, and the Luminosity Server. We will eventually add the trigmon application, if people are interested. cf. http://www-d0.fnal.gov/cgi-bin/cvsweb.cgi/trigmon/ The top files which define monitoring block structures are: - The DAQ Monitor program only needs to include the top file L1_Tcc_Monitoring_Data.hpp. To pick up the definition of the block type currently used by the DAQ_MONITOR program, the calling code needs to define the pre-processor constant "TCC_SUPPORT_PHASE3_MONIT_DATA". No new application should use this legacy data, which has been replaced with new blocks with more information. These "obsolete" block types will eventually be abandonned. - The Luminosity Server program only needs to include the top file L1_Tcc_Luminosity_Data.hpp. There has been no change in data definition, just a change in organization of the header files. - Trics and our specialized monitoring programs would additionally include the following definitions, as needed. These are not considered to be of interested outside our group. - L1_Tcc_Monit_Data_CalTrig.hpp this one will eventually be included in L1_Tcc_Monitoring_Data.hpp when it is ready for prime time, (This is not new, while some information has been added to it and programs using this block need to be re-compiled) - L1_Tcc_Monit_Data_Hsro.hpp this is a snapshot of readout data catpured in the monitoring register and rebuilt into a structure identical to what we send to the VRB and read out of the VBD, (This is not new) - L1_Tcc_Monit_Data_Card_Info.hpp this is a block of information about each of our cards, e.g. FPGA revision, VME Interface Status, etc. (This is new) This file defines the request expected by TCC on its Monitoring Server Port. - L1_Tcc_Monit_Data_Request.hpp Definition of the structure to send to TCC's monitoring server to request a monitoring block of a particular type. There are a number of intermediate level definition files: - L1_Tcc_Monit_Data_Frameworks.hpp Definition of the structures holding information about the L1&L2 Frameworks. (There is a "Brief" and a "Full" version of this structure) - L1_Tcc_Monit_Data_CalTrig.hpp (already listed as a top file above, but eventually becoming and intermediate level file) - L1_Tcc_Monit_Data_L2HardScalers.hpp Definition of the structure holding information about the "L2 Hardware Scalers". - L1_Tcc_Monit_Data_Obsolete.hpp Collection of all the legacy (i.e. "obsolete") blocks that will eventually be dropped - Tcc_Block_L1fw_General - Tcc_Block_Per_Bunch_Scaler These files are the lower level building blocks: - L1_Tcc_Monit_Data_Header.hpp Definition of the Header which always comes first and includes a code that the client can use to recognize the block type on the fly (There is a single "new" and an "obsolete" version of this structure) - L1_Tcc_Monit_Data_BeamX.hpp Definition of the sturucture holding the various Beam Crossing and Tick and Turn Scalers qualifying L1 FW data and L2FW data. (There is a "new" expanded version of this structure while the old short version is still used) - L1_Tcc_Monit_Data_PerBunch.hpp Definition of the structure for one per bunch scaler. (There is only a single unchanged version of this structure) - L1_Tcc_Monit_Data_LumBlockNum.hpp Definition of the structure for information related to the Luminosity Block Number. (There is only a single "new" version of this structure) - L1_Tcc_Monit_Data_FwGlobal.hpp Definition of the structure holding L1&L2 Framework-wide global information. (There is a "Brief" and a "Full" and an "obsolete" version of this structure) - L1_Tcc_Monit_Data_AoTerm.hpp Definition of the structure for one Andor Term. (There is a single "new" and an "obsolete" version of this structure) - L1_Tcc_Monit_Data_SpTrg.hpp Definition of the structure for one Specific Trigger. (There is a "Brief" and a "Full" and an "obsolete" version of this structure) - L1_Tcc_Monit_Data_ExpGrp.hpp Definition of the structure for one Exposure Group. (There is a "Brief" and a "Full" and an "obsolete" version of this structure) - L1_Tcc_Monit_Data_GeoSect.hpp Definition of the structure for one Geographic Section. (There is a single "new" and an "obsolete" version of this structure) This defines the 8, 16, 32, 64 bit data types for different platforms - L1_Tcc_Monit_Data_BasicTypes.hpp Definition of the basic data types used in the above structures. Monitoring Information newly defined but not yet filled: Keeping track of an upper longword to serve up 64 bits scaler is not done yet. The monit data block that collects all the card info is not being filled at all (only the header type information). In the new Global Framework-wide information (Brief and Full) the following items are not yet filled: - Tot number of Specific Trigggers currently allocated - Tot number of Exposure Groups currently allocated - Tot number of GEographic Sections currently allocated - The list of Geographic Sections needed for L2 Data Path (Full block only) (this concept has not yet been implemented in Trics) - The time since last COOR Initialize - The time since last FPGA Configure In the Specific Trigger Section (Brief and Full) the following items are not yet filled: - The additional mask of programming info (including the sptrg "force_reject" flag) - The Andor Requirement of the Spec Trig (Full block only) In the Exposure Group Section (Brief and Full) the following items are not yet filled: - The Andor Requirement of the expo group (Full block only) - The set of Geo Section digitized by the Expo group (Full block only) - The Expo Group Andor Fired Scaler (we do not have such a scaler yet) In the Andor Term Section (Brief and Full) the following items are not yet filled: - The Andor Synchronization error count (Trics does not yet look for and count these errors) In the Geographic Sector Section (Brief and Full) the following items are not yet filled: - The latest status mask (from the Hub End status concentrator cards) - L1 and L2 Error Counts (Trics does not yet count these errors) Internal: Add the Scalers to the L2 Helper Fpga and reset them during initialize. Add the Mark and Force Pass Scaler to the TDM Fpga and force it in reset during Initialize Single Chance Test now uses the Time Zone Spread as an initial value for the test. This value can still be overridden via the corresponding edit box. Made the Fifo Depth analysis a generic property by creating a new register class called RegFifoStatus. This class has member functions to collect a histogram of a specified sample size, locate the maximum value, and build an ascii representation. the "Input TRM FIFO Depth" submenu with its Dlg_Test_Trm_Fifo_Depth class now uses this method to probe the andor term fifo depth. modify the TRM, and Tick and Turn FPGA classes to use the new RegFifoStatus register classes for their m_poFifoStatusMonitor register. In the class FpgaGS, add a member function f_okAddIndividualGate to add a given private gate to a given scaler. Rename the constant KiTotForeignExpGrp (weird name) to KiL1fwTotExpoGroup add the file names behind the buttons in the "Master Command Files" sub-dialog to ListOfMasterCommandFiles.h and further annotate this file. Add a number of constants to MonitControl.h indepently set the number of samples per fifo depth histogram for each of our TRMs and TTS. #define KiMonit_AOIT_FifoDepth_SampSiz 5 // to monitor the Andor Input Term Fifo Depth #define KiMonit_TTS_FifoDepth_SampSiz 5 // to monitor the TTN Scaler Fifo Depth #define KiMonit_L1Fired_FifoDepth_SampSiz 5 // to monitor the L2FW L1 Fired Fifo Depth #define KiMonit_AuxL1Data_FifoDepth_SampSiz 5 // to monitor the L2FW L1 Auxiliary Data Fifo Depth #define KiMonit_L2Answer_FifoDepth_SampSiz 5 // to monitor the L2FW L2 Decision Fifo Depth To implement the new monitoring blocks (whose contents overlap between Brief and Full version and with legacy block types) without reading the same data many time, the organization of the collection of all this information has been adapted. We do the substructure common to more than one block first, e.g. the beam Crossing and Tick and Turn structure, then we copy this data to the other blocks. We also fill similar blocks together, e.g. the Spec Trig Struct Brief and Full as well as the legacy phase 3 structure. Separate Programs: All Toy Monitoring programs have been updated to use the new definition of the monitoring structures. Most of it is cosmetic, as the same old information is being received and displayed, with one exception: The only actual change is in the Cal Trig Monitoring data which has more information being served, while the toy cal trig monitoring only displays the same old Trigger Tower information. A new version of this toy monitoring program has been installed a t DZero. The set of Toy Trigmon programs are not going to be developped much further, as we are now switching to a new Run II Trigmon engine that will be much more convenient to maintain and make grow. Trigmon_II V0.3 is already functional: This is the NEW trigmon engine but displaying the OLD monitoring data block type, i.e. the same stuff toy_trigmon and daq_monitor are displaying now. The data in the top/header part of the display is pretty much all fake except for the "triggered" flag, the COOR pause percentage, and the tick and turn number. There is a new shortcut "_TrigMon_II_" on the TCC's screen. Type "F", "G", or "A" to switch between the different display pages, to ask for a new sample. This is already an improvement over toy trigmon, but we will get the real benefit from the upgraded monitoring services when we switch trigmon_II to request and display the new monitoring block types. -------------------------------------------------------------------------------- TRICS II Version 9.4 Release Notes ------------------------- V9.4 was never run at DZero ------------------------- 07-Oct-2001: (Rev A) Exclude Trigger Tower: Implement the COOR Message to Exclude Trigger Tower COOR Message cf. //www.pa.msu.edu/hep/d0/ftp/tcc/coor/coor_to_tcc_l1ct_message_syntax.txt e.g. L1CT_Exclude EM_Tower TT_Eta(20) TT_Phi(23) L1CT_Exclude HD_Tower TT_Eta(20) TT_Phi(1:32) Summary of actions to exclude one trigger tower at the CTFE level: - save a copy of the mask of which of the 8 EM/HD TT are currently updated with the ADC clock (FA 81) - select just the targeted TT for updating (FA 81) - Write 8 to the Test Data Register (FA 82) - Set the Board Control Register to Simulation Mode (128 at FA 80): since the ADC clock is running at 132 or 396 ns, the value 8 gets immediately loaded in this trigger tower's ADC/Simu mux/latch. - restore the mask of Trigger Towers being updated to its original setting but with the bit controlling the targeted tower now cleared (FA 81) - restore the Board Control Register to its original value (FA 80) Pedestal Control DAC and Gain Control DAC: The Trigger Tower Info (.TTI) file syntax has also been extended to ingest information describing the Trigger Energy Tower Gain Control Programming. cf. www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/syntax_rules_trgtwr_info.tti The keyword "Dac_Value:" has been changed to a more explicit name "Pedestal_Control_DAC:". "Dac_Value:" has been kept as an alias for backwards compatibility, but new files created by "Find_DAC" will use the new keyword. There is a new keyword "Gain_Control_DAC:" to register new Gain Control DAC values for the new Terminator-Attenuator mezzanine cards. Note that the "CTFE DAC Programming" sub-menu can be used to debug individual new-style terminator-attenuator boards, but that Trics currently still expects all L1CT cards to have the old-style front-end electronics. Note that the "Pedestal_Control_DAC" keyword will still cause immediate programming of the old-style DAC resources. Recollect that the current usage is to let "Initialize" load default value in the pedestal DAC registers and that we use L1CT_post_auxi_init to execute a TTI file (generated by FIND_DAC) to overwrite these values. Note that the new "Gain_Control_DAC:" keyword will have no effect for now. Note that the intended future usage of these TTI keywords will be to only register these values with Trics and that the "Initialize" procedure will load both the Pedestal Control Values and the Gain Control Values into the serial DACs. We will use a pre_init_auxi file to execute a TTI file during every "Initialize" or some new kind of "boot_auxi" file to execute only once. The sub-menu "CTFE DAC Programming" now has a button to convert a CTFE card address to a Trigger Tower Coordinate and verify that the proposed CTFE address is valid. Note that when we switch to officially using the terminator-attenuator boards in L1CT, the situation will be reversed, and the user will enter the trigger tower coordinates and will be able to translate to CTFE coordinates. Trics will also then have a button(s) to retrieve the registered Pedestal and Gain Control DAC values from what was specified via the TTI file(s). PROM Programming definition and simulation: The Trigger Tower Info (.TTI) file syntax has been extended to ingest information describing the Trigger Energy Tower Lookup PROM programming. cf. www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/syntax_rules_trgtwr_info.tti Note that this same syntax is used for both PROM programming and Trigger Tower DAC pedestal control (cf. below). This information can be used to describe the transfer function of all 8 lookup pages of each EM, HD, PX and Py lookup PROM of each of the 1280 Trigger Towers. This description can then be used to (1) simulate the PROMs (e.g. in a future L1CT single chance test), (2) verify the content of individual Lookup PROMs (3) generate files in an apropriate format to use in a prom programmer. These 3 functions are not yet available. Ingesting PROM description files is implemented, and PROM lookup can already be simulated (while there are still some questions about the meaning of Low Energy Cut). Trics uses sanity-check constants to limit the allowed values of Prom coefficients in TTI files. These values may need to be adjusted when we understand what we really want. This is to protect ourselves against operator errors. KfMaxPromSlope 1.0 //max Lookup PROM Slope (typ=1 or sin/cos(phi)) KfMaxPromLowEngCut 4.0 //max Lookup Low Energy Cut (typ=0.. 2.0 GeV) KiMaxPromZeroEng 8 //max Lookup Zero Energy Response (typ=0 or 8) There is a new sub-dialog "TrgTwr PROM Lookup" available from the main Trics dialog box. The user can use this submenu to load a new TTI file into Trics, if there isn't one already. The user then selects a particular Trigger Tower coordinates (eta sign, eta magnitude, phi), a particular PROM type (EM, HD, Px, Py) and a particular Prom Page (0..7). The user can view the coefficients currently registered for this prom page with the button "Show Current Coeffs". The user can change these coefficients on screen and ask Trics to overwrite the registered coefficients with the button "Set Coeffs Current". Manually entering coefficients is not (yet?) restricted to the above limits. After selecting a PROM page, the user can use "Simulate PROM Page for this TT" to simulate the PROM response by entering a PROM input value in the "In" edit field. The read-only "Out" edit field is automatically updated. After selecting a PROM Page, the user can use the "Show Ascii Dump" button to print to the console window an ASCII dump of the whole selected PROM page. After selecting a PROM page, the user can use the "Check PROM" button to ask Trics to check in situ the content (all pages) of the PROM for this L1CT Trigger Tower. This is not yet implemented. This checking will be disruptive of normal L1CT operations as Trics will need to set this Trigger Tower in simulation mode in order to send controlled values to the PROM input. Reading the PROM output will need to happen on the following CAT2 card after CTFE summation of the 4 TT on the card. Trics will thus need to put all the towers on that CTFE in simulation mode. After selecting a PROM, the user can use the "Generate Programmer File" button to create a file suitable for the PROM programmer to burn the selected PROM (all pages). This is not yet implemented as there is no final decision on what programmer and what file format will be useful. All Command Files: In order to allow floating point values for TTI command files (e.g. for momentum prom slopes) the command files now accept floating point values. The parser will properly convert fields with decimal points, and/or exponent values. No space must be present between the mantissa and the exponent. The exponent must use the "e" or "E" notation (and not the "d" of the C syntax for the double type) Keywords that expect a floating point value may be entered in many different ways (some of them useful), e.g. Transfer_Slope: 1 !these are all equivalent representations Transfer_Slope: 0x1 Transfer_Slope: 0b1 Transfer_Slope: 1. Transfer_Slope: 1e0 Transfer_Slope: 1E0 Transfer_Slope: 1.e0 Transfer_Slope: 1.0e0 Transfer_Slope: .1e1 Transfer_Slope: 0.1e1 Transfer_Slope: 0.1e+1 Transfer_Slope: 10e-1 Transfer_Slope: 10.e-1 Transfer_Slope: 10.0e-1 Keywords that expect an integer value can also be entered in many different ways (however probably never very useful), e.g. Zero_Energy_Count: 8 !these are all equivalent representations Zero_Energy_Count: 8. !i.e. integers can be entered as floats Zero_Energy_Count: 8.9 !but the floating point value will be truncated Zero_Energy_Count: 0.8e1 Zero_Energy_Count: 80e-1 Sending Mail Messages: The goal is for TCC to send us a mail message when it detects a failure during an Initialization sequence. The method chosen is for TCC to write a "Result File" with the command success status and use an external utility that will notice the file has been created or updated and automatically mail us the file. An application that seems to do what we need is BEEE http://www.iopus.com/beee.htm and I nave been using it for some weeks at MSU with total success. Create a new directory \Trics\D0_Log\ToMail. Any new file appearing or updated in this directory will automatically be mailed out to us. The file is mailed as a text attachment with a subject line saying something like "TCC Status Report" plus the file name. The original goal was expanded a little bit. Trics will be creating/sending a file at EVERY Initialize message from COOR. We can scale it back in the future if necessary. Initialization from COOR has been happening less than once a day and the multiple occurence of Initialization may already show a sign of trouble. The File content will clearly show Success or Failure and where the eventual failure happened (L1FW, L1CT, SCL, or LBN). This file name is \Trics\D0_Log\ToMail\Status_At_Last_Init.log. Trics will also be sending us a file at system configuration time (=FPGA download) where the message will include how many FPGAs were configured and how many Errors there was. This file name is \Trics\D0_Log\ToMail\Status_At_Last_Config.log. Trics will also send us a file when the Monitoring Data Manager thread declares the system Non-Operational after detecting too many successive failures trying to force a Monit Data Capture. This file name is \Trics\D0_Log\ToMail\Status_Non_Operational.log. Splitting LogFiles: The motivation was to control the size of the Logfiles created by Trics without having to stop/restart the application. This will make the logfiles easier to handle and easier to archive. There is a new "Start a New Logfile" Button in the "System Control/Status" sub-menu to make Trics stop writing to its current logfile and start a new logfile. The new logfile will use the current date in its file name, and may thus have a different name than the original logfile (and not just a different VMS-style version number). Trics will remember and write the name of the orginal Logfile at the beginning of the new logfile. Trics will also write the name of the Logfile continuing (preceding) the current Logfile at the end (beginnin) of each Logfile segment. New Environment Variables: Add %LOG% to point to \Trics\D0_Log (\Trics\MSU_Log at MSU) and use this to create the logfile (this was previously hardcoded). Add %MAIL% to point to \Trics\D0_Log\ToMail (\Trics\MSU_Log\ToMail at MSU) Internal: Add a global variable to CommandFileDownloadFpga.cpp to hold the status string of the last download operation. This string specifies the total number of FPGA downloaded and the toal number of errors. It is then retrieved after the "configure" command has called the master command file. This string is writen to the status file that will be mailed out. The Result File Names (and the LBN file name) are specified in a new header file called ListOfResultFiles.h To help in the management of the many source code files: L1FW_MasterCommandFiles.h has been renamed ListOfMasterCommandFiles.h EnvironmentVariables.h has been renamed ListOfEnvironmentVariables.h IP_PortNumbers.h has been renamed ListOfIPPortNumbers.h L1ctCardAddresses.h has been renamed ListOfL1ctCardAddresses.h L1fwCardAddresses.h has been renamed ListOfL1fwCardAddresses.h L2fwCardAddresses.h has been renamed ListOfL2fwCardAddresses.h SclAddresses.h has been renamed ListOfSclAddresses.h In HandleLogFile.cpp use the %LOG% environment variable to create the logfile path intead of hardcoded reference to \Trics\D0_Log. In UtilsFile.cpp split the environment variable translation functionality out of the FileLocate function to a new function SubstituteEnvVar. Upgrade/fix the ResultFile constructor to allow usage of environment variables (it was only working if a file with same name was already existing). Also add a new CResultFile::ReadyForWrite() member function to be able to test the availibilty of the File before calling WriteLine(). Drop the old style prescaler suport (64 bit circular shift with 24 bit after burner). There was a pre-processor switch to pick between old and new style prescaler. Only the code for new style prescaler is left now. This has no impact on what code gets compiled for the prescaler. The L1ct class now has an array of pointers to 1280 Trigger Tower Objects. -------------------------------------------------------------------------------- TRICS II Version 9.3 Release Notes ------------------------- 13-Sep-2001: (Rev A) General Layout: The main entry dialog box now starts out in the upper right corner of the monitor screen (instead of the center). Trics takes ownership of SCL Hub End Crate: New actions during main Initialize: Now initialize all resources of the Hub Controller and the Status Concentrators of the Hub End Crate during the main initialization sequence. cf. Trics_II_Initialization.txt and Hub_End_Initialization_Steps.txt in http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/ Note that Trics currently skips all VME IO to TSC# 2, 8, 11. SCL Initialize: Now display the status of all GeoSect currently allocated by COOR before (e.g. who claimed L1 Error) and after (e.g. who didn't get out of Init Ack) the SCL_Init command is sent. cf. scl_initialization_steps.txt in http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/ Note that Trics currently skips all VME IO to TSC# 2, 8, 11. New "SCL Hub End Crate" Sub Menu: This is a new sub menu to interact with the SCL Hub End Crate. The upper part of the Dialog interacts with the Trigger Hub Controller: The "Read THC Status" button reads the THC status register and displays its content bit by bit using check boxes. The only box and the only bit that the user can interract with is the "7MHz Enable" control. This bit controls whether the THC will listen to the DAQ commands from the L1FW. Clicking on this box will generate a VME write to the proper Set or Reset register of the THC to flip the state of this bit to ON or OFF, and Trics will also re-read and re-display the register content for verification. Clicking on any other check box of the THC display is ignored and has no effect. The middle part of the Dialog interacts with the Trigger Status Concentrators Cards, one channel (i.e. one GeoSect) at a time, with the user entering the desired GeoSect Number in an Edit Box (the default is GS #31, i.e. the L1FW): The "Read Status" button reads the Status Register for the specified Geo Sect Number. The content of the register is displayed bit by bit with its associated meaning. This is a read only register and the user cannot change its content; Clicking on any of the Channel Status check boxes is ignored and has no effect. The "Read Int Mask" button reads the Interrupt Mask Register for the specified Geo Sect AND reads the corresponding TSC Board Level Status Register. The content of the Int Mask register is displayed bit by bit with its associated meaning. The LSB of the content of the board level status register is displayed right underneath the Interrupt mask register, and is labelled for its meaning: Board Level Interrupt Enable. Clicking on any one of the check boxes for the Interrupt Mask Register will make Trics do a VME Write Cycle to invert (turn ON or OFF) the state of the corresponding bit (leaving other bits unchanged) and Trics will also re-read and re-display the register content for verification. The Board Level Interrupt Enable Bit can be changed in the same manner. The "Read Int Req" button reads the Interrupt Register for the specified Geo Sect Number. The content of the register is displayed bit by bit with its associated meaning. Clicking on any one of the check boxes for the Interrupt Request Register that is currently displayed as a Bit ON will make Trics do a VME Write Cycle to Reset the state of the corresponding bit (leaving other bits unchanged) and Trics will also re-read and re-display the register content for verification. Clicking on any one of the check boxes for the Interrupt Request Register that is currently displayed as a Bit OFF is ignored and has no effect (as these bits cannot be turned ON with VME cycles). Note that Trics currently skips all VME IO to TSC# 2, 8, 11. The lower part of the Dialog has two buttons: The "Initialize the SCL Hub End Crate" Button will call the part of the full initialization sequence that initializes the Hub End Crate. This is (currently) a benign and stateless action that provides a simple way to look at the status of all Geographic Sections. cf. Hub_End_Initialization_Steps.txt The "Request SCL Init" button sends a message to Trics to generate an SCL Initialization. Add ability to disable sending DAQ commands over SCL: There is a new button in the Single Chance Test sub-menu, to disable the 7MHz clock, cf below. There is a check box in the new "SCL Hub End Crate" sub-menu to enable/disable the 7MHz clock. Calorimeter Trigger Initialization: The Cal Trig Initialization now needs to be successful for Trics to return an "Ok" acknowledgement to COOR (we were ignoring the cal trig init status until now). Note that we have the ability to "Totally Ignore L1CT" in the "System Control/Status" dialog. This would skip the L1 CT Initialization (and associated errors). Master Command File Menu: Drop all special buttons to setup various specific triggers. Only kept the "Configure L1&&L2 Frameworks", "Initialize L1&&L2 Frameworks", "SCL Initialize" and the 3x "UnNamed #" buttons. The file button_mapping_master_command_files.txt in www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/ has been updated Connection to COOR: Increase the maximum size of acknowledgement message to COOR from 256 to 500 char. Find and fix a problem where Trics could become comatose waiting for internal resource locks. The symtoms would be that Trics would ingest the messages but not act on them. This bug was triggered when the system is declared non-operational (after a series of unsuccessful attempts at capturing monitoring data) WHILE an SCL_Init message was being processed at that exact time. This causes the same symptoms as what was observed a few times while the system was turned off, but there is no proof that this was the actual cause. Monitoring Data Server: The Monitoring Server now estimates and displays on the console and in the logfile the L1 Accept Rate integrated over the last 5 sec every time it collects a monitoring data sample. It will display "*****" if the measured increment in beam crossing is negative (e.g. rollover) and will display a positive (or negative in case of problem) rate otherwise. Monit Data -> L1 Accept= 0x00012345 L1 Rate= 10.2 Hz Buf Depth= 0 The monitoring server will now read the L1 Accept and L1AL2 scalers and refresh the LED display on the Per bunch scalers at 10 Hz (while it is not busy pulling the monit data out). This is an attempt to see if this LED display can become more useful if it is updated more often than the 5 second refresh which is nearly useless. Single Chance Test Add a property to the TesterL1fw object to hold the Time Zone Spread between the beam crossing number currently sent to the SCL and the beam crossing being processed by the L1FW. This value is used in the CheckTimeZoneShift routine to verify the Tick and Turn Scalers. The Sub-Menu Dialog has a new Edit box to enter this time zone spread the current default value is 35. There is a new button to disable the 7MHz clock of the SCL Hub End Crate Controller and thus stop sending Trigger commands over SCL. Internal Moved machinery to watch for successive errors requesting monitoring data from L1fwCardL1fwHelper to MonitControl. MonitControl calls the proper routines from L1fwCardL1fwHelper and L2fwCardL2fwHelper and also handles the successive failure machinery to be ready to call the system non-operational during power off. MonitControl has a new ResetFailureDetection routine now called explictely during initialization instead of previously doing the same thing implicitely inside L1fwCardL1fwHelper::Initialize. MonitControl is the high-level handling for RequestMonitData, CheckMonitDataCaptured, and ForceCaptureMonitData. L1fwCardL1fwHelper now calls the same capture monit functions from its helper function fpga with no value added. New SerialCommandLink Object to control Hub End Crate: This is a singleton, meaning there is only one instance of this object in the whole Trics program and all its data members and functions are "static". This object maps bit3 resources to the Trigger Hub Controller address space and the Trigger Status Concentrator Cards. It has member functions to read, set, display the status bits and interrupt masks. It also has an "Initialize" member function to initialize the THC and THC's which is called during main initialization. There is a kludge at the moment to skip reading the registers from TSC #2, #8, and #11 (zero based) as they don't DTACK. -------------------------------------------------------------------------------- TRICS II Version 9.2 Release Notes ------------------------- 9-MAR-2001: (Rev L) General: (Now 80k lines of source code in 336 files). Version 9.2 will include control of the L1 Cal Trig for initial triggering while still using the original Run I CTFE hardware. The Run II serial DAC upgrade is supported for tests (starting with V9.1-F), but not for triggering. Current important limitation: Trics currently doesn't initialize or control any of the Control and Timing signals. In particular the 29525 Read A/B and Write A/B or Latch/Shift signals are not touched. We'll need a separate CBus IO command file to control these signals. Use more Colors on TCC console window: The screen messages received from COOR (or the dialog boxes, command files, etc) are now prefixed with a "M$" and displayed in yellow. This highlights TCC's primary function and helps in following COOR download on the console. The screen messages that correspond to important system events (e.g. L1CT ignored) are now flagged with a "S$" and displayed in purple to highlight transition points. (Note: the total count of Fpga downloaded is now displayed in purple) Calorimeter Trigger: There is a new L1ct object that will include all the L1CT Cards and manipulation functions. This includes the CTFE cards. The idea is to create Card Object for the full coverage, but independently specify the current sign eta, magn eta, and phi coverage in the form of min and max values. Implementa CBusCAT2 class to be able to set correction and comparator registers. Add the Tier#1 EM, HD, Px and Py CAT2 cards to the L1CT Object. These cards are now initialzed cf below. The CHTCR Cards are still not implemented. Add the Tier#2 EM Et and Tot Et RefSet CAT2 cards to the L1CT Object. These cards are now initialzed cf below. Other Tier#2 Cards are still not implemented. Fix the code that reads the 29525 registers. This is a specialized object that saves on VME cycles when reading all 8 time slices. There was a typo that was writing the Function Address to the Card Address port of the Ironics card. This should fix the bad TT_ADC info sent in the monitoring information. New Trigger Tower Info Command File: cf. www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/syntax_rules_trgtwr_info.tti for syntax. This Command File can be called from the Serial DAC menu, but at the moment it only sets up Run I old-style DAC. This Command File lets the user address a given Trigger Tower or a range of Trigger Towers in Eta Magnitude and Phi as well as its EM or HD type. The user can then specify a new DAC value to load into the corresponding CTFE card(s). At the moment the DAC Value is the only available target item, but any other Trigger Tower related quantity can be added. For example PROM slope and low energy cut, and even a list of towers to exclude. The idea is that such a (or several) command files can be called from the Init_Auxi Master Command file, as desired. Master Command Files: Add the ability to call a Trigger Tower Infor File from a Master Command File. The keyword is "Call_TT_Info:" This new keyword will be used from Init_Post_Auxi_L1CT.mcf to call Init_Post_Auxi_L1CT.tti. New Keyword allowed in Master Command Files. "Ignore_L1CT:" to include/exclude L1 Cal Trig: "Ignore_L1CT: 1" ignores L1CT (we can put this line in the PRE-init-auxi). "Ignore_L1CT: 0" includes L1CT (which is still the default). www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/syntax_rules_master_command_files.mcf has been updated. Self Message Command File: No longer wait for message execution when sending COOR messages from a command file (previously waited up to 2 sec), as the command file itself may have been called from a COOR message (e.g. initialize) which means the additional messages generated by the command file are queueud up and wait until the original message is done. Note that there is still a 0.1 second systematic wait when TRICS sends any ITC message. This is a precaution to prevent runaway disaster in case of coding problem. Change the keyword to send messages to TCC's ITC port #52160 (to impersonate COOR or send special TRGMGR messages) from the former "COOR_L1fw_Msg:" (mis-named because too specific) to now be "Send_Msg_To_Self:". The former keyword is still accepted, as an alias, but new command files should use the new, more sensible, keyword. The keyword to call a "Send Message Command File" (.msg) from a "Master Command File" (.mcf) hasn't changed ("Call_Self_Msg:"). CBus IO Command Files: Fix the CBUS IO command file handling routine so that it (as advertized) only does a write cycle for the "Write_Value" keyword, and only does read back and verify for the "Write_Verify" keyword. CBUS IO: Deselect the Mother Board Address (i.e. select MBA=0) upon exiting all CBUS IO Cycles. This is a precaution to prevent glitches to corrupt register programming. more intelligent second CBUS write attempt when first attempt failed. Instead of just writing the data again, now re-send the MBA/CA/FA first. Add a Resource Lock around every CBUS IO to prevent collisions between two threads (e.g. executing a coor message, and the Monit Pool Server). The danger is if one thread starts setting part of a CBUS address, and another thread steals the CPU's attention and start selecting a different CBUS address, when the first thread gets to execute again, it continues its CBus cycle but is now aimed at a different CBUS address. New TrgMgr messages: Added the following COOR-like messages to include/exclude the L1 Cal Trig. "TrgMgr_Ignore_L1CT" "TrgMgr_Include_L1CT" Such messages are however not quite sufficient for the Init_PRE_Auxi master command file because the message will be SENT but NOT EXECUTED until the end of the Initialize command and thus the rest of the Initialize Command will not know of the change in status. It is better to use the new command "Ignore_L1CT: 1" in the Init_PRE_Auxi.mcf instead. Confirm Yes/No Pop-Up Dialog: Change Icon from a question mark to a Guillotine. System Control/Status Dialog: The background is now Red, with Yellow text, with new "gun logo". Change the message showing the user is entering this dialog to an Error message so that it appears in Red to help log file analysis. Add fields to enter a new Trigger Tower Eta/Phi Coverage in the form of a min/max Eta and Phi. The new coverage doesn't take effect untill the user clicks on the button "Set This Coverage". There is an additional and separate control to have NO L1 CalTrig at all. Selecting this option take effect instantly, without needing to use "Set This Coverage". This means that NO more CBUS IO will take place, No L1CT message from COOR will be accepted, and no L1CT Monitoring data will be collected (return zeroes). These controls allow Trics to track along regarding which part of the system is currently available and will only accept commands corresponding to this coverage. As currently planned and implmented this means that Trics will complain if a COOR message or a DAC command file specifies a Trigger Tower outside of this coverage. Trics now wakes up thinking the L1 Cal Trig is available (i.e. NOT ignored) and that the Trigger Tower Coverage is TT_Eta(-4:+4),TT_Phi(1:32). This dialog uses the new "System" messages for most actions, and now generates mostly purple messages. Add a button "Debug" to force an access violation and thus allow jumping in the debugger even if the program was not started from the debugger. This button is protected by an "Are you Sure?" pop-up box. L1 Calorimeter Trigger COOR Message Menu: This is a new sub-menu to provide template messages for L1CT COOR commands. This menu is not directly accessible from the Main Menu, but instead via a new "L1 Cal Trig Messages" button in the existing "Send COOR Message" Menu which handles only the L1 Framework Messages. COOR Commands: The commands for setting EM Et, HD Veto and Tot Et Reference Sets are now operational. Implement the messages to deallocate EM Et, HD Veto, and Tot Et Ref Sets. This means the reference sets are reset to full scale (in fact use 1000 GeV which translates to a count of 255). Suppress all informational messages displaying the Referense Set Thresholds applied to each Trigger Tower (there would be too many). Trics will answer "Bad" to COOR when a reference set is specified that overflows the existing Trigger Tower Coverage. When the TT_Eta or TT_Phi range is omitted in a message from COOR (e.g. a "L1CT_Ref_Set" message) Trics will now use the currently defined Trigger Tower coverage (instead of the maximum eta/phi range). This means that a message like "L1CT_Ref_Set HD_Veto_Ref_Set 0 Value 10.0" will automatically adapt and define the threshold over the whole Trigger Tower coverage currently defined without trying to access non-existing Trigger Towers. Implement the "L1CT_Count_Threshold" message for both the "EM_Et_Towers" and the "TOT_Et_Towers". However, instead of trying to program the normal CAT3 cards in Tier #3, TCC always programs the Tier#2 CAT2 for eta (-4:+4). This is how we are currently running with our limited eta coverage, and the output of the comparators of this card are sent to the L1FW as AndOr Terms. L1CT is initialized during (and at the end of) the main initialize sequence. Note that there is still a control flag to totally ignore the L1CT, available in the "System Control/Status Dialog". Add a "L1CT_Initialize" message that initializes ONLY the Cal Trig. At the moment, "L1FW_Initialize" is in fact synonym to "init" which is the system level initialization. Add a template for this L1CT_Initialize message in the "L1 Cal Trig Messages" sub-menu (which one accesses from within "Send COOR Message" sub-menu). This message also asks for user confirmation ("Are you sure?"). Rename the "pre-auxi" master command file from "Init_Pre_Auxi_L1FW.mcf" to "Init_Pre_Auxi.mcf" as the functionality will be common to both L1FW and L1CT. Note that there is one separate "post-auxi" command file for each of the the L1FW and L1CT. Add a call to a new file "D0_Config\Init_Post_Auxi_L1CT.mcf" at the end of the initialization of L1CT. Note that when the L1CT is flagged to be "ignored" the L1CT is NOT initiliazed, and this auxi file not executed. The whole DAC management business needs to change with the new serial DAC mezzanines, but this is the current model: After power off, one must first run L1CT_Init, then one (or L1CT_Init_Auxi automatically) executes the DAC programming TTI file, and TRICS should thus be able to find the last value it wrote (0x00) in the DAC registers. At the moment the TTI file actually writes the DAC registers, but I picture we eventually want the TTI file to only make these values known to Trics so that it can then load them later during CTFE initialization. The "Initialize" sequence now is: 0) Display and Clear any previous Bit3 Errors, if present. 1) If (0) failed and Trics cannot clear bit3 errors (e.g. power off), declare "bad" status, and jump to (9) 2) Execute the Init_Pre_Auxi Master Command File (currently empty, but could receive "magical IOs" needed to guarantee proper initialization, or high level messages to direct the rest of the initialization, e.g. L1CT eta coverage) 3) If (2) failed, declare "bad" status, and jump to (9) (it is not expected that we would encounter errors during the simple Init_Pre_Auxi commands). 4) Display and Clear any previous Bit3 Errors, if present. 5) Call L1FW_Initialize 5.0) declaring the L1FW "non-operational". 5.1) Init L1FW Cards (If failed, return, i.e. jump to (6) ) 5.2) Display and Clear any previous Bit3 Errors, if present. 5.3) Init L2FW Cards (If failed, return, i.e. jump to (6) ) 5.4) Display and Clear any previous Bit3 Errors, if present. 5.5) Init L1FW VRB Readout Crate Cards (If failed, return, i.e. jump to (6) ) 5.6) Display and Clear any previous Bit3 Errors, if present. 5.7) Init_Post_Auxi_L1FW Master Command File (Initializing the SCL hub-end happens in Init_Post_Auxi_L1FW) (If failed, return, i.e. jump to (6) ) 5.8) Display and Clear any previous Bit3 Errors, if present. 5.9) If everything ok this far, the L1FW is declared "operational". (otherwise no subsequent COOR message can be executed). 6) If (5) failed, declare "bad" status, and jump to (9) 7) Call L1CT_Initialize (which is something that can be called directly) 7.1) if the Cal Trig is currently flagged "ignored" return, i.e. jump to (8) 7.2) Init L1CT Cards for current eta/phi coverage (CTFE, Tier#1, Tier#2 CAT2 cards at the moment) (If failed, return, i.e. jump to (8) ) 7.3) Display and Clear any previous Bit3 Errors, if present. 7.4) Init_Post_Auxi_L1FW Master Command File (note that the eta/phi coverage in any .tti file must match the current eta/phi coverage) (If failed, return, i.e. jump to (8) ) 7.5) Display and Clear any previous Bit3 Errors, if present. 8) Even if (7) failed, do NOT declare "bad" status 9) Write the LBN_At_Last_Init.lbn File 10) If the L1FW has been declared operational call the Increment_LBN message handler which will push a Lum Monit Data Block out the door The last two steps are not necessarily in the logical order, but it makes no functional difference. I knew it would work this way because the Increment LBN step has been the last step until now. I would need more tests to verify that I can reverse the last two steps and I ran out of time for releasing this Revision. The Increment LBN step is acomplished by implicitely calling the Increment_LBN message. I know there is no surprises when it happens last and all the acknowledgement messages get tacked on the way they are supposed to. The down side is that the LBN number written down is the one before the initialize, instead of the first LBN number after the initialize, but the LBN recovery functionality is not being affected. cf. http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/trics_ii_initialization.txt COOR-like command: L1 TCC implements a new message "L1FW_ReSynch_L2TS". Trics will - pause data taking (if needed) - call the master command file \d0_config\L1FW_ReSynch_L2TS.mcf - resume data taking (if needed) This is to help the L2 Test Stand flush its buffers and get ready for a clean event. This master command file currently only waits for one second. The L2RS application that will run on the L2 Test Stand PC will know how to send this message. SCL Initialize: When the system is non-operational and we receive an SCL Init request, TRICS now skips the clean up to the FOM++ and L2 TRM to reset scalers, reset FIFO etc. So now, like for other commands, TCC does not try to use the framework when it is non-operational, and will thus paint less red messages. Note that Trics still executes the Init_SCL.mcf command file (which calls SCL_Initialize.rio that actually causes the SCL_Init via 2x register IOs on the SCL Helper) as a "minimum service". Add an explicit reset of the L2 Helper State Engine during the SCL Init process. The L2 Helper State Engine is forced to (and held in) Reset immediately after pausing the L1 FW. The L2 Helper State Engine is released from Reset after the cleanup of the L2 FW input FIFOes and right before resuming the L1FW. Note: The L2 Global Answer TRM FIFO will also need to be drained when L2 decisions are added to the trigger system. This will be added in the next revision of TRICS. http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/scl_initialization_steps.txt contains a detailed description of the current SCL Initialize steps. Monitoring and Luminosity Services: Added a new Block type to hold an array of DAC values for all 8x time slices of all EM & HD Trigger Towers. Additional information passes the current Eta/Phi coverage. Send the Tick and Turn Scaler from Fpga 14 instead of Fpga 15. This is a change that will affect all Monitoring services, but this is thought to be of benefit to all. The only down side is that the Tick and Turn Number will no longer correspond to "The" TTN that was used over SCL for that event... but there is no connection between Monitoring data and full readout. This Tick and Turn Scaler from FPGA #14 is not reset at SCL_Init time, but is still reset by TCC at Initialization time. The motivation is to avoid sending a time base that gets frequently reset and especially to the Luminosity server which is trying to derive trigger rates and live times. When no data is flowing, TRICS, after waiting 2 seconds and not finding that a data block has been capture, pokes at the L1 Helper Function to cause an immediate capture monit data signal. Poking at the L2 Helper to cause an immediate monit data capture was missing and has now been added. When events are flowing, the L2 Helper listens to one of the L1 Qualifiers coming out of the FIFO through the auxiliary data TRM and will capture monitoring information for the SAME event captured by the L1 Helper. When no events are flowing, the L1 qualifier is never set, and the L2 Helper needs to be explicitely told to capture the monitoring data. Note: the number of beam crossings elapsed between the successive L2 FW data samples will NOT match the number of beam crossings elapsed between the successive L1 FW data samples, but that is nothing new anyway, since the L2 FW data is captured after the corresponding L2 Cycle. There is a separate Beam crossing counter available on the L2 Helper to count the crossings specifically in the L2FW monit data sample context. **BUT** this level of detail is not yet part of monitoring, and L2 scalers are displayed using L1FW beam crossing information. This will introduce some fuzziness probably visible only when trying to show 100.00%. Formatted HSRO Event Dump: Find and fix bug that crashed trics when it tried to display a card name for a VRB channel where no THE-Card was expected. HSRO Test Dialog: Add a selection in the "Readout Crate Test Tool Box" to chose between L1FW readout crate and L1CT crate. This will only affect the Tool Box, and not the Readout Test itself. Trics will not initialize or write to the L1CT Readout crate, except from these toolbox buttons. Note that the "Init VRBs" and "Init VBD" buttons are not available when the L1CT readout crate is selected. This is because Trics does not know how many VRBs are in the L1CT Crate. Trics however expects that this crate has a VBD and VRBC. The "Dump N Longwords from VBD" button is available for both L1FW and L1CT with similar straightforward results for both cases. The "Analyze current event in VBD" button is available for both L1FW and L1CT with slightly different results. The L1FW formatted hasn't changed. The L1CT formatted dump is a modified/simplified dump where the THE-Card data is only merged from the two VRB channel pairs, without further formatting of the typical THE-Card data header and trailer. It will dump up to 100 longwords per L1CT THE-Card, and however many Channel pairs are connected to each VRB, for all VRBs found until it runs out of VRB records in the VBD data. New Find_DAC sub-sub-Dialog: This sub-sub-dialog is accessible from a button "Find_DAC" in the sub-dialog "CTFE DAC Programming". The user can select one or more Trigger Towers (EM/HD, Eta Sign, Eta Magn, and Phi) and let TCC hunt for the DAC Value that will generate the desired Zero Energy Response. The nominal target Z.E.R. is 8 counts, but the user can pick a different value. This version of Find_DAC is only compatible with the Run_I CTFE hardware and does not support the new Run II Serial DAC/ADC front-end upgrade. The user may select to generate a "Result File". This file will be created in the Trics\D0_Log directory and named "Find_DAC_Va_b_x_yyyymmdd.tti;n" where "Va_b_x" is the Trics version number, "yyyymmdd" is the current date and ";n" is a version number so that Find_DAC files are never overwritten by Trics. This Result File is in the form of a TTI file and can be executed as a TTI file from a Master command file. The user may also select the option "...with Details" which will generate additional screen messages showing the histograms of ADC counts as Trics is sweeping towards the optimal DAC Value. These extra messages will appear on the console AND in the result file (as comments). Trics still does not manage the L1CT MTG, or the Timing and Control Signals generated by this MTG. The user must thus ensure that the L1CT MTG is programmed so that the 29525 Read_Pipe_AB and Write_Pipe_AB are identical before trying to run Find_DAC. The algorithm is a straight port of what was done in Run I. - determine a min and max DAC byte for the search, as calculated from the empirical spread in values, with additional safety margin. The search range is 19 to 45 for ZER=8 and the algorithm sweeps up until it decides it found the optimal DAC Value. - The initial histogram sample size is 10 (fast serach), and the algorithm switches to 1000 (deep search) when it detects that the median of the histogram is only one count away from the target ZER. The Function Address being histogrammed is in the range [0,8] which corresponds to the oldest am29525 data. The register may be read while the data is being shifted and some of the samples may thus be corrupted. - every time a new DAC value is programmed, the algorithm waits 0.06 seconds (=3 time const) for the ADC output to settle within 5 %. - Once in deep search mode, the algorithm waits until the histogram shows a decline in the bin population of the target ZER. The algorithm concludes that the optimal DAC value was just overshot. New Dialog to Analyze Input TRM FIFO Depth: Add a new sub-menu "Input TRM FIFO Depth" to analyze Andor Input Term TRM Fifo Depth. This test reads the L1 TRM Fifo Status Register a number of times, extracts the Read and Write Fifo Addresses, derives a corresponding fifo depth, and histograms the result. The output is in the form "n ( a@x b@y c@z )" Where 'n' was the most populated histogram bin, and bin#'x' had a total of 'a' hits, bin #'y' had 'b' hits, etc. All non-empty histogram bins are displayed. The test will abort as soon as one of the samples had its read or write fifo address "reset" bit set. In the matching VME_Access version of this utility the user needs to enter the full TRM FPGA coordinates by hand (don't forget the transposed FPGA order), but the TRICS version finds the TRM FPGA given the AOIT num. The user also selects the sample size (default=100). L2 Busy Answer Delay: Fix a bug in the if-then-else structure during programming of the L2BAD card. Programming the L2BAD is done two places: when COOR specifies a new list of geo sect for an exposure group, and when COOR deallocates an exposure group. In both cases, the programming of all geo sect has to be re-evaluated and all L2BAD channels are reprogrammed, as it is not possible to decide just from the last COOR message which geo sect have been added/removed/still used by some other expo group. Add comments in Card and Fpga code for the L2BAD cards to remind that the programming must be repeated for all 16x FPGAS to allow scaler operation, but that only the output from 1x fpga is used. Create a new constant kiBADTotChanPerCtrlReg (=8) and use it instead of kiBADTotChanCtrlRegPerFpga (=8 also) where we determine which Control Register to use for a particular Channel. There is no change in the machine code generated, but the ascii code now makes more logical sense. Non-recurring Luminosity Block Number: This functionality provides non-repeating, ever increasing, Luminosity Block Number with two components 1) at every initialize from COOR, TCC writes down the current LBN to a file on its local disk. 2) at every software restart, TCC reads back that fairly recent value and adds 10^4 = 7 * 24 * 60 = one week's worth of once per mn increment = or 10k of SCL_Init and start/stop/pause_run - if for some reason Trics can't read this file or value, TCC starts off from 0x00000000 The problem (the file) would have to be fixed and the software restarted. This is accomplished by having a new type of Command file that understands only one keyword: "LBN_Value:". Trics automatically writes such a file at every initialize from COOR. Below is an example. The file name is \Trics\D0_config\LBN_At_Last_Init.lbn. !------------------------------------------------------------------------------ ! Do not delete, rename, or modify this file <%CONFIG%\LBN_At_Last_Init.lbn> ! This File was written by Trics_II_V9_2_D at the last System Initialization ! 20-Apr-2001 14:14:31.947 LBN_Value: 0x0000d0d0 !------------------------------------------------------------------------------ The first LBN issued this way was 0x0000d0d0 at 20-Apr-2001 14:14. This file cannot be executed by any other mean than restarting Trics (at the moment, or until we can find a reason to think we need otherwise). There is thus no syntax description document needed for this command file type. (But we still need better documentation of the overall Luminosity Services). The definition of some of the lum block variables has also been updated per Michael Begel's request. cf. http://www.pa.msu.edu/hep/d0/ftp/tcc/monitoring/tcc_monit_data.hpp - The Luminosity Block information has new fields to hold a Run Number (only filled for the LBN data sent after a start/stop/pause/resume_run message from COOR) and a Spec Trig Mask (only filled for LBN sent after a start_run message from COOR). - L1 Errors, L2 Errors, and L1 Event Dumped are now per Expo Group. Note: these are still not scheduled to be implemented yet. - The blocks will now be flagged as "Phase 5" (which is value=4). - also fix the comments that were reversed for uqDeCorrDaqEnable and uqCorrDaqEnable in struct Tcc_L1fw_Specific_Trigger The upgrade to provide the run number and mask of Spec Trig with the LBN data required propagating these new arguments through the many layers of function calls, in many places. Also updates for better control of the Luminosity data when Trics first starts up, or when Trics is told to skip IO and send blank data. Result Files: A new class was also added to handle writing LBN files. The class is called "CResultFile" in HandleResultFile.cpp and it provides a simple interface to open for read/write/append access, close, flush to disk, etc, for a simple text file. (We know we are going to need such result file shortly for writing the output of the Find_Pedestal algorithm). Internal: New CBusCardBase Object Holds the Card MotherBoard and Card Address, a card description, eta and phi offsets (for reference), and a link to a chain of its daughter registers (while the base card doesn't actually have any). New CBusCardCtfe Object Implements the Ctfe Card and includes all registers from both of its two card addresses. It also knows how to set a Trigger Tower Threshold for any of the reference sets given the desired value in GeV. It has an Initialize function. New CBusReg29525 Derived from CBusReg with additional functions to retrieve one given Previous Time Slice, or all Time Slices. Update CBusReg Object to now accept a constructor with a pointer to a Mother Card and keep a linked list of Reg Objects, similar to the FW model. New CommandFileTrigTwrInfo.cpp to handle Trigger Tower Info Command Files. Update Dlg_IO_Ctfe_Dac.cpp to be able to call TTI command files. Create new enumerated types for Eta Sign, Eta Magn, Eta Magn By 4, Phi, Phi By 8, Ref Set Type (EM/HDVeto/Tot), and Trigger Tower Type (EM/HD). New Dlg_Msg_L1ct.cpp file to provide templates for L1 Cal Trig Messages. Add new keywords to HandleCommandFile.cpp, .h for the new Trigger Tower Info Command File. Start using a new Macro to implement straight forward keywords. The new keywords were added this way, but the rest of the file was not retrofitted. The L1ct object has member functions to set a different coverage, check if a Trigger Tower Mask is within current coverage, set the threshold for a Reference Set over a tower sub-range. The Card Addresses for the L1CT are recorded in L1ctCardAddresses.cpp and L1ctCardAddresses.h. Unlike for L1FW, the card addresses are not all recorded as pre-compiler constants, but use a few constants and functions to compute the address of a given card from its eta, phi coordinates. Flip the order of the enumerated values for Sign Eta, now Pos=0. Neg=1. Update L1CT message parsing for phi ranges (e.g. "TT_Phi (1:8)"), as the above change broke the (already questionable) mixing of enumerated types for Asserted/Negated and TT_Eta_Pos/TT_Eta_Neg. Add in Tcc_Monit_Data.hpp new data structure "Tcc_Block_Cal_TT_ADC" to hold info for the new type "eTcc_Block_Type_Cal_TT_ADC". Add member variable and a member function to MonitPoolData.h to record and retrieve Trig Twr ADC info. Add member function to MonitPoolHelper.h to Collect Trig Twr ADC info. Drop unused variables from RegBase, FpgaCommon, and CardBase. Expand the use of Macros in HandleCommandFiles.cpp that was started in an earlier version. This makes the code more compact and clearer with no difference in functionality. Clean up the Initialization message to separate the actions for L1FW, L1CT, writing the LBN file, etc. For this reason there now is a L1CT_Initialize routine that can be called directly (cf. above), and a L1FW_Initialize routine that in fact cannot be called directly but is part of the system level initialization sequence. At the moment, "L1FW_Initialize" is in fact synonym to "init" which is the system level initialization. Create new CBusCardMTG with methods to initialize the card, and to control the Read_AB and Write_AB pipe BUT this is not used presently and until we better understand how we are going to use the MTG and what PALs we want to use. At the moment only the L1CT Init auxi file initializes the MTG card. Add the MTG Card addresses to L1ctCardAddresses.h. Replace all #include "Trics_II.h" with #include "resource.h" in all dialog implementation files and all other files where it is used (except Trics_ii.cpp). "resource.h" is sufficient in all these cases and prevents confusion with all the files shared by TRICS, VME_Access, and/or L2RS. All these projects have their own "resource.h" file created by Visual Studio which will be properly picked up. Tailor CommanFileSelfMsg.cpp to properly connect to the correct Dialog box for TRICS vs L2RS. HandleBit3Adaptor61x.cpp to record a "Warning" status (which is a new value) when a Bit3 Adaptor cannot be initialized (e.g. because it is powered off) which is different than the "Error" status for a non-existent adapter. This is used in L2RS to probe which L2 crates are currently connected and powered. Rename the MessageTccConsumer, MessageTccParser, MessageTccDispatcher, and MessageTccExecuter to MessageL1xxx. There is a new set of MessageL2xxx files. There is no real change to the MessageCoorxxxx which are still used for the real Coor messages. MessageL1xxxx are classes mostly derived from MessageCoorxxx to provide additional messages (e.g. ForeignBaseTickSelect). The MessageL2xxx files will implement all of the L2 message functionality without the MessageCoorxxx equivalent. Note that L2RS will still use the base MessageCoorParser files. MessageCoorParser needed to be tailored for L2RS to skip the part that fills in the trigger tower coordinate ranges when they are omitted in the reference set messages. This requires using information from the L1ct object, which is not desirable for L2RS as it would pull in a lot of code. This is required in Trics in order to follow the current defined coverage for L1CT instead of defaulting to eta(+20:-20). Tailor HandleCoorConnection.cpp which is the top level file for the management of the COOR connection channel. It will now use the MessageL1Consumer for TRICS and MessageL2Consumer for L2RS Tailor IP_PortNumbers.h to use a different set IP Port Number for Trics vs L2RS: Coor Connection (52160 vs 52165), the Remote Console (52161 vs 52166) and Monit Server (52162 vs 52167), while only Trics has a luminosity server (52163) New File Dlg_Test_Find_DAC.cpp/h to implement the new Find_DAC dialog. New File L1ct_TrgTwr.cpp/h: to implement a Trigger Tower with essentially a link to the CTFE cards that handles it, an initialize method (currently not used) and a Find_DAC method, as well as method to display Trigger Tower coordinates and ranges in a uniform manner. HandleLogFile.cpp: Split the Date Tag (e.g. "20010530") to a utility "DateTag()" now in UtilStrings.cpp Split the functionality to figure out which file version number comes next to a utility "AddFileVersion()" now in UtilFiles.cpp. The momtivation was that Find_DAC can now re-use these utilities. Rename the MonitPoolServer, MonitPoolManager, and MonitPoolData to MonitPoolL1xxx, and create new MonitPoolL2xxx for L2RS. Tailor MonitControl.cpp which is the top level file for the management of the monitoring and lum services so that it can use common code for Trics and L2RS while calling a different set of MonitPoolL1xxx, (and MonitLumManager, MonitLumServer) for TRICS vs the new MonitPoolL2xxx files for L2RS. Create Base Class HsroCrate from which HsroL1Fw and HsroL1ct are derived. This separates the generic actions from the specificity of each readout crate. The base class contains the pointers to the various cards in the crate, while it is the derived class that has instantiated the objects behind the pointers. The base class then know how to initialize, etc, all cards with a non-null pointer. Separate Supporting Programs: Create a new program for the Toy Trigmon Suite to display the Cal Trig Trigger Tower ADC Information. One can display any One ADC Time Slice, or the average of the previous 1:7 time slices, or the standard deviation of the previous 1:7 time slices. Update Remote_Console program to accept a different IP port number as a run-time parameter, so that it can connect to the L2RS port. Update the Remote Console application to detect lines that start with a M$ (or S$) and swith to printing the line in yellow (or purple). Update the Luminosity Test Client to display the new Run Number and Specific Trigger Mask data being sent. cf. http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/trics_support_programs.txt for details. Other work: Start a L2RS project. That's "L2 Relay Software", for lack of a better name, for the L2 TCC code. At the moment, it is little more than VME_Access with a remote console. This is a separate Visual Studio "project" in the same "workspace" as Trics's code. Much of L2RS code is in fact re-using of Trics code. - console - logfile - remote console - bit3 interface - COOR command interface (but different messages) - monitoring pool manager (but different data, and collection) - monitoring server (but different data) Made small changes to Trics code, as tailoring or renaming was necessary for better code management. Also started on new L2 specific code - L2 crate (with the ability to detect which crates are online and the crate type from the crate ID read from the DPM). - L2 Trigger (set of crates) - L2 specific monit pool management - L2 specific monit pool server - L2 specific COOR message consumer, parser, dispatcher, executer, printer Overall most of the structure is now in place, but more L2 specific work is needed. Also revive and bring up to date some old Prescaler test code to model the prescale percentage behavior and determine that Dean's divide-the-turn-number-by-512 mode for pulser runs only exposes every third bunch because 512 is not prime with the length of the prescaler shift register. -------------------------------------------------------------------------------- TRICS II Version 9.1 Release Notes ------------------------- 7-MAR-2001: (Rev I) General: The primary goal of V9.1 is to implement the Luminosity Monitoring Server, and improve the general Monitoring Server architecture by using a separate process to collect the data at 5 sec intervals. The VRB+VTM card that was in Slot #8 has moved to Slot #19. The Data Block Format Version.Revision has been updated. cf. HSRO Crate Initialization below. Monit Data Pool and Luminosity Block Management: Add new IP Server Port #52163 for the Luminosity Server (not operational) Make a test Luminosity client to connect to this new Lum Server Port. New Files to manage the different components of the new monitoring model - MonitControl.cpp Start and Stop monitoring services (i.e. start and stop needed threads) Holds variables to control Monitoring Behavior (e.g. Monit_Server_Silenced) - MonitPoolData.cpp Holds the Monitoring Data Pool itself. Routines to update and retrieve this Monit Pool data from different threads without interference. - MonitPoolHelper.cpp Routines to help read and gather the disperse monitoring information. Formerly called HandleMonitData.cpp - MonitPoolManager.cpp Separate thread (sub-process) to collect Fresh Monit Data every 5-10s. First try to capture a triggered event and wait up to 2 sec, then force immediate capture if no event has naturally occured. We verify that the Capture Monitor Data Pending Bit is set in the corresponding L1 Helper Control Register right after the Request to Capture Monit Data is made. (note that there could be a trigger firing during the 5 us window between write and read, but this should still be a useful test for the moment). - MonitPoolServer.cpp Separate thread to field and service Monitoring Requests (i.e. Taka, and Toy TrigMon) Formerly called HandleMonitServer.cpp. - MonitLumManager.cpp Separate thread to increment the Luminosity Block Number every 60 sec Push some data out (simply Per Bunch Monitoring Data for the moment) when the LBN is incremented. - MonitLumServer.cpp Separate thread to field and service connection to Luminosity Database Manager Program on the Host (i.e. Michael Begel's) The data pushed out by the Luminosity Server is the old Per Bunch Scaler Data Block instead of the new data block type(s) needed for luminosity. We started implementation by using a block that already existed and was vaguely related. This will be replaced by the new/different block type(s) with the contents that is outlined elsewhere. Trics however stuffs the LBN in the field normally reserved for format version number. This may be useful to Michael Begel for short term tests (or maybe not). Update the Tcc_Monit_Data.hpp and send it to M.Begel. This file now includes the Luminosity Server information in the form of two structures: A "Full" Luminosity Data Block and a "Brief" Luminosity Data Block. The Brief Block is a truncated version of the Full Block with only the Foreign Per Bunch Scaler information. In the process of creating these new Monitoring Block types, also define a new Tcc_Block_Extended_Header as a superset of the old Tcc_Block_Header with additional fields for new flags: "System non-operational", "Data Not Current", and "Triggered Beam Crossing". To update the L2Accept Field of the Luminosity Data Block Full we use the L2 Accept AONMs (instead of the L2 Answer TRM which would record the global L2 Accept Rate instead of the individual per Spec Trig rate... because we are in L2 Bypass Mode). Timing of Monit Data Manager and Luminosity Block Manager: Trics polls the Monit Data Captured (i.e. capture triggered event) at 10 Hz. Trics also checks the necessary programming of the L1 Helper every time it polls for Monit Data Captured, and reports an eventual error at most once per Request. The Refresh algorithm remembers when the last successful Monit Pool update happened (truncated down to the whole second) then waits 5 seconds before asking for a Monit Data Capture again. Polling to see if an event has been captured, and checking if it is time to get fresh data are both done at 10 Hz. The time measurement used is truncated down to the whole second. Taking this into account, we should see a refresh time of between 4 and 5.1 sec when data is flowing at high rate or up to 2 sec more for low or no rate. Similar thing for Luminosity Block Increment Timing algorithm, but the nominal time between successive increment is 60 sec and this is independent of data flow rate, as it always captures data for an immediate random crossing. Add a second time context to decide when it is time to send another Brief Lumninostiy Data Block. New Safety Net: Implement "Do you really want to do this: Yes No " on critical actions: A two-option Yes/No dialog box pops up whenever the user: - clicks on Exit from the main menu - clicks on "Configure L1&L2 Frameworks" in the Master Command File Menu - clicks on "Initialize L1&L2 Frameworks" in the Master Command File Menu - send a "L1FW Config" message from the "Send COOR Message" Menu - send a "L1FW Init" message from the "Send COOR Message" Menu Monit Data Server: Add a new type of monitoring data: TCC now captures and serves HSRO data (rebuilt from the Monitoring registers and NOT from VBD data) and serves this information as a new monit block type. Add a new program to the Toy TrigMon Suite to display this data in the familiar Formatted Dump format. cf. "_Hsro_Toy_TrigMon" Shortcut on TCC. This is a simple/convenient way to look at Monitoring Data to verify/observe triggered data which is not so obvious in Toy TrigMon. Finding healthy data in this display does NOT prove that Readout to L3 is working properly, as this data is NOT read from the VBD, but from the Monitoring Data Registers of each THE-Card. I have been thinking of adding the ability to retrieve "true" VBD data over the Monitoring path, but this has more complex implementation issues. It will also require mini-pausing the Framework and will have thus to be a controlled access resource (not public knowledge). Upgrade (or kludge) the Geographic Section part of the standard Monitoring structure to stuff in a previously unused/spare/reserved \ field the lower 16 bits of the Geo Sect Start Digitize (i.e. L1 Accept) Scaler as read from the outpu FOM cards. Upgrade the Block of type "L1FW HSRO" to use the new Extended Header. This Monitoring Data Type is not used by Taka or Michael and this non-backwards-compatible upgrade will not affect anybody else. For the development version of Trics, now fill the Tick and Turn Fields with a quantity derived from the current time, which lets the client display the actual elapsed time between samples without having a real Framework Tick and Turn Scaler available. Initialize the Monit Pool Data (to Zeroes) at boot time (this includes the Luminosity data) so that reasonable data is served even before th system is first declared operational. Resource Locks: TricsLocks.cpp holds the resource locks that we now need for full multi-threaded operation. - One lock (Mutex) to prevent monitoring pool data to be updated while it is being read and sent to a Monitoring Client. - One lock to prevent another thread to launch a new Capture Monit Data before another thread is done collecting the data last captured. - One Lock to protect against the Framework being declared non-operational (e.g. by config or init or SCT) at some importunate time (e.g. while Monit Pool Manager programs is in the middle of poking at the L1 Helper in intricate ways). This new Lock and additional checking for this operational state protects the Monit Pool Manager program from disturbance during initialize or SCT AND vice versa. - One Lock for Pause and Resume to protect sections of code from having this resource changed while some critical sequence is executing. This includes every time any AONM/FOM/FOM++ resource is programmed and TCC needs to mini-pause the framework. This also includes when TCC needs to increment the Luminosity Block Number and capture a new Luminosity Data snapshot while guaranteeing no events are flowing. Measure the Lock acquiring+release time penalty at about 0.18 us per pair (asuming the lock is available). This is very small, and makes it possible to add a Lock around every Trigger IO function call. This will be done in a future revision of Trics. System Control/Status Dialog Menu: Global control values in CMonitControl hold the Time between successive Monit Pool Refreshes and the Time between successive Luminosity Block Increments. These control values can be modified through the "System Control/Status" Menu to change the default 5 sec interval for Monit Data Refresh and default 60 sec for Luminosity Block Number increment. Added a global control value to hold the Time between sending successive Brief Luminosity Block. This is in addition to similar global control values above to hold the Time between successive Monit Pool Refreshes and the Time between successive Luminosity Block Increments. All these control values can be modified through the "System Control/Status" Menu to change the default 5 sec interval for Monit Data Refresh, or the default 5 sec for sending a Brief Luminosity Block, or the default 60 sec for Luminosity Block Number increment and sending a Full Luminosity Block. When one of these values is changed in the "System Control/Status" Meny, the corresponding "<- Set" button situated next to the quantity must be pushed for Trics to ingest the new value (this avoids transient values). These quantities are specified in milliseconds but Trics only polls the current time at 10 Hz. There are two reasons why Trics does not use timers to wait and wake up at specific times. Number one is that other independent asynchronous events may change the time the next update is needed (e.g. after an implicit or explicit request to increment the LBN). Number two is that Trics also uses the oportunity to check every .1 second whether the thread was politely requested to gracefully exit. I also haven't figured out how one is supposed to make ACE wait on multiple events, like a timer and/or a mutex. This was straightforward to do in VAXELN, and has to be doable in ACE too. The previous time granularity method used the simple time() function which only gave time measurement truncated to the current second. Upgrading to finer granularity will make the luminosity service cleaner and .1 second is probably sufficient. Note also that this quantity only controls the time when the thread wakes up, but in the case of the monitoring pool the time when the monitoring data ends up being captured will still fluctuate. Single Chance Test: SCT Initialize now declares the L1FW non-operational which will prevent the Monit Pool Manager and the Luminosity Manager from generating any IO while sending blank data to their respective clients. It is not clear to me what I will need to do with LBN; send 0 to emphasize that the data is junk or stick to the last LBN to maintain continuity. The current implementation is to keep sending the last LBN. Declaring the Framework non-operational means that all messages from COOR (except Initialize) are acknowledge with an error and no action. This should actually be a good thing. COOR Commands: Add a new COOR Message: 'force_l2reject': The user sends "L1FW_Spec_Trig 0 force_l2reject" from the COOR Message menu to program the L2FW L2 Answer TRM to simulate a negative decision from the L2 Global for SpTrg #0 and thus generate 100% rejects from SpTrg #0. The user sends "L1FW_Spec_Trig -0 force_l2reject" to return SpTrg #0 to the default 100% accepts. The SpTrg 'Deallocate' message was updated to restore default 100% accept. Update the COOR Message 'Increment_LBN' that was a NO-OP in V9.0 to now cause the LBN to be incremented and push a luminosity block out. Modify action for COOR Message 'L1FW_Spec_Trig [SS] Expo_Group [X]' to change programming of the FOM++ by adding a copy of Start Digitize Geo Sect #31. FOM++ Channel #36,37,38 (decimal, zero-based) *CONTINUE* to be programmed to generate a L1 Strobe, i.e. any allocated SpTrg Firing will generate an asserted output. (note: Channel #38 is currently a spare signal) FOM++ Channel #39 *IS NOW* programmed as a copy of the Start Digitize FOM Channel for Geographic Section #31, i.e. the L1FW Readout Crate. Modify SpTrg 'Deallocate' message accordingly to undo/update the above programming. Increment Logical Block Number on certain requests from COOR: Add implicit "Increment_LBN" to the "Start_Run", "Stop_Run", "Begin_Store", "End_Store", "Pause_Run", "Resume_Run", "SCL_Init", and "L1FW_Init" commands and the new Luminosity Block Number is appended to the acknowledgement message sent back to COOR. Note that "Start_Run" has an implicit "SCL_Init" which in turn also causes the implicit "Increment_LBN". Note that Pause/Resume_Run messages are different from L1Fw_Pause/Resume: Pause/Resume_Run is a notification of overall Run Status, while L1Fw_Pause/Resume is the active control of triggering while COOR programs some resources (e.g. enable/disable SpTrg). L1Fw_Pause/Resume messages are sent only to TCC while Pause/Resume_Run messages are sent to all systems. When the LBN is incremented, a Full Luminosity Data Block is pushed by the luminosity server with the apropriate flag(s) set to specify the reason for the luminosity block increment. This implicit "Increment_LBN" only happens when the system is considered "Operational". The Start/Stop_Run, Pause/Resume_Run, Begin/End_Store messages were until now mostly no-op messages. They are now treated like other messages in the sense that TCC will answer "sorry the system is not operational" if COOR hasn't properly configured and initialized the system. Add two arrays to the L1fw object to remember the current prescaler ratio and percentage of each specific trigger so that it can be sent to the luminosity client. HSRO Crate Initialization Add initialization of VRB's Buffer Starting Address Registers to configure all VRBs for 16x2kB buffer mode instead of the default 8x buffer mode. cf. http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/ Hsro_Crate_Initialization.txt Add a Wait during VRBC Initialization after the reset command and before trying to read the SCL Status register. Wait 50 ms after step #II.c in Hsro_Crate_Initialization.txt Note: the order of initialization VRB,VRBC,VBD has NOT been changed The VRB+VTM card that was in Slot #8 (now empty) has moved to Slot #19 (previously empty). (Slot #8 has a hardware problem). The 4x AOIT TRM cards serviced by this VRB+VTM have moved with it. This VRB card will continue to be the first card read out by the VBD. The VRB slot readout order will now be 19, 9, 10, 11, 12, 13, 16, 17, 18. Other VRB cards have not been affected (not even the order they appear in the readout). The HSRO VBD event dump/analyzer automatically tracks along. The Data Block Format Version.Revision has been updated: its revision number has been incremented; it is now 1.1. This change will not confuse L3 ScriptRunner while it retrieves the SpTrg Fired Mask, LBN, and L1 Accept Number. Send COOR Message Dialog Menu: Add 'force_l2reject' and 'Increment_LBN' message templates. Command Files: Resurrect the "Include_File:" command which makes a recursive call to the specified command file while passing full context into the called file and saving full context when coming out of the call file (unlike the "Call_File:" Keyword which drops all changes made in the called file). This "Include_File:" keyword is useful to call a common file where a list of symbols could be defined to be used in the body of other command files. Serial Programming of CTFE DAC: Create new Menu "CTFE DAC Programming" where the user can program each DAC on a CTFE Card one at a time (later also one channel at a time, or the whole card at a time). We may also later consider to enable command file access. Split part of the former HandleCbusIO.cpp &.h into a new set of files CBusReg.cpp & .h. Create new CBusCtfeDac.cpp, & .h file to manage the Serial Command Programming of the new CTFE DACs. The user can write any logal value into the EM and Had Gain and Zer DACs of any of the CTFE card's four channels. The user can also "Reset Whole Card (=Set Default)" to force the DACs to a known state where they will listen to commands. Add option to trace message and show every IO to the CTFE Card Board CSR Register while sending out the serial command. This option is controlled by a check-box switch on the sub-menu to turn this feature on/off. CBus Random Register Test: There is a new sub-menu called "Rand CBus Reg Test" This is a new sub-menu to implement for CBus Registers the same functionality as is available for THE-Card Random Register Test. Just like for the classic Random Register Test, the user can enter ranges of registers manually or with a command file. cf. http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/ syntax_rules_cbusregtest_range.crt This functionality may also be added to the VME_Access program, but at the moment it is only available as part of TRICS. CBus Register Access: Upgrade the CBus Register class read/write functions to now do Pre-Write Read-Check and Post-Write Read-Check (with 2nd attempt on Post-Write Error). Also Upgrade the CBusReg routines to maintain a pointer to a previous register, have a Read Mask, Write Mask, Remember Last Read, Last Write, and keep track if it was written to at least once. Fix the Cbus IO sub-menu so that the spinner control for the Function Address field has the proper range 0-255 (instead of 0-63). New Time Routine: Make a new TimeMilliseconds() routine that returns the time since 1-JAN-1970 as a 64 bit integer in units of milliseconds much like the time() routine returns the time since 1-JAN-1970 but as a 32 bit integer in units of seconds. This routine is in MonitControl.cpp for the moment. Memory Leaks: Notice a memory leak during fpga download. It has probably been there for a long time, probably from the start. This was a simple (and stupid) omission of deleting a temporary dynimically allocated object in CommandFileDownloadFpga.cpp. Do a systematic manual check for memory leaks by matching all "new" with all "delete" and find a few more minor omissions in Dlg_IO_Load_Fpga.cpp (missing delete temporary generic card in the de-program Fpga), Dlg_Test_Hsro.cpp (missing delete the L2Helper), HsroL1fw.cpp (missing delete VBD card), L2fw.cpp (missing delete the L2Helper), Internal: Skip most of the Fpga Download IOs for the development version of Trics to speed up tests that involve "downloading the fpgas" to pick up the correct FPGA version numbers. In CFpgaL1fwHelper add a function to request Capture Monit Data, f_okRequestMonitData, and a function to check if it happened, f_okCheckMonitDataCaptured. Add similar functions to CL1FwCardL1fwHelper to call the Fpga's functions and keep track of the number of errors to declare the system non-operational if needed. Fix Bug in definition of Read and Write Mask for some L1 Helper Fpga TSS Control Registers. This was causing failure of the new f_okCheckMonitDataCaptured function. HandleMonitData and HandleMonitServer have now become MonitPoolHelper and MonitPoolServer. Declare some important flags as "volatile" so that repeated tests on these variables have no chance to be optimized out. Note that TRICS is still not compiled optimized. This has been applied to g_eynL1fwOperational and mg_eynMonit_Server_Silenced. Notice that FpgaSupport::Initialize was resetting the Fpga's scalers twice in the row. This was a typo and was removed. Fix HandleCbusIO.cpp where the outgoing Ironics data was not inverted in the case of TRICS_IO_BIT3_API. Added the keyword "To_Cbus_FA:" to support CBus Register Range Command Files. Separate Programs: cf. new www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/trics_support_programs.txt for details on all Trics support programs Increase timeouts of all test client programs to 30 sec. HSRO_Trigmon: This is a new program (with "_Hsro_Toy_Trigmon" shortcut on TCC's screen) added to the Toy_TrigMon Suite to display the new type of Monit Data served by TCC. This shows each THE-Card's HSRO Data in the familiar format of the Formatted Dump format. _Hsro_Toy_TrigMon also displays the new flags available from the extended header. ("System non-operational", "Data Not Current", and "Triggered vs Random Beam Crossing"). (Note: this extended header was not available at the time the main trigmon data was defined and thus cannot be displayed in the classic Toy Trigmon). Toy TrigMon: The classic TrigMon_Test_Client (with "_Toy_TrigMon" shortcut on TCC's screen) now displays Expo Group of each SpTrg, plus a "Disable Mask" which is NOT a straight copy of any TDM reg. cf. http://www.pa.msu.edu/hep/d0/ftp/tcc/monitoring/tcc_monit_data.hpp Update the Toy Trigmon program to show the newly available GeoSect L1 Accept rate. Also update the program to allow user control of how much information is being displayed with each refresh. Type "B" for Brief or "F" for Full (or "Q" to quit) where one previously only typed to get the next sample. Test_Luminosity_Client: This is a new program to connect to the new Lum Server Port and receive Luminosity Monitoring Blocks. It displays the Luminosity Incremented flag and the reason for the LBN increment. It is also watching for consistency and ready to display problems in red. It will display all of the information in the luminosity blocks for all Spec Trig currently defined. This program is used at MSU with the development version of Trics to connect to the Luminosity Server Port. It can also be used at DZero to connect to the Monitoring Server port instead and watch the data being served to the Michael's Luminosity Monitor Program without interfering with this official Luminosity client. Also add the option of automatically asking for a luminosity block at specified intervals. VME Access: Update this separate application originally created for the L2 Test Stand. It used to only offer the 'VME IO" Sub-Menu. It now has the "Register IO", "CBus IO", "Configure FPGA", "Card CSR", and the new "CTFE DAC Programming" Sub-Menus. Find and fix a problem with the CBus IO, where the data was not inverted on its way out to the Ironics Ports. The VME Access program uses the Bit3 API interface (as opposed to memory mapping for Trics). Flipping the outgoing bits was present in the memory mapping method but forgotten in the API method. This had never been tested or used before. -------------------------------------------------------------------------------- TRICS II Version 9.0 Release Notes ------------------------- 30-Nov-2000: (Rev W) General: Rev U,V,W use new TDM FPGA (i.e. new prescaler model) Rev <=T use old TDM FPGA (cf. 000_trics_ii_revision_notes.txt for othe diff) Rev V expects the New TTS Fpga design which reads out Turn LSW first, then Turn MSW, then Tick, then 0x0. Update the Register Address of the Monitor Copy Registers for the Tick and Turn Scalers. This version takes full control of High Speed Readout and VRB Readout Crate. There now is a L1FW Readout Crate Object made of 1x VBD, 1x VRBC and 9x VRBs. Each VRB Card in this crate knows how many of its channels are used and which L1FW Card is attached to each of its channels. Trics V9.0 initializes the VRBs+VRBC+VBD (in this order) either - when COOR (or the TRICS button) says L1FW_initialize - when you click on "Initialize" on the HSRO Test Menu (among other things done during HSRO Test Initialization) The L1FW Readout Crate cards are initialized according to http://www.pa.msu.edu/hep/d0/ftp/l1/framework/hsro/hsro_notes.txt Add Raw and Formatted event dumps read back from VBD (cf. below). Change L1 Helper control of delay between L1 Accept and Capture HSRO (cf. below). New Dialog "System Control/Status" (cf. below) with new flag to prevent Monit Server from generating VME cycles. Expect 8x Miguels in the EG AONM and L1Bz FOM in sites 9-16. (Note the FOM++ remains at 4x Miguels with only 1x slice of data). Expect SM in slot M123-Bot-19 connected to second fiber of VTM in VRB readout Crate Slot #18 Expect L1AL2 Fpga in Site #16 of SM in slot M123-Bot-19. Fix Monit Server Per Bunch Scaler Readout of Tick #159 (cf. below). Note: still uses old TDM Fpga Pre-Scaler model. HSRO Timing sequence: The issue is to align the Readout data with the triggered crossing. This had never been checked, except for the Tick and Turn Scaler. In particular the delay values in the L1 Helper were only a best guess, which proved to be off. SCT was certifying that the BXSHR control values were mutually consistent (except for the Tick and Turn Scaler that cannot be checked in absolute value, only in its increments). SCT is however using a different control of these delays while the L1 Helper is in Test Mode with a programmable canned pattern of timing signals, in contrast with the Normal Mode which uses the stimulus of the L1 Accept Signal. Change L1 Helper Normal Mode Timing: - issue Capture HSRO with delay of 1 Tick after L1 Accept (i.e. load 0x1 in Reg 9 of L1 Helper, instead of 0x4) - issue Capt Monit Data with delay of 1 Tick after L1 Accept and only issued on explicit request from TCC. (i.e. load 0x81 in Reg 10 of L1 Helper) - issue Transport HSRO with delay 1+2=3 Tick after L1 Accept (The previous delay was only 1 tick away from Capture) (i.e. load 3 in Reg 8 of L1 Helper) Change L1 Helper Test Mode Timing: - Issue Maginot Line 1 Tick into the canned pattern (i.e. load 0x0201 in Reg 23 of L1 Helper, meaning up at tick #1, down at tick #2) - Issue Capture HSRO 7 Tick into the canned pattern Note: The value pre-Rev-K was 6. (i.e. load 0x0807 in Reg 21 of L1 Helper) - Issue Capt Monit Data 7 Tick into the canned pattern (i.e. load 0x0807 in Reg 22 of L1 Helper) - Issue Transport HSRO 7+2=9 Tick into the canned pattern (i.e. load 0x0A09 in Reg 20 of L1 Helper) Note: There are thus 6 ticks between Maginot line and Capture Monit Data which seems like quite a LONG delay. Where is it all going? my guess: 1x tick to get into the second slice of processing 1x tick to get through the second slice and into the L1 Helper 1x tick explicit delay in the L1 Helper 3x ticks of implicit delay to build minimum history in all BX Shift Registers Increment every Main array and BSF BXSHR by 1 count for L1FW Cards to keep track of the above changes. - e.g. typical AONM now gets 2, typical TDM or FOM gets 1 - except for TTS Scaler Card which was changed from 4 to 1 - these values apply to both normal running and SCT running But maintain previous BXSHR control values for L2FW TRM, AONM, FOM Cards, as their usage is different in the L2FW where the multiple slices are for successive L2 Decisions instead of successive BeamX. New Dialog "System Control/Status": "System Operational" allows to see and modify this global status. When the system is Non-Operational, COOR messages are returned with an explicit error acknowledgement until the next Initialize. "L1FW Paused" see and modify the current Pause/Resume Status by sending a Pause/Resume message, as needed. "L2 Global Bypassed" Not yet useful, but this is becoming the place to collect all system-wide status information. Let me know if you think of other. (e.g. Total number of Initialize or SCl Init since last Configure ?) "Monit Server Silenced" allow to see and modify a NEW flag that prevents all IO by the Monitoring Server (e.g. for Taka's Global Monitoring, or Toy TrigMon). When this flag is set the Monit Data Server stops requesting Immediate Capture Monit Data, and stops collecting the requested Monitoring Data. Blank Data is returned while the Monit Server is "Silenced". This flag is automatically cleared by an Initialize message from COOR. "Monit Data Every Event" to control this L1 Helper function (so you don't have to go hunting around for the L1 helper addresses) "System Operational" vs "Monit Server Silenced" - "System Operational": When the system is NON-Operational, all COOR messages (issued by COOR or by the Trigger Expert) fail with a bad acknowledgement. - "Monit Server Silenced": When the Monit Server is silenced, normal trigger operation continues, but no asynchronous and uncontrolled IO is generated by the Monit Server. "Refresh" Button. All status information in this display may be changed by events external to this menu (e.g. COOR messages), and this is a request for an update. FPGA Download: We need to figure out each FPGA revision number from the name of the EXO file being loaded during Configuration and furhermore remember these values for later retrieval during Initialization of HSRO BSF Header/Trailer Data. A new piece of information is being printed to the screen along with the EXO file name which shows the Version Number extracted from the file name. The S-record file name requirements are: - there must be a file extension (e.g. ".exo") so that Trics can locate the right most dot. - the version and revision number must appear directly preceding the extension with a single underscore leading each number e.g. "xxxxx_2_3.exo" - this matches our current usage. The Version of each Main Array Fpga is recorded in the 16-word Scratch Memory of the VME Interface Fpga, using one scratch word per Main Array Fpga. The Version Number of the BSF FPGA is recorded in the currently unused Board Interrupter ID Register of the VME Interface Fpga. HSRO Control: Update Board Support Function to use the new BSF FPGA design with the new user defined words in HSRO Header and Trailer and with 4 BSF Data words. Update all FpgaSupport to initialize the new registers, and update all necesary CardXYZ to properly override the initialization of the BSF BXHSHR according to the updated document: www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/bsf/bsf_fpga_programming.txt Note that the CardLatchFM has a 4013L with a stable older FPGA and thus does NOT have the new registers. Update CardAONMCommon to properly override initialization of unused Aonm/Fom Fpgas so they do not readout. The EG AONMs and the L1Bz FOM cards reads out 2x2x Aonm/Fom Fpgas (#1,2,5,6) at 2 words per Fpga, 4x Miguel Fpgas (#9-12) at 4 words per Fpga (for TT-3, TT-2), 4x Miguel Fpgas (#13-16) at 4 words per Fpga (for TT) for the required fixed total of 32 words. The FOM++ reads out 2x4x FOM Fpgas for L1 Qualifiers, 1x FOM for Skip Next Tick, 1x FOM for the Global L1 Accept Strobe, 1x FOM for Skip Next N, and 4x Miguel Fpgas, all FPGAs readout 2 words per Chip for the required fixed total of 32 words. Update CardTickTurn to include and initialize another 14x FpgaTickTurn. Change Readout Control of Tick and Turn Card. (i.e. the Interim Proposal) - Readout Nothing from the Fpga #1 - Readout 1x Word from Fpgas #2-10 - Readout 4x Words from Fpgas #11-15 - Readout 3x Words from Fpgas #16 - for the required fixed total of 32 words. Fpgas #1-15 are setup for "Current Tick and Turn" Mode. Fpga #16 is setup for the "L1 Accept Tick and Turn" Mode. Update the CardTRM to include and initialize 12 SHED Fpgas for the Global Disable TRM (other TRMS have no SHEDs). All TRM and SHED Fpgas readout 2 words per Fpga for the required fixed total of 32 words. The FPGA Shed registers are initialized as follows: - Fpga #N+1 (N=0x0,0xf) Reg 8 gets 0xN1N2 and Reg 9 gets 0xN3N4 Override the defined SHED Data Words (cf. summary_of_fw_data_readout.txt) - SHED Info 1st Word MSByte TRICS Version compound of two fields MSNibble Major Version ID (0:15) MSNibble Minor Version ID (0:15) LSByte TRICS Revision ID (0:255) The Revision ID is typically expressed as an uppercase letter (0=A, 1=B,... 25=Z) e.g. V9.0-U -> 0x9014 - SHED Info 2nd Word Word of "Operating State Information" e.g. Is L2 FW in bypass mode, ... Format not defined, write 0xcafe for now - SHED Info 3rd & 4th Words 32 bit long "Luminosity Index" Not Implemented, write 0x00000000 - SHED Info 5th Word version-revision of the BSF FPGA used by the 4028XL's Use Tick&Turn Scaler BSF Version Number - SHED Info 6th Word version-revision of the BSF FPGA used by the 4036XLA's Use FOM++ BSF Version Number - SHED Info 7th Word reserved currently not used - SHED Info 8th Word reserved currently not used Write 0x0000 in both words - Note that the upper 8x SHEDs (site #9-16) keep the initialization data 0x8182, 0x8384, 0x9192, 0x9394, etc Create a new HsroChanTheCard class that all L1FW Card Object derive from. i.e. CardAONMCommon (which covers AONM, FOM, FOM++), CardTRM, CardTDM, CardGS, and CardTickTurn. Note that more cards (including some L2fw cards) end up including this base class, but it won't get used or fully constructed. A filter on the card ID is used in the constructor of the derived classes (in particular for CardAONMCommon and CardTRM. The L1FW Readout Crate Object is created first. When the L1FW Object is created, each L1FW card object explicitely calls CHsroChanTheCard::FurtherConstruct and passes a pointer to its BaseCard. FurtherConstruct retrieves the VRB Card Slot Number and Vtm Channel Number as listed in pre-processor constants in L1fwCardAddresses.h. It then locates the corresponding VRB Object in the L1FW VRB Crate and register in the VRB Card Object the pointer to the CardBase Object so that the VRB Card can have access to the text description of the card that it is servicing. Initialize the VRB Header User Info field according to the updated summary_of_fw_data_readout.txt MSNibble - Slot Number that this VRB is in. The value written here is the actual slot number minus 8. Nibble - Trig FW Data Block Version 0:15 LSByte - Trig FW Data Block Revision 0:255 With the Initial L1FW Data Block Version set to 1.0. Fill THE-Card Header Word #0 LSByte with the Card ID according to the updated summary_of_fw_data_readout.txt Bit 7 Vertical Master Number (0 = M122, 1 = M123) Bit 6:5 Vertical Slave Number (0 = Top, 1 = Middle, 2 = Bottom) Bit 4:0 THE-Card Slot Number (2:21) This replaces the now abandonned word count field. Fill in HSRO THE-Card Header Word #1 with the Primary (i.e. most prominent) Main Signal Array Fpga Version Number. Fill in HSRO THE-Card Trailer Word #0 with the Secondary (i.e. less prominent) Main Signal Array Fpga Version Number. Done by retrieving this information from the VME Int FPGA Scratch Memory as it was recorded during the last FPGA download. Note that if there are 8x FPGAs of each type, the FPGA in Site #1 is designated as the primary FPGA type. HSRO Test: There is a new "HSRO Test" Dialog. The old HSRO Test has been renamed "Old HSRO Test" and will be totally retired in a future version. The overall plan is to pick a set of cards (like in SCT) and verify the operation of HSRO by reading the data back from the VBD buffer and comparing it to what can be reconstructed from the Monitoring registers of each card. This can be done a number of times (i.e. loops). The idea is for this part of the test to have the minimum requirements with respect to how the system is programmed and what data is going to be transported. Each CardXYZ which inherits from HsroChanTheCard implements a HsroReadFromMonitReg method that can read the Monit Data registers and rebuild the expected content of THE-Card HSRO. i.e. CCardAONMCommon, CCardTRM, CCardTDM, CCardGS, and CCardTickTurn. Select which card to test via the "Select Cards to Test ..." button. Note that only the cards that readout are available to test (no L2FW). Add TTS Card to HSRO Test (including interim weird readout distribution). Add Gated Scaler Card to HSRO Test (including L1AL2). Note that the Card Select Menu has new buttons for these 2x cards. The "Wait Before Reading VBD" field selects the amount of time each test loop waits for the VBD to present data on VME for read back. The first environment being implemented is to use SCT to bring the system to a state of random simulated input data and random programming, then come in with HSRO Test's "Initialize" and override the programming of the system to guarantee that a clean L1 Accept and L2 Accept are generated while using the KickHelperFunction method from SCT to generate one event at a time with event transfer and capture monit data. HSRO Test after SCT: 1) Run 100-300 loops of SCT on all L1+L2 cards (no scaler checks needed) 2) go into "HSRO Test" 3) "Select cards to test..." 4) "Initialize" (i.e. force L1&L2 Accepts to crate 31, and Init VRB Crate) 5) "Go" HSRO Test without SCT. This is a manual mode, with small impact on other triggers. 1) COOR-level Initialize 2) setup a 1 Hz trigger of any kind (e.g. execute \trics\scratch\SpTrg103_FW_RO_Setup.mcf) 3) Go to the "System Control/Status" Menu Select "Monit Data Every Event" (not needed for SCT method) Select "Monit Server Silenced" (not needed for SCT method) 4) Go into "HSRO Test" a) "Select cards to test..." b) "Pause" c) "Compare Again" d) "Resume" e) wait 1 second (for 1 Hz Trigger) f) back to (b) Another environment (in the future) would be for HSRO Test to be a parasite during normal running and simply manage to pause the trigger after a Capture Monit data and read the VBD before resume-ing. Raw HSRO Event Dump: Available as a "Dump N Longwords from VBD" button in HSRO Test Dialog. The "Dump N Longwords from VBD" button reads the specified number of D32 words from the VBD Data Buffer and presents them in Hex format Truncate length of dump to the amount of memory mapped for VBD Buffer in order to avoid possible access violation. Formatted HSRO Event Dump: Available as a "Analyze Current Event in VBD" button in HSRO Test Dialog. This is both a formatted dump and an event consistency analysis. What is currently being "analyzed" - Check that the event size doesn't exceed a generous maximum of 9x VRBs with 4x THE-Card each, while we have VRBs servicing with only 3x or 2x THE-Cards. - make sure that each VRB Section still fits in the overall Event Length advertized in the VBD header. - make sure that each VRB Section still fits in the overall amount of Memory mapped to the VBD Buffer Data. - make sure the length of each VRB Section as advertized by the VBD is at least as long as a VRB header. - compare the length of each VRB Section as advertized by the VBD matches the VRB length as advertized in the VRB header. - verify the Event Number is the same in all VRB Headers. - verify the VRB Slot Numbers in each VRB Header matches expectation. - verify the User Info in the VRB Header is correct (i.e. encoded Slot Number & Data Block Format Version). - verify the Config Info is 0x0002 - verify the VRB Error Status Word is 0x00000000 - make sure that each VRB Section still fits in the overall Event Length advertized in the VBD header. - make sure that each VRB Section still fits in the overall amount of Memory mapped to the VBD Buffer Data. - For each VRB Channel pair, verify there is 0x00 words for unused channels - For each VRB Channel pair, verify there is 0x28 words for channels used - For each THE-Card Header, verify the Card ID is Correct - For each THE-Card Header, verify the Event Number is the same in all BSFs - For each THE-Card Header, verify the Primary Fpga Version is correct (- For each VRB Channel pair, display the name of each card plugged in) (- For each VRB Channel pair, unscramble data but without checking content) - For each THE-Card Trailer, verify the Event Number matches the Header's - For each THE-Card Trailer, verify the Status Flag is 0x03 - For each THE-Card Trailer, verify the Secondary Fpga Version is correct What could be improved - what can we expect out of the Firmware Info field of the VRB Header? - we could add an option to also compare event to Monitoring Data. Note: the formatted event dump fully adapts to the ACTUAL lenghts of data in each VRB Channel. This means that problems in reading out some cards will NOT polute the dump for the following cards. No matter how many words may be present in a VRB channel the formatted dump will unpack what should be the normal 40 words, even if it is more or less than what was readout in case of problem, as a compromise for help and diagnostics. This does not affect the ability to ALWAYS flag incorrect lengths. HSRO Toolbox: In HSRO Test Dialog, add buttons to independently - initialize the VBD, - initialize the VRBC, - and initialize the VRBs. Other "ToolBox" Buttons - "Pause" \ - "Resume" > done by sending corresponding Coor Command. - "SCL Init" / Another "VME SYSReset" button writes to 0xFFFF181A which is supposed to make the Vertical Interconnect Slave cause a VME SysReset in the VRB Readout crate. However it currently does NOT seem to be successful in resetting the Readout Crate. Possibly due to missing part on VME module. "Compare Again" Button will not try to cause an event, but just read THE_Card Monit Data to rebuild the HSRO content, then read back the event data from the VBD, and compare the two. Only the Card(s) selected in the "Select Card to Test..." are compared. Difference between "Compare Again" vs "Analyze Current Event in VBD" - The two actions are in fact complementary. - "Compare Again" will only look at (the selected) THE-Card HSRO Data and compare it to the actual data in the VBD. It does not try to check for sanity and content of VBD and VRB headers, nor does it separate THE-Card header, trailer, main array, and BSF data. It also only locates and checks the specified card(s). - "Analyze Current Event in VBD" will analyze the structure of the WHOLE event and provide a formatted dump of the event data. It checks the consistency of the VBD, VRB, and THE-Card Headers. It does NOT compare (but maybe it could) the Main Array and BSF Fpga Data. It verifies that All expected cards are present in the readout (and none more). Single Chance Test SCT now checks the "Triggered Tick" (i.e. pattern B) data from register pair 33/34 for the FOM++, L1 Bz FOM, and EG AONM and L1 Busy Miguels in sites #13-16. One now needs to explicitely select the TTS card if the option "Include L1 Scalers" is selected. The Tick and Turn Scaler Time Zone shift is NO LONGER tested by default until the TTS Card is selected (while it was previously always tested). The Gated Scaler Card is still not part of SCT. SCT Initialize After forcing the needed 3x extra L1+L2 cycles (in order to fill all 4x time slices on the L2FW TRM/AONM/FOM), SCT Initialize now verifies there are no more L2 cycles waiting, and if there are, just complain and flush them out (up to 4x L2 cycles). This was implemented to investigate an intermediate problem, but is in fact a rational thing to to anyway. Monit Data Server: Fix Monit Data Served to now fill in Tick #159 that was previously left at zero. The checksum for the Exposure Groups is now correct. The checksum for the foreign scalers is also now correct since Trics does a synchronous reset of all foreign scalers. Monit Server now reads and prints to the console the L1 Accept Number and Buffering Depth (read from the Gated Scaler and L1AL2 Fpgas) whenever a Phase III request comes in. New LED Line-ups objects allow displaying any quantity on a contiguous set of Card Front Panel using the TCC-controlled LED accessed via a Board Support Fpga Register. Display the lower 20 bits of the L1 Accept Number on the 20x Foreign Per Bunch Scaler Cards in M122-Top with LSBit on Slot #21. Do not try to initialize the LED Line-ups at Trics Startup time. This would fail if the FPGAs haven't yet been configured. The LED Line-ups will start being displayed as soon as Monitoring Service starts up. Also skip updating display when the system is non-operational. Display the 5 bit L1AL2 Number on the upmost 5x Expo Group Per Bunch Scalers in M122-Mid with LSBit in Slot #21. Initialize: Add the Gated Scaler Card in Slot $19. - The L1AL2 FPGA is expected in site #16 The thresholds are initialized to 1, 5, 10 and 15. - All other sites are expected to have Gated Scaler FPGAs - All gated scalers channels are initialized to be disabled by writing 0x0000 in all gate and load control registers - Except for the Scaler Channel #0 of Fpga #1, 2, 3 which are enabled to listen to their respective Individual Gate #0 by writing 0x8008 to reg 130 - All Fpgas on this card are setup to read 2x words (GS and L1AL2 Fpgas). - All channels of all Gated Scaler Fpgas on this card are setup with a BXSHR control value of 0x0000 - The L1AL2 Fpga on this card is setup with a BXSHR control value of 0x0001 Reset All Board Support Function Scalers during Initialize (one card at a time). This will reset the local one-byte Event Number and it will also reset the HSRO Status Flags in Reg 33. Synchronous reset of all Per Bunch Scalers (Expo Group and Foreign). Checksums for Foreign Scalers now have a chance to be correct. We have an updated per-bunch trigmon program to test checksums. Expos Group Per Bunch scalers already quietly remained at zero while Trics was resetting them one FPGA at a time, but Foreign Scalers do not remain quiet during Initialize. Now **ALL** per bunch scalers are reset together at the end of Initialize. COOR Commands: Implement 'Increment_LBN' Message. - to which TCC will answer 'ok ' - including the <> brackets - NNNNN is the decimal representation of the 32 bit LBN after it has been incremented - Return <000000> for the moment. Improve tags in the logfile showing the COOR commands received and processed. e.g.: I$COOR Msg # 10 : 000000000000010227 L1FW_Spec_Trig 0 And_Or_List 2 255 -247 expo_group 0 prescale 5000 I$COOR Msg Command : I$COOR Msg Status : I$COOR Msg Command : I$COOR Msg Status : I$COOR Msg Command : I$COOR Msg Status : I$COOR Msg # 11 : 000000000000010228 configure I$COOR Msg # 12 : 000000000000010229 l1fw_pause I$COOR Msg Command : I$COOR Msg Status : Accept "L2Script " Coor Command: The command is acknowledged while the content of is not parsed and no action is taken. SCL Initialize: Now reset the Read and Write FIFO of the L2FW TRM for Spec Trig Fired, and Auxiliary Data L2FW TRM. Now reset the L1AL2 Scaler. SCL Initialize does not atempt explicit Initialization of VRBs. No Card from the Readout crate is explicitely touched during SCL Init. The VRBC will receive the SCL Init signal and reset the VRBs. VME IO Dialog: Switch default state of "Read after Write" from Enabled to Disabled. We will now have to explicitely select this option if needed. (the motivation for this change is that not all VRBC registers are readable) VME IO Command File: New Keywords (cf. www/hep/d0/ftp/tcc/trics_ii/syntax_rules_vme_io.vio) Bit3_Adaptor: (Index of the desired Bit3 Adaptor Number) Address_Space: (Allowed values are 32/24/16/0 for A32/A24/A16/DPM) Data_Size: (Allowed values are 32/16/8 for D32/D16/D8) These Keywords are not required, but may be used to override the initial settings corresponding to the radio buttons in the VME IO Dialog. Special care had to be taken to make sure that any change to these values in recursively called VIO command files is forgotten when coming back to the current command file. Internal: Switch development version from TRICS_IO_NONE mode (i.e. skip all IO) to TRICS_IO_FAKE where main memory is allocated instead of calls to bit3 Memory Map interface and the IO calls are accessing this main memory instead of remote VME space. Also Trics will now explicitely Zero the blocks of memory allocated before they are used. Switching mode made it possible to test acccess to the L1fw Readout Crate. It also allows all cards objects pointing at the same card address to be mapped to the same memory space, just like the real system. For example, configuring FPGAs writes Version Numbers in the scratch memory of the VME Interface, and COOR Initialize can retrieve these numbers using different card objects. Change of approach: The special cases of cards with non-uniform FPGAs (i.e. TRM with SHED, AONM with Miguel, FOM with Miguels, and FOM++ with Miguels) are no longer handled with derived classes from the base vanilla Card classes. The TRM and AONMCommon (i.e. the common part of AONM, FOM, FOM++) are now able to support a variable number of SHEDs (for the TRM) or Miguel (for AONMCommon). Nearly all the special case code is in the constructor and in the Initialize methods. This approach limits the number of files needed to handle the special cases (dropped 14x files). This approach also limits the number of special cases in SCT and the amount of duplicated code. Implement the new FOM++ V3.1 (in Rev W): Update fpgaFOMPP to move the address of the Monitor Copy of the L3XferNum. CardAONMCommon does not provide HsroReadFromMonitReg for the FOM++, there is a HsroReadFromMonitReg in the derived CardFOM. Note that the function of the derived class only fully handles the case of the FOM++ and defers to the function from the base class for all other FOM cards. This is needed because only the CardFOM can access the m_apoMaFpgaFOMPP FOM++ FPGA object to access the L3XferNum register. Update MessageCoorPrinter.cpp to use a function (not a macro) to print the message to the screen and append text to the reply. Update CRegBase::WriteReg and WriteOnly methods to declare the value to write passed as argument (via pointer) as a "const". In fact WriteOnly was ANDing the write value with the write mask which was modifying the data to be written. This happened not to be an issue anywhere, but it could have been, or could have become in the future. Declare the prepared Prescaler Circular Shift Patterns as "const" in PrescCircShiftPattern.h to protect it from explicit overwriting (note that I don't think it is protected from overwriting via a rogue pointer). Separate Programs: A Separate "project" was also made in the Trics "workspace" for a standalone tailored version of Trics with only the VME IO Menu and VME IO command files. This is VME_Access V1.0. I am planning on adding Register IO and CBUS IO so that we can have a standalone separate program that we can run muplitple copies of without interfering with TRICS. cf. www.pa.msu.edu/hep/d0/ftp/tcc/vme_access/vme_access_documentation.txt Per-Bunch Trigmon: - now verify Checksum scaler for all Exposure Group and Foreign Scalers. - By default do not display individual ticks for Exp Group scaler, but only the checksum -------------------------------------------------------------------------------- TRICS II Version 8.9 Release Notes ------------------------- 20-Sep-2000: (Rev H) General: Allow Byte Stream (.exo) for XC4036XLA to be one byte longer. The whole stream is sent to the device. Byte Streams with either 104066 or 104067 bytes are accepted. This is the new length produced by M3.1 Xilinx software. Implement Miguel Fpga: The FpgaMiguel Object is initialized as follows: - Beam Crossing Shift Register Control = 1 - HSRO Terminal Count = 6 words per Fpga - Initialize Input Term Select (gets 0 in FpgaMiguel::Initialize then proper value in CardAONM_ExpGrp, or CardFOMPP::Initialize) Implement a CardAONM_ExpGrp Class derived from CardAONM. This class deletes the FpgaAonm objects for the sites replaced with Miguels, and creates the apropriate number of FpgaMiguel at Chip Num 13, 14, 15, 16. Modify the CardAONM and CardAONMCommon class to verify the pointer to each Daughter FpgaAONM or FpgaAONMCommon is non-Null before doing any action. This is how the CardAONM can be used both as a regular AONM card and as a base class for CardAONM_ExpGrp. Modify the CardFOMPP (which was already derived from CardFOM) to also delete the FpgaFOM objects replaced by the Miguels, and creates the apropriate number of FpgaMiguel at Chip Num 13, 14, 15, 16. Modify the CardFOM class to verify the pointer to each Daughter FOM Fpga is non-Null before doing any action. This is how the CardFOM can be used both as a regular FOM card and as a base class for CardFOMPP. Also add consistency checks with Internal Error Messages (the blue ones) in case Trics tried to program a basic AONM (or FOM) function aimed at an Fpga site now occupied by a Miguel Fpga. Implement SHED Fpga: The FpgaShed Object is initialized as follows: - Clear all Data Registers - HSRO Terminal Count = 2 words per Fpga (we know this is not right, but the proper HSRO word/fpga count as well as the total number on SHEDs is still fuzzy) Implement a CardTRM_GlobDis Class derived from CardTRM. This class deletes the FpgaTrm objects for the sites replaced with Shed, (in fact we currently delete ALL TRM Fpgas except for the 4 "truely used" GlobDis Fpgas at Chip Num 1, 2, 5, 6) and creates ONE FpgaShed at Chip Num 9. Modify the CardTRM class to verify the pointer to each Daughter FpgaTRM is non-Null before doing any action. This is how the CardTRM can be used both as a regular TRM card and as a base class for CardTRM_GlobDis. In the CardAONM_ExpGrp, CardFOMPP, CardTRM_GlobDis, L1fwCardAONM_ExpGrp, L1fwCardFOMPP, and L1fwCardTRM_GlobDis Classes, only the constructor, destructor, and the Initialize functions are overriden by the derived class, the rest of the member functions for programming the cards come from the base classes. Implement the new TDM prescaler: Code for both old and new flavors still included and selectable with a preprocessor constant "NEW_PRESC" located in FpgaTDM.h. The Prescaler Shift Register patterns are hardcoded to sprinkle the 1's or the 0's as uniformely as possible. Currently Rev G uses the Old Prescaler. Implement a "Framework Operational" Flag: Find a method which is safe with respect to the multi-threading environment. There now is a stronger mechanism to stop the zillion errors when the power is off: a) The Framework is declared "operational" only after a successful initialize b) The Framework is declared "NON-operational" i) at the beginning of the FPGA Configure ii) at the beginning of Initialize iii) If Initialize fails in any respect iv) after the Monit Server has noticed 24 consecutive IO failures while trying to force a Capture Monit Data c) while the Framework is NON-operational i) The Monit Server sends Blank Data without FW IO (and without screen messages) ii) Most COOR Commands abort with an error message and without trying to perform the action requested The CL1fw::mg_poL1fw and CL2fw::mg_poL2fw are now created in the main Trics_II.cpp before initiating the dialg box, but AFTER the initialization of the Bit3 interfaces as the creation of the Card objects also allocates the address space mapping resources. Trying to initialize these static variables directly in the class implementation code failed, because the objects would be created before the explicit user code executes. The CL1fw::mg_poL1fw pointer is now never NULL, and some instances of testing for the NULLity of this pointer have been removed (when it was to prevent an access violation) while other have been replace with testing the new CL1fw::mg_eynL1fwOperational flag (when it was to decide whether the action made sense). Issues open for discusion : - are we happy with (b.iii) and (c.ii) above? - do we need to think of a mechanism to override this operational status and more generally what do we do if there are "minor problems" during initialize? - do we want to extend this mechanism to keep COOR out during SCT ? HSRO: Update all Main Array Fpgas to provide basic Initialiaztion of the HSRO registers during the Initialization process. Default: - Terminal Count = 2 words per Fpga Special Cases: - Miguel Terminal Count = 6 words per Fpga no HSRO: (i.e. program 0 word/Fpga) - L1 Helper - FM Latch - Per Bunch Scaler - Board Support (i.e. it doesn't have the typical HSRO CSRs) - L2 Helper - L2 BAD have - L2 TRMs - L2 AONMs - L2 FOMs The HSRO registers of *ALL* BSF FPGAs were already initialized according to www/hep/d0/ftp/l1/framework/hardware/bsf/bsf_fpga_programming.txt We may still want to do something different for cards that don't readout, and that hasn't been addressed yet. Misc: Notice and work around a problem with Win32 and File Selection. - Our Environment variables (e.g. %CONFIG%) only specify the directory path (e.g. \Trics\D0_Config) without the drive letter. This is a useful approach as it makes the system more relocatable. - However this relies on not loosing the knowledge of the default drive - If we loose the default drive, then everything which depends on environment variables will fail, e.g. Initialize !! - If one clicks on a "Find..." button to select a command file and then "Cancel" out of it, the default drive may be lost (I think it goes to the system drive which is ok at DZero for the moment). Fix this by grabbing the current default drive early at the start of the program and always restoring it every time before trying to resolve an environment variable in FileLocate of UtilsFiles.cpp. Start collecting notes to improve track record of peaceful release of new versions at DZero. cf /Documentation/_Release_Procedure.txt in the source code directory. Force flush to LogFile relatively early to give chance to check on logfile success when running the DZero version of the code on a bit3-less machine, as suggested in _Release_Procedure.txt. All Dialog Menus: Override the default function called on (the "CWnd::OnOk" function) so that a reasonable action is taken instead of the default exit from the dialog menu (which was driving me nuts). - In most cases this simply validates the field edited, and moves on to the next entry field. - When editing the number of Test Loops, a makes the focus move to the 1/k/M/G exponent, and another to initialize, or start the test. - When editing a file name, a makes it load or execute the file. Let me know if that is more of a nuisance to you than helpful. Extend the line of "*" written to the screen when entering a new Dialog in order to make it more recognizable in the logfile. Configure (aka download Fpgas): The configure command now starts with clearing Bit3 errors, and aborts if this fails (e.g. communication crate powered off). The L1fw_Configure command also starts by declaring the framework non-operational (this is a new flag) so that: - COOR will have to send an "initialize" before any other COOR command will get serviced thus avoiding confusion and error messages. - the Monit Data Server will be prevented from generating IOs during the configuration process and until the next "Initialize". Suppress many of the informational messages (mainly the ones telling you that the Jtag chip, the Fpga Outputs, etc had been enabled). These extra messages are still displayed when using the Download FPGA Menu to manually load one EXO file or many via a DCF. Also always skip a line between each Fpga Download. before: % Configuring FPGA(s) @Master#0/Slave#0/Slot# 3/Chips 0b 10 0000... _ Using File : %EXO%\bsf\bsf_20_1.exo _ Byte Stream Length consistent with XC4028XL = 83523 bytes _ Closing File after Reading 5222 Lines and finding 5222 S-Records _ Board FPGA Configured Register after download is now 0b 10 0000... _ Enabling Main Array FPGA Output _ Enabling Board Support FPGA Output _ Enabling JTAG Scan Path Controller _ Activating JTAG Scan Path Controller _ Disabling Main Array ECL Output _ Disabling Global Card Interrupt _ Clearing VME Interface Reconfigured Flag _ Clearing VME Bus Error Flag now: % Configuring FPGA(s) @Master#0/Slave#0/Slot# 3/Chips 0b 10 0000... _ Using File : %EXO%\bsf\bsf_20_1.exo _ Byte Stream Length consistent with XC4028XL = 83523 bytes _ Board FPGA Configured Register after download is now 0b 10 0000... Some Vme Interface Fpga bits of the Control Register were not initialized (they were initialized by the Configure Fpga command, and never touched by anything else, but not reset by Initialize). - Now update ALL writable bits of the VME Int Fpga CSR - Now also check the Reconfigure, VME Error, and Config Error Flags and display a Warning Message (Bright White) if the bits are set. The Prescaler Ratio was not Initialized (but also not enabled), it is now reset to a ratio of 1 and no bits in the circ shift register. Fix FPGA download accounting problem that would miss adding up the contribution of nested DCF files if the recursive call depth exceeded 3. The original kludge was made more general and the maximum depth was made arbitrary, which is currently set at 10. COOR Commands: Implement L1 Qualifier Command. Note that Trics currently thinks of having 32 qualifiers (0-31) until it becomes clear that managing them as two sets of 16 is preferable. SCL_Initialize now ingested the pause/resume functionality we previously implemented from the command file so that we now don't resume if the framework state was paused before calling this command - Pause the framework (if not already paused) - wait 1 s (if the implicit pause above was needed) - call the Init_SCL.MCF wich calls SCL_Initialize.rio - wait 1 s (if the implicit pause above was needed) - Resume the framework (if the implicit pause above was needed) The command assigning a Specific Trigger to an Exposure Group now verifies that the Exposure Group has been defined first. Previously no error was generated, but the Specific Trigger would not pick up any geographic section to digitize, etc. There is now a "bad" acknowledgement message returned to COOR. Update Prescaler Command - L1FW_Spec_Trig [SS] Prescale_Ratio [R] The range of Prescale_Ratio is 1 to 2^32-1 - L1FW_Spec_Trig [SS] Prescale [R] This is a synonym of Prescale_Ratio for backward compatibility - L1FW_Spec_Trig [SS] Prescale_Percent [R] The range of Prescale_Percent is 0 to 100 Update the Spec Trig Deallocate Command - Release/re-initialize the L1 Qualifier resources - release/re-initialize the L2fw Accept/Reject FOM resources - release/re-initialize the L2fw Accept/Reject AONM resources One more round of changes to make the parsing code usable outside of the trics environment for use with the simulator. - drop the pre-compiled header feature - use pre-processor macros to flag character position on parsing error - use standard strtoul instead of A_to_uI to convert string to int Fix the problem that was causing Trics to crash when the returned acknowledgement exceeded a certain length. The message length control protection code was checking against an improper maximum length. It was using KiMaxLengthReplyTextToCoor from MessageCommand.h which was set too large compared to the KiMaxLengthStringOut from TricsMessageConsumerInterface.h that was used in HandleItcServer.cpp to create the space for the return string. There are reasons to have two separate constants, and one shouldn't really be set by referencing the other. But there now is some additional safety net code in HandleCoorConnection.cpp that checks the relative size of these two separate constants. This problem had been there all along, and recent code changes only made it aparent as it now overwrote a local CString variable (oMsg) in ItcServer::Message_Consumer and got in trouble when exiting the routine and implicitely calling the CString destructor. It also took a pretty long COOR request to reach this maximum length which may be why this had gone un-noticed. The CMessageCommandLine::NewRawCommand initialization now also takes an explicit argument telling it how much space it available to store a reply. This was not the direct cause of the above problem, but it makes more sense to make this explicit, since this part of the code will be shared with the simulator. CMessageCommandLine::CopyReplyText and AppendReplyText now use this explicit information to control how long the reply will be. COOR message Command Files: Make each command in a Coor Message Command File wait up to 2 second for an acknowlegement back from Trics before moving on to the next command (or returning after end of file). This makes a good attempt at keeping the screen messages in order so that the thread executing the COOR commands can print its messages before the thread executing the command file starts printing its next action. COOR message Dialog Menu: replace edit box for manual entry of commands with a "combo box", this means it will now remember and offer via a pull-down menu a list of the last commands SENT to Trics. Add the new Prescale Ratio and Prescale Percent message to the "radio buttons" and reorder these radio buttons a bit. Master Command Files: Master Command Files (.MCF) can now directly send COOR Messages without having to use a . MCF files can now use the same syntax as MSG files to send COOR Commands; namely: In many cases, this will cut down on the number of files in \Trics\D0_Config www/hep/d0/ftp/tcc/trics_ii/syntax_rules_master_command_files.mcf has been updated Lock Coor out during Fpga Configure evoked from MCF Menu Button: Send Message to Trics Coor Server Thread to do the configure instead of directly executing the Download from the MCF Menu main Thread. In other words: ask the COOR command server to do it instead of doing the same thing directly. The "Configure Frameworks" Button now calls the new file Configure_Frameworks.Mcf (instead of "Configure_L1fw.Mcf") which sends a L1FW_Configure Coor Command. When processing this message, Trics will then call the "Configure_L1fw.Mcf" File which calls "m122_m123_all.dcf". www/hep/d0/ftp/tcc/trics_ii/button_mapping_master_command_files.txt has been updated. See also above notes about keeping the Monit Server out of the Fpga Configuration sequence, and forcing COOR to re-initialize the Framework before processing other COOR commands. Fix SCL_Init Coor Command (and MCF Menu Button) so that it does not un-conditionally Pause/Resume the Framework: The MCF Button now calls the new command file Init_Scl_With_Pause_Resume.Mcf which contains a Coor Command to request an SCL Init. Trics will then use its internal knowledge of overall run state to know whether it needs to Pause/Resume the framework for 1 second before and after calling the file "Init_SCL.mcf" which calls "SCL_Initialize.rio" and which no longer has hardcoded pause, wait and resume. VME IO Command File: New Keywords (cf. www/hep/d0/ftp/tcc/trics_ii/syntax_rules_vme_io.vio) Bit3_Adaptor: (Index of the desired Bit3 Adaptor Number) Address_Space: (Allowed values are 32/24/16/0 for A32/A24/A16/DPM) Data_Size: (Allowed values are 32/16/8 for D32/D16/D8) These Keywords are not required, but may be used to override the initial settings corresponding to the radio buttons in the VME IO Dialog. cf. http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/syntax_rules_vme_io.vio Monitoring Server: Fix Bug that was writing junk (some AO Term Info) in the L3 Disable Scalers of the Monit Data (i.e. Indiv SpTrg Dis #0 ; #1 was sick too). Upgrade the messages logged for every monitoring request: - Make them more explicit about the success of the request: "L1FW Phase III Monitoring Request -> Getting Fresh Data" "L1FW Phase III Monitoring Request -> Capture Monit Data Failed" "L1FW Phase III Monitoring Request -> Send Blank Data (no IO)" - Suppress all messages once the Monit Server has given up on capture Monitoring Data (after 24 failed request). This will save logfile space while still being able to correlate the requests to potential problems. - Same thing for Per Bunch Scaler Request, (but legacy/obsolete Phase II requests have not been touched). When the power is off and the Monit Server counts 24 succesive failures, and quits trying to update the monitoring data, it also declares the framework non-operationsl so that COOR will have to send an "initialize" (after a "configure") before any other COOR message will get serviced thus preventing the logfile from filling up with error messages while the Framework is turned off. Single Chance Test: Update for the presence of Miguel and Shed Fpgas. The approach was to simply skip the Fpga's that are no longer AONM, FOM or TRM in their respective cards. Modify the TesterL1fwCardAONM constructor to delete the AONM Fpga's from the Miguel's sites and replace them with NULL pointers which is then used to skip these sites. Same thing for TesterL1fwCardFOMPP (for the Miguels) and same for TesterL1fwCardTRM (for the SHEDs) It would be possible and not a tough challenge to check the Miguel Outputs, but quite a bit of work is involved and this isnt' done yet. SCT Initialize was not failing when the L1 Helper or Tick and Turn intialization failed; now it does. Screen Console: Add a 2-character prefix flag to the beginning of every line. "I$" for Information line (in white) "E$" for Error line (In Red) "B$" for Internal Error line, a.k.a. Bug (In Blue) "W$" for Warning Line (in Bright White) "-$" for continuation line if the screen line had embedded This Prefix will make it easier to locate Error Messages in Logfiles. Also look below for Textpad extension that allows to color these messages while editing a lofgile!! Clean up code to use pre-processor constants for line length, flags, etc. Increase the maximum console line length (before graceful truncation). It is now set to 160 characters (including the 2-char prefix above). This is enough to support a double line (i.e. with embedded ) of 2x 80 characters. Note that this used to be 132 characters which explains the truncation of some messages, namely the "Beam Crossing Time Zone Shift" Error. Note: there is still another specialized "WriteMultiLine" function for truely multi-line messages where the length it currently set at 1024. This is used in particular for the Connectivity Test arbitrarily long description tags of each connection. WriteMultiLine does not need to be used to simply include an extra at the beginning or the end of a message. WriteMultiLine is only available for Info message (not Errors). Log File: Now split a long screen line into two logfile lines (used to truncate). The Logfile lines have a fixed 132 char length, but the last 26 char are used by the time stamp and the first 2 hold the "x$" prefix, so the max payload/line is 132-26-2=104 char. Extend the concept of 2-character prefix to every line by adding "_$" for continuation line Clean up code to use pre processor constants for line length, flags, etc. The maximum Logfile line length (before graceful truncation) currently is set to equal the console line length (the line may be split). Also Close the logfile earlier in the exit sequence because one of the steps in disconnecting ITC services actually kills the application early and skips the last flush to logfile and controlled close of the logfile. I don't really know why, but life is too short... Just close the file a bit earlier. Itc Connections: Now always display the Client's IP Address + Process ID whenever a connection is made or broken. Now the the ITC server fills the program_name and program_version field of the ITC debug information exchanged at connection time, and ITC Server will also now display this information about the connecting program. Internal: Upgrade the Tick and Turn Scaler to hold the stored expanded value (for later computation of increment) as a quadword so as to preserve the maximum range. (this used to be truncated to 32 bits of 159*T+t) In CardBase Class get rid of unused m_ubCardAddress member variable. Create a KiTotForeignExpGrp pre-proc constant instead of only using the eTotExpGroup enumerated value. Both of these constants have the same value, but sometimes one is more appropriate to use than the other. Same thing for KiTotForeignPbs and eTotForeign. Move the HSRO control registers from individual FpgaXXX to the FpgaCommon base class and FpgaXXX::Initialize only needs to delete the corresponding FpgaCommon registers in its constructor if there is no HSRO for this XXX Fpga type. In L1Fw.h harmonize the variable names for holding allocated resources. Also switch the data types from OneFomOutputProgr to arrays of EIgnoreObey. Now create the L1Fw and L2Fw objects in Trics_II.cpp before the dialog box is started. These objects are now always present, and never deleted. The mechanism to know if the Framework is operational now uses the CL1fw::mg_eynL1fwOperational static variable In MessageCoorExecuter.cpp now use pre-processor macros to implement the repetitive tasks of append the reply status, check for IO error during the command, check if the framework is operational, pause the framework if needed, and resume the framework if needed. New Files: FpgaMiguel.h, .cpp FpgaSHED.h, .cpp CardAONM_ExpGrp.h, .cpp CardTRM_GlobDis.h, .cpp L1fwCardAONM_ExpGrp.h, .cpp L1fwCardTRM_GlobDis.h, .cpp Separate Programs: Remote Console: Add Colors to messages starting with E$ (Red), B$ (Blue), W$ (Bright white) Coor Access: Write Bad Acknowledgements in Red and repeat the request with a ruler to easily spot the offending word by its advertized column number. Add a command line option [-f ] to read a file and send each line as a coor command instead of the standard interactive input. The rate is 1 line per second. The lines should include only the message payload (i.e. no command ID) e.g. "L1FW_Spec_Trig 0 Coor_Enable" Trigmon Test Client: Add a command line option -u to cause an auto-update every 5 sec. All Test Clients: Also Update the Remote Console, Trics Access and TrigMon Test Clients to fill their version information and display this information about the server they connect to. Note that these test clients advertize themselve with the Trics_II Version number available at the time they were compiled. TextPad: Make a new Syntax File Style to display Trics LogFiles Trics_Log.Syn - use reverse video, i.e. white on black - pick a font similar to the console display - highlight Error lines starting with E$ in Red (=comments) - highlight Internal Error (Bug) lines B$ in Blue (=alt comments) - highlight COOR syntax keywords yellow (=keywords) - highlight "$" yellow (=operator) - highlight file names enclosed in <> in green (=strings) -------------------------------------------------------------------------------- TRICS II Version 8.8 Release Notes ------------------------- 16-Jun-2000: (Rev H) General: Implement Phase 3 of Framework Monitoring. This installment phase has enough information to monitor all sources of disable for each specific trigger. cf. Tcc_Monit_Data.hpp and www/hep/d0/ftp/tcc/monitoring/trigger_fw_monitoring_april2000.html The Phase 2 Data Block type is still being served for a smooth transition. The Monitoring Server also serves a new Data Block type eTcc_Block_Type_Per_Bunch_Scalerfor Per Bunch Scalers. This includes all Exposure Groups and Foreign Per Bunch Scalers. Update FpgaBad and CardBad. There are now L2Busy scalers on the Bad Fpga, and all sites are populated to implement all scalers for all Geo Sect. Stop forcing Geo Sect #127 into all Exposure Group definitions now that COOR is explicitly doing it. COOR messages: Initialize: Previous versions (up to V8.7) were deleting and recreating all cards objects at initialize time. Now no longer delete the L1fw and L2fw Objects (i.e. the collection of all L1+L2 Fw cards) but instead only re-Initialize all cards. Deleting/Recreating was a sure-bet/steamroller approach Note: this approach is still required in SCT for the Tester Card Objects But this was also the reason (I believe) we had occasional losses of monitoring server. (even after testing for validity of the pointer, there were still chances for the monit server to try access the card objects between deletion and re-creation) Starting with V8.8 Initialize only creates the card objects the first time it is called, then the initialize sequence is repeated on the same C++ object instances for all subsequent Initialize requests. A necessary additional change was to flag all registers as not-yet-modified so that they can be spared the pre-write check during the first write to each register (e.g. after SCT or Power Off). Another necessary additional change was to reset the consecutive error count during L1fwCardL1Helper::Initialize so that the Monit Server will thus be able to Refresh Monit Data again (e.g. after a power off). Change the order of initialization in L1FW::Initialize to initialize the Tick and Turn Scalers last, so that the scalers can be re-synchronized after all the resources are under control. Initialize also initializes all Exposure Groups and Foreign Per Bunch Scalers and resets them, but only one Fpga at a time, so that they will may start synchronized (in particular the absolute check sum may be off, while the check sum of the differences should match). Exposure Group Andor List and GeoSect List: Update a list of which Exposure Group is currently allocated, this information is being served with the Phase 3 Monit Data. Also stop forcing Geo Sect #127 now that COOR is explicitly doing it. Note: And-Or Terms are still not "released" and will not appear as deallocated in TrigMon when they are no longer used. Exposure Group Deallocate: Now de-program the exposure group and also rebuild a list of the geographic sections still in use and update the programming of the L2FW BAD Monitoring Server: Drop the legacy initial prototype of monitoring data. This type of data will no longer be served. Rename the previous data block type eTcc_Block_Type_L1fw_General to eTcc_Block_Type_L1fw_Phase2 Create the new data block type eTcc_Block_Type_L1fw_Phase3 and alias it to eTcc_Block_Type_L1fw_General A new file HandleMonitData.cpp is created with a collection of utilities GetMonitInfoXXX to collect all the sub-pieces of data blocks of each type. Note: the only "Phase 3" Monit Data still missing is (I believe) the Exposure Group And-Or Scalers because we do not have these scalers. the Global Correlated Disable #3 (i.e. Skip Next) because it is now read from the Global Disable TRM card while this signal does not go throuh it For both of these types of scalers, the proposed cure is to add another PBS Scaler card in the Exposure Group PBS Crate and program 8 + 1 Fpga's to implement the needed scalers while using only one scaler from each fpga. Note: the L2Busy Delay and Cycle scalers will not be incrementing until a cable is installed between l2 Helper and L2 Bad cards. Create a standalone TrigMon_Test_Server Test Monit Server project for John Lee. Also Rename the Trigmon project to TrigMon_Test_Client. Internal: CFpgaAonm::Initialize and CFpgaFom::Initialize now call CFpgaAonmCommon::Initialize which in turn call CFpgaCommon::Initialize which initializes the network programming interface. Change all CFpgaXXXX::Initialize to first the new f_vClearModified routine for all registers (even the read-only registers that don't really need it) to reset the not-yet-modified flag before the true Initialize part of the routine. L2BAD programming must now be carried on all Fpgas, not only the "real one" that sends its output to the L2 Helper. This is so that the scalers operate correctly. -------------------------------------------------------------------------------- TRICS II Version 8.7 Release Notes ------------------------- 2-Jun-2000: (Rev E) General: Parse all L1 Calorimeter Trigger COOR Messages (no action taken...) cf. http://www/hep/d0/ftp/tcc/coor/coor_to_tcc_l1ct_message_syntax.txt Add all 2* 8 Exposure Group Per Bunch Scaler Cards. These cards are initialized and the scalers are reset during a COOR Initialize message. cf. www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/sm/per_bunch_programming.txt Add all 2* 10 Foreign Per Bunch Scaler Cards. These cards are initialized and the scalers are reset during a COOR Initialize message. Fix Initialization value of Skip Next N Crossing Comparator #0 with a count of 18 instead of the typo value of 0x18. COOR messages: Improve the error messages returned with bad acknowledgement of coor command by specifying the character number at which Trics detected the problem. Improve parsing of messages where characters embedded (or trailing) in numbers were not detected, but just ignored, and the error reported was misleading or not clearly pointing at the cause. This now causes an immediate error labelled as a missing space after a number. Fix two bugs where incorrect syntax could crash the parser Now allow ranges of negated SpTrg or ExpGroup e.g. to disable a set of SpTrg Now allow ranges of negated andor terms to set range of veto terms TrgMgr Messages: Add first Non-Coor Message. These messages are sent to the same port #52160 where COOR messages are received. They use the same format of a Command ID and a message payload, with a returned acknowledgement message. This message allows to shift the Tick Offset of Foreign Per Bunch Scalers. The syntax is "TrgMgr_Foreign_Scaler Base_Tick_Select

" This will change Foreign Scaler #N to have channel #1 Tick Select of P, channel #2 gets P+1, etc, with wrap around at 159. Internal: The new L1CT messages imply accepting negative numbers as lower and/or upper bounds of ranges parsing open and close parenthesis parsing the decimal point (for decimal threshold values) parsing a plus sign before number Use macros for advertizing errors during parsing During parsing the tokenizing phase now records the beginning character of each token, so that it can be used to tag errors during the next phase of interpreting the tokens The new classes CFpgaPerBunch, CCardPerBunch, CL1fwCardPerBunch have been created. The previously named CoorCommand, CoorCommandParser, CoorCommandDispatcher, CoorCommandPrinter, CoorCommandExecuter, and CoorCommandConsumer have been renamed to MessageCommand, MessageCoorParser, MessageCoorDispatcher, MessageCoorPrinter, MessageCoorExecuter, and MessageCoorConsumer They are now base classes for the new classes MessageTccParser, MessageTccDispatcher, MessageTccPrinter, MessageTccExecuter, and MessageTccConsumer which implement the TrgMgr command syntax, parsing, execution, etc, and call the base classes for COOR commands. Rename MessageConsumerInterface.h to TricsMessageConsumerInterface.h to avoid a name starting with the word Message. This file is the definition for a message consumer at the ITC receiver level. -------------------------------------------------------------------------------- TRICS II Version 8.6 Release Notes ------------------------- 27-Mar-2000: 10-May-2000: (Rev N) General: This version concentrates on adding the L2FW to the Single Chance Test. cf. below. SCT Init is kludged not to abort upon error while initializing L2fw cards. Rev L had L2fw SCT kludged so that only SpTrg #0:15 and 96:111 are verified in the L1 STFired TRM, and L2 Accept/Reject AONMs. The Accept/Reject FOMs were Initialized, Programmed and checked for all Geog Sections, but always programming overriden to ignore all SpTrg inputs outside of 0:15 and 96:111. Fix bug in CCoorCommandExecuter::ExpoGroupGeoSectList due to stupid C++ trap with "if ( ... = Obey )" instead of "if ( ... == Obey )". The end result is that the L2 BAD always had ALL channels enabled as soon as ANY geographic section is defined. I think that was the only consequence. Fix another bug with L2 BAD initialization and progrmming that would also tend to leave Geo Sect enabled once they were used once. Rename Main menu button "Download FPGA" to "Configure FPGA". Also rename the menu itself and the console message when it is entered. Also update console messages during FPGA download, or upon download error. Add a string at the Bottom Right of the main menu (just below the version number graphic). This string can have one of three values "MSU" "DZero" or "No IO" depending of the executable built (via Preprocessor switches). Suppress the screen output advertizing each ITC message received or sent on each Itc Server or Client Port. This information was making the logfile hard to read. Update intialization of L2fw L1 Fired TRMs to program 0xa220 in BSF Timing Signal Select Register (i.e. new usage of maginot line) Update intialization of L2fw L2 Answer and Auxi TRMs to program 0x2220 in BSF Timing Signal Select Register (i.e. new usage of maginot line) Update intialization of L2fw FOMs, and AONMs to program 0x2420 in BSF Timing Signal Select Register (i.e. new usage of maginot line) Update intialization of L2fw TRMs, FOMs, AONMs to program 0x0001 in Tick History Control Register. Shrink height of the Card CSR Dialog so that it fits on 1024x768 display. Shift the ascii console window a bit to the left so that it fully fits on 1024x768 display Monit Data Server: After 24 unsuccessful attempts at trying to write to the L1 Helper in order to Capture Monit Data from the Monit Server, give up and quit trying, nevre try again until the next COOR-level Initialize. This error is typically caused by the framework power turned off. When this condition is detected, the following 4 lines are displayed in blue " -------------------------------------------------------" " Warning - Consistent IO Error during Capture Monit Data" " --> STOP trying until NEXT Initialize " " -------------------------------------------------------" Make sure the Register IO menu "Refresh Monit Data" Button is not affected by this Master Command Files: Rename Download_L1FW.mcf to Configure_L1FW.mcf (Internal: also find a way to use the same constants for file names as what CoorCommandExecuter uses instead of repeating the same values, namely for osL1FW_Configure_MCF and osL1FW_Init_SCL_MCF) Button Name Master Command File Name ----------- ------------------------ "Configure L1&L2 Frameworks" -> %CONFIG%\\Configure_L1FW.mcf (same file as when COOR asks for FW Config) Register IO: Add Button in Register IO menu to "Transpose" the Fpga Chip Number from the "logical" chip number (e.g. relative Spec Trig Number) to its corresponding "Physical" number. Initialization: Reorganize hierarchy and add messages to advertize which card is being initialized. These messages are visible during COOR Init and SCT Init. More details on hierarchy are described in SCT Initialize below. L2 Framework: Add function ExcludeL2SpTrg to L2fwCardAONM to initialize or reset one of the channels to require all inputs true. The other two L2fw specific routines are ProgL2Accept and ProgL2Reject to include a particular specific trigger in the L2Fw operation. Single Chance Test - General: Now display a list of the Test Options choices before starting a set of loops. This is most useful while sifting through logfiles. Rename the "Kick Helper Funct" button to "Sweep L1 Helper". Now also check Tick and Turn Time Zone Shift during SCT Initialize (only if "include L1 Scalers" Option is selected), still no L1 Scaler Increment (or L2 Scaler Count) checked during SCT Initialize. Add checking of Tick and Turn Time Zone Shift to button "Verify All Again". Create a TesterL1fwCardTickTurn object to reset/synchronize the Tick and Turn Scalers using the proper method to talk to the L1 Helper which has already been placed in test mode by SCT Initialize. Note that all Scaler reset actions taken while calling the L1/L2fwCardXYZ are NOT effective because the L1 Helper is already in test mode. This is actually a positive side effect; moreover no effort is made to reset any scaler (except TTN) during SCT Initialize, so that more bits of scaler counts can be explored. A COOR Initialize resets all scalers (but one at a time and not yet synchronously througout the whole system). Single Chance Test - L1FW : Shrink the height of the inter-Cards signals window invoked via the "Show All States" button so that it fits on 1024x768 display. Add "No L1 Fire on Pattern A" test option which is required when trying to test the Skip Next feature in order to be able to predict which L1fw cycle this signal will be asserted for. This mode will also be required to limit the number of L2 cycles to a maximum of one per loop of Single Chance Test. When the "No L1 Fire on Pattern A" test option is selected all TDMs are initialized (and never changed during the test loops) to obey the Global Source of De-Correlated Disable #3 which normally carries the COOR Pause/Resume signal. This signal still goes thru the Global Disable TRM card, and is thus under control of SCT. SCT initializes (and never changes during the test loops) this channel of the Global Disable TRM Card to be High for Pattern A (i.e. Disable is active) and Low on Pattern B (i.e. Disable is inactive) which is the mechanism used to guarantee no firing on Pattern A. This option additionally requests the SCT to initialize (and never change during the test loops) all 4 FOM++ channels that generate the L1 Fired Strobe signal to be 128-input OR gates. This is most crucial for L2fw SCT testing as more than one one L1 Strobe output is used to control the L2fw and these resources must always remain programmed in lockstep. This is enforced as a constant 128-input OR gate programming for simplicity. Add "Test Skip Next" test option to verify the operation of the Skip Next Crossing (in fact skip next two crossings). When the "Test Skip Next" option is NOT selected, all TDMs are initialized (and never changed during the test loops) to ignore the Global Source of Correlated Disable #3 which carries the Skip Next signal. When the "Test Skip Next" Option is selected all TDMs are initialized (and never changed during the test loops) to obey the Global Source of Correlated Disable #3 which carries the Skip Next signal. This option additionally requests the SCT to initialize (and never change during the test loops) all 4 FOM++ channels that generate the Skip Next signal to be 128-input OR gates. Trying to select or de-select these two new options when the apropriate conditions are not met generates a pop-up message listing the pre-requisites: "No L1 Fire on Pattern A" cannot be selected - unless the Global Disable TRM is included in the test "No L1 Fire on Pattern A" cannot be DE-selected - if there is any L2fw cards included in the test - or if the "Test Skip Next" Option is already selected "Test Skip Next" cannot be selected - unless the Global Disable TRM is included in the test - unless the FOM++ is included in the test Add a TesterL1fw object to split the actual testing code out of the Dlg_Single_Chance_Test which still handles the dialog box input/output. TesterL1fw uses Macros to implement the repetitive application of the same action to each one of the L1fw cards in the test. i.e. Initialize, ModifyProgramming, PredictCardOutput, VerifyAllCardOutputs, VerifyAonmProgr, DisplayLastChange, CaptureBaseCounts, and VerifyScalerIncrements. and also the more global operations like KickHelperFunction, CaptureTickTurnBase, ReadTickTurnIncrements, and CheckTimeZoneShift. The constructor to TesterL1fw also receives the state of the two new run time options "No L1 Fire on Pattern A" and "Test Skip Next" so that it can remember these flags and use them when needed (i.e. know whether to call CTesterL1fwCardTDM::AddSkipNext when needed). Some TesterL1fwCardXYZ objects also need to know the state of these flags, and the TesterL1fw constructor sets member variables in card objects after calling the card object constructors for the Global Disable TRM Card, the TDM Cards, and the FOM++ cards. The SCT Initialize sequence uses the class dependencies in the following way, and in this order: TesterL1fwCardXYZ::Initialize first calls L1fwCardXYZ::Initialize L1fwCardXYZ::Initialize first calls CardXYZ::Initialize. CardXYZ::Initialize first calls CardBase::Initialize (except CardFOM & CardAONM::Initialize which call CardAONMCommon::Initialize which in turn call CardBase::Initialize) CardBase::Initialize doesn't do much but display the card's name. CardXYZ::Initialize also calls FpgaVmeInt::Initialize FpgaVmeInt::Initialize clears interrupt enable masks, and Enable Fpga and card outputs CardXYZ::Initialize also calls FpgaSupport::Initialize (if present, i.e. not for FM) FpgaSupport::Initialize calls FpgaCommon::Initialize FpgaCommon::Initialize clears the Fpga CSR, and Scaler Reset Registers (if present) FpgaSupport::Initialize also sets up the BSF resources to default settings described elsewhere. CardXYZ::Initialize also calls each FpgaXYZ::Initialize FpgaXYZ::Initialize calls FpgaCommon::Initialize (cf. above) FpgaXYZ::Initialize also sets up resources in a generic way (e.g. HSRO, Tick History Control Register,...) CardXYZ::Initialize also overwrites default BSF programming if needed and if this is common to all cards of type XYZ L1fwCardXYZ::Initialize also overwrites default resource programming if needed while differentiating between each actual instance of this XYZ card type L1fwCardXYZ::Initialize also programs the card's triggering resources to the default-non-allocated initial programming described elsewhere L1fwCardXYZ::Initialize also resets the card's scalers. TesterL1fwCardXYZ::Initialize also overwrites default resource programming for SCT testing if necessary (also differentiating between each actual instance of this XYZ card type) TesterL1fwCardXYZ::Initialize also programs the card's triggering resources to the default-non-allocated initial programming described elsewhere. TesterL1fwCardXYZ::Initialize also resets the card's scalers, but only for the Tick and Turn Scaler Card (XYZ=TickTurn) I need to make a document with the final Initialized state of all cards after SCT Initialize Note that COOR invokes L1fwCardXYZ::Initialize in the same manner. Add a TesterL1fwCardFOMPP class specialized for FOM++ with the essential difference from the TesterL1fwCardFOM card that it is derived from L1fwCardFOMPP instead of L1fwCardFOM, and thus has access to the FOMPP specific registers to return the card to its non-FOM mode. Fix typo in TesterL1fwCardAONM.h in the size of the array of scalers; was using wrong constant KiTrmTotAoTermPerCard instead of KiAonmTotSpTrgPerCard (but the values were the same) Disable the ECL Output of the FOM++ (if included in the test) while changing the programming of the L1 Framework (to avoid clocking extra data in the L2fw L1 Fired TRMs). Also Disable the ECL Output of the FOM++ (if included in the test) before SCT Initialize which should cure the 200 ms L1 Strobe syndrome. Single Chance Test - L2FW : Add the L2fw internal inter-cards signals to TesterCardInterfaces.h This is where each card reads the predicted state of its inputs and writes its predicted outputs. Add Dump of L2fw inter-Cards signals to "Show All States" button. A separate window appears with the L2fw signals whenever any L2fw card is included in SCT. Add a TesterL2fw object to implement the repetitive application of the same action to each one of the L2fw cards in the test. i.e. Initialize, ModifyProgramming, PredictCardOutput, VerifyAllCardOutputs, VerifyAonmProgr, DisplayLastChange, VerifyScalerCounts, and SynchronizeScalerCounts. and also the more global operations like VerifyL2HelperWaiting, and ApproveL2Cycle. The constructor to TesterL2fw also receives the state of the new run time option "Test L2 Answer Fifo" so that it can remember this flag and use them when needed (not needed and option not yet implemented) Some TesterL2fwCardXYZ objects also need to know the state of this flag, and the TesterL2fw constructor will set this member variable after calling the card object constructors for the L2 Answer cards. In each SCT test loop, do all steps for L1 first, then for L2 (even twice if needed cf. below), instead of trying to inter-mix L1 and L2 during each step (modifying programming of L1 then L2, checking scalers of L1 then L2, checking outputs of L1 then L2). When the "Include L1 Scalers" option is selected SCT cycles the L2fw twice for every loop. This is because SCT kicks the L1 Helper twice to capture Scaler Increments, and thus two "events" end up clocked into the L2fw TRM Fifos. Unlike for the L1fw scalers where SCT can only predict their increment over a known number of crossing, SCT can predict the actual obsolute count of all L2fw scalers as the L2fw is only cycled under TCC control and NOT while SCT changes resource programming (which is the issue for L1FW). However since SCT does NOT reset scalers, SCT Initialize must now also go out and read the current count of those L2 scalers before starting the test loops. There is also a new button "ReSynch L2 Scal" to let SCT re-synchronize to the current counts after an error, and upon operator request. There is also a new "On Error" Option "ReSynch L2 Scalers" to automatically re-synchronize at the end of a test loop that recorded any kind of error. TesterL2fwCardAONM initializes all channels to the normal programming for the Accept/Reject type of card, i.e. require the L1 Sptrg Fired true and require the L2 SpTrg Answer true/false depending on the particular L2 Accept or Reject AONM card. Then during ModifyProgramming, one randomly picked channel will be selected and programmed to be "excluded (that is require all inputs true), but that channel will be returned to its normal programming first thing during the next loop. TesterL2fwCardFOM initializes all channels to obey only one input: the input with the same number. i.e. L2 Accept/Reject for GeoSect #N obeys L2 Accept/Reject for SpTrg #N and ignores all other inputs. TesterL2fwCardTRM initializes all channels of the L1 SpTrg Fired TRMs to normal Fifo mode and thus only copies the card's inputs to its outputs TesterL2fwCardTRM initializes all channels of the L2 Answer TRMs to use simulated data and initializes Pattern A to all zeroes, and will flip one randomly selected bit for each test loop. L2fw SCT only uses Pattern A, i.e. the maginot line is not used in the L2fw. TesterL2fwCardTRM initializes the Auxi L1 Data TRM, but does not ever modify the programming or check the output of this card. L2fw Auxi L1 Data TRM must be included in any L2fw SCT test in order to be able to initialize its FIFO which stimulates the L2 Helper. Add a member function to Dlg_Test_Card_Select so that Dlg_Test_Single_Chance can call back after the cards have been selected to find out if ANY L2fw card was included in the set of cards selected. In Dlg_Test_Single_Chance an internal flag lL2fwIncluded is updated with this information early in OnButtonInitialize. This flag is used throughout OnButtonInitialize and OnButtonGo before taking each action related to the L2fw; This includes: - during OnButtonInitialize: - Creating a TesterL2fw object, - SCT-initializing any L2fw card (including L2Helper), - Making the L1Helper cycle 4 times and each time checking the L2 Helper for a L2 Cycle waiting for Approval and then approving the L2 Cycle waiting for Approval. - Verifying all selected L2fw card outputs - Reading L2fw Scalers to synchronize internal starting value - during OnButtonGo: - Looking at the L2 Helper for a L2 Cycle waiting for approval during each loop after letting the L1 Helper sweep - Modifying programming of each L2fw card in the test every time there is a L2 Cycle waiting for Approval - Approving a L2 Cycle waiting for Approval - Verifying L2 Scalers (if "Include L2 Scalers" option selected) - Verifying all selected L2fw card outputs SCT Initialize knows to kick the L1 Helper and Approve L2 Cycles four times in order to clock in 4 known time slices in all L2fw card monitor registers. SCT Initialize also calls PredictCardOuput four times for each card in order to shift the same predicted output to all four time slices. This is only if at least 1x L2fw card is included, otherwise the L1 Helper is requested to sweep only once, and the L2 Helper is not touched. SCT knows if at least one L1 SpTrg Fired, and after the L1 Helper sweeps through its timing sequence SCT checks that the L2 Helper is indeed waiting for approval of a L2 cycle. SCT waits for L2 Helper to ask for "Approval Removal". SCT will display an error message if it had to wait more than ~150 us. The action triggered by the "Sweep L1 Helper" button also approves a L2 Cycle if there is one waiting, and update the expected card state and scaler ouput so that the button "Verify All Again" has a chance to work properly. SCT-Intialize initializes the L2 Helper AFTER all L2fw cards (while the L1 Helper is initialized BEFORE all l1fw cards). Internal: Rename Version.h to Trics_Version.h to try and get out of a weird behavior where Dev Studio did NOT re-compile source files depending on this header file after it was modified. This may be because it had been included in stdafx.h for a while. It didn't seem to help at first, but now it does??!! Declare the file name strings as static in L1FW_MasterCommandFiles.h so that this same file can be included in multiple source files without causing multiple definitions link errors. Modify CFpgaL1fwHelper::f_okSynchroScalerReset to use the proper method to pulse this Timing Signal depending on the L1 Helper Mode (Test vs. Normal). What mode it is is decided by looking at the apropriate bit last written to the control register. Cleanup and rename the constants for control register values in CFpgaL1fwHelper. -------------------------------------------------------------------------------- TRICS II Version 8.5 Release Notes ------------------------- 17-Mar-2000: 21-Apr-2000: (Rev 5) General: Add the Revision Number to the tag shown on every menu e.g. "V_8_5_1". The Logfile name will also include the revision number in the same format. Implement New Monitoring Server Request Protocol and Data Format, cf. below. Implement New COOR-like messages to Obey/Ignore all sources of Global Correlated, Global DeCorrelated, and Inidvidual Spec Trig Disable. Also Implement an Exposure Group Deallocate Message, but the associated action isn't yet functional. Also Update the templates in the "send L1FW message" menu. Drop all D0me code. All ITC now. Add implicit SCL Intialize to the actions associated with a COOR Start_Run message. At the moment this is the only action taken for a COOR Start_Run message. Intialize the Skip Next N Crossing Comparator #0 with a count of 18 for a 2.6 us minimum gap between L1 Accepts, i.e. ~20 Beam X. This is FOM++ Channel #40, and Andor Input term #247 which should be required in veto for all SpTrg Andor Requirements. Coor Commands: New Commands : "L1FW_Expo_Group n Deallocate" Deallocate Exposure Group #n "L1FW_Spec_Trig n Obey_Correlated_Disable p" "L1FW_Spec_Trig n Obey_DeCorrelated_Disable p" "L1FW_Spec_Trig n Obey_Individual_Disable p" Obey the corresponding Global Correlated, Global DeCorrelated, and Inidvidual Spec Trig source of disable #p for Spec Trig #n. "L1FW_Spec_Trig -n Obey_Correlated_Disable p" "L1FW_Spec_Trig -n Obey_DeCorrelated_Disable p" "L1FW_Spec_Trig -n Obey_Individual_Disable p" Ignore the corresponding Spec Trig source of disable. Note: the sources of disable currently used, and the only sources of disable that the Spec Trig are listening to by default are: Global Correlated Disable #0 = Skip Next Beam Crossing Global DeCorrelated Disable #0 = COOR Pause/Resume Inidvidual Disable #0 = L3 Disable Master Command Files: Update the Master Command File menu to send a COOR message to initialize the frameworks instead of reproducing the same actions. Button Name Master Command File Name ----------- ------------------------ "Initialize L1&L2 Frameworks" -> %CONFIG%\\Init_Frameworks.mcf (send COOR message asking for FW Init) cf. www/hep/d0/ftp/tcc/trics_ii/button_mapping_master_command_files.txt for full list. This means the MCF framework initialize button uses a COOR message instead of independently doing the same thing as the COOR message. There is no functional difference, except that the COOR messages executes asynchronously. A 5 second wait was added to the MCF to let the informational messages related to initialization (going to the screen and in the logfile) precede the closure of the MCF file. Rework Master Command File Buttons - replace the two "Enable/Disable SpTr#0" buttons with two "Pause/Resume Run" buttons. - replace the Muon and Cal Setup 1 & 2 buttons with one button per sub-system: Muon, Cal, SVX The new files are called D0_Config\SpTrgNNN_XYZ_Setup.mcf and .msg Where XYZ is the subsystem and NNN is the SpTrg Number. The .mcf and .msg files associated use the following resources Muon Cal SVX SpTrg # 107 106 105 Expo Group # 7 6 5 Geo Sect # 56, 59 74, 77 102, 103 Andor Terms 255, 247 255, 247 255, 247 Prescale 7M 7M 7M - The following files have been modified to add AOIT #247 SpTrg0_Ao224.msg SpTrg0_Ao224_Ao251.msg SpTrg0_Ao251.msg SpTrg0_Init.msg Button Name Master Command File Name ----------- ------------------------ "SpTrg #107 Muon Setup" -> %CONFIG%\\SpTrg107_Muon_Setup.mcf "SpTrg #106 Cal Setup" -> %CONFIG%\\SpTrg106_Cal_Setup.mcf "SpTrg #105 SVX Setup" -> %CONFIG%\\SpTrg105_SVX_Setup.mcf "COOR Pause" -> %CONFIG%\\Coor_Pause.mcf "COOR Resume" -> %CONFIG%\\Coor_Resume.mcf Web file button_mapping_master_command_files.txt has been updated in http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/ Frameworks Initialization: Now Reset all scalers (TRM, AONM, TDM, FOM, FOM++) upon initialization. Also Reset all TDM scalers upon Spec Trig Deallocate. Reorganize the initialization steps that used to be all in the classes L1/L2fwCardXYZ::Initialize. (TRM, AONM, TDM, FOM, FOM++, BAD, FMDlatch, L1Helper, L2Helper) Move all Initialization steps which are independent of Card ID (excluding resource programming) from L1/L2fwCardXYZ::Initialize down to CardXYZ::Initialize. Then Move the Main Array Initialization steps one level lower to FpgaXYZ::Initialize. Monitoring Server: The new-style Protocol is defined in Tcc_Monit_Data.hpp (request and content). The Monitoring Server now looks in the opaque message and if the data corresponds to a new-style request (for the only currently defined data type), is sends one block back. If the request does not look like a properly defined request, the Monitoring will (for a while) answer with one block of the format used in the earlier tests (for compatibility during switch over). The new-style data block is now made of a header and a payload. The new-style data block header contains a block type (wich uses the same code used in the request) and a version ID, currently set to 1. The new-style data block payload contains a snapshot of: The Tick and Turn scaler (the "Framework Time Zone" copy) Arrays of Spec Trig "Allocated" COOR and Spec Trig Fired (as before) Arrays of Andor Term "Used" by COOR and Andor Term Fired All scalers are now 64 bit wide except the Tick scaler which is 32 bit. A Spec Trig is considered "allocated" to COOR when a COOR message mapping the Spec Trigger to an exposure group has been received, and remains considered allocated until the next Spec Trig Deallocate message, or framework initialize message. An Andor Term is considered "used" when it has been listed in a list of andor terms either for an Exposure Group or for a Specific Trigger and remains considered used until the next framework initialize message. The monitoring server will now force a capture monitoring data every time it receives a new-style request. The long term goal is not well defined and may involve an asynchronous refresh every 5 seconds. The monitoring server returns zero in every data field until the frameworks have been initialized once. The Toy TrigMon program has been updated to display the new data, and display rates starting with the second refresh. Single Chance Test: Work in preparation for inclusion of L2FW in the test. Add L2FW cards in the menu to select the cards under test (these cards are not tested yet, even if selected). Also shrink the height of this window so that it fits on 1024x768 display. Add the Tick and Turn Scaler as a card (was just 2 TTN registers). The Tick and Turn Scalers are also now initialized by SCT. Drop the Slot selection for the L1FW Helper, use the defined site-dependent slot instead. (This avoids one of the two blue messages mentioned for V8.3) Rename the TesterCardXYZ objects used by SCT for L1FW tests to TesterL1fwCardXYZ. Internal: Create Macros for the common button actions of all Menu Dialogs in file Dlg_Generic_Macros.h. DLG_FILE_BROWSE_IMPL for Browsing directories to find a file. DLG_EXEC_FILE_IMPL for executing a command file of some kind. DLG_DISPLAY_FILE_IMPL to display a generic file. DLG_SYNTAX_IMPL to display the syntax rules of a particular command file. Create Macro for the actions (onButtonXYZ) of the Master Command Files Menu. Cosmetic rename some of the constants related to L1FW card types in preparation inclusion of L2fw in SCT. Migrate the two Scaler Reset Registers from the FpgaXYZ class (TRM, AONM, TDM, FOM, FOM++) to their base FpgaCommon class. The FpgaCommon class has an Initialize method, and a ResetAllScalers method to reset all scalers of a the Fpga. Move "Version.h" out of the precompiled header file stdafx.h to make Version/Revision updating easier. -------------------------------------------------------------------------------- TRICS II Version 8.4 Release Notes ------------------------- 16-Mar-2000: (Rev 2) General: Only difference is to change default setup of all Specific Triggers to enable Individual Disable #0, i.e. L3 disable. -------------------------------------------------------------------------------- TRICS II Version 8.3 Release Notes ------------------------- 08-Mar-2000: 16-Mar-2000: (Rev 8) General: Update L1FW and L2FW card initialization and L2FW programming, cf. below. Create Fpga, Card, L1fwCard classes to initialize Tick and Turn Scaler. This has not been tested, so we still keep the TTN initialization in the init_auxi for the time being. In the Register IO menu, the "Refresh Monit Data" button now forces immediate capture monit data of both the L1FW and the L2FW. Found that the init_auxi RIO file resets the TTN scaler in a weird way, using test mode registers of the L1helper to force Synchronous Scaler Reset while the L1Helper is initialized to normal mode. This is a legacy from the first SCT test initialization RIO which hasn't been modified after its use as a L1fw Initialization. This may explain the occasional unexplained errors in SCT initialization, complaining about the difference in TTN scaler counts not being 26. Master Command Files: MCF menu button label renamed from "L1FW Configure" to "Configure L1&L2 Frameworks" and from "L1FW Initialize" to "Initialize L1&L2 Frameworks" Update the Master Command File menu to add buttons to execute specific command files to support current commissioning effort. Button Name Master Command File Name ----------- ------------------------ "SpTrg #0 Muon Setup 1" -> %CONFIG%\\SpTrg0_Muon_Setup_1.mcf "SpTrg #0 Muon Setup 2" -> %CONFIG%\\SpTrg0_Muon_Setup_2.mcf "SpTrg #0 Cal Setup 1" -> %CONFIG%\\SpTrg0_Cal_Setup_1.mcf "SpTrg #0 Cal Setup 2" -> %CONFIG%\\SpTrg0_Cal_Setup_2.mcf "SpTrg #0 Enable" -> %CONFIG%\\SpTrg0_Enable.mcf "SpTrg #0 Deallocate" -> %CONFIG%\\SpTrg0_Deallocate.mcf cf. www/hep/d0/ftp/tcc/trics_ii/button_mapping_master_command_files.txt for full list. L1FW Initialization New card type for FOM++. Now Initialize L3 Transfer Number, and Skip Next N Beam Crossings Add call to ForceFifoResynch to L1fwCardTRM to force the Fifo error detection to "trip" and thus resynchronize (this is done before manually clearing errors). L2FW Initialization * Change Initialization of M123 FM DLatch (L1 Trig Number & L3 Transf Number) to receive 0xa430 instead of 0xa440 in the Timing Signal Select Register, i.e. send P1(12) to HQ(1) instead of LOW. * Change Initialization of M122 FM DLatch (L2 Fired) to receive 0x2430 instead of default 0x2440 in the Timing Signal Select Register, i.e. send P1(12) to HQ(1) instead of LOW. * Reset L2fwHelper State Engine at initialization. * Change Initialization of Auxiliary Data TRM and L1 Fired TRM to skip Fifo full and Fifo empty error checking. This may only be temporary (?). * Add ForceFifoCounterReset to FpgaTRM, CardTRM, and L2fwCardTRM to help start the Read and Write Fifo Counters for all L2fw TRMs. * Change Initialization of all L2fw TRM cards Main Array Fpga CSR registers to receive 0x0021 instead of 0x0020, i.e. Enable sending VME Interrupts to VMEint FPGA (while the VMEint Fpga may/does not pass the interrupt to the VME Bus) * Change Initialization of all L2fw TRM cards VME Interface Fpga to enable all Main Array Fpgas in the Interrupt Enable Mask Register. These last two steps are executed at the end of the card's initialzation. (*) entries marked with a star show changes in the intialization steps described in l2_fw_setup.txt, trm_initialization.txt and bsf_fpga_programming.txt Change the order of initialization: Initialize all cards first Initialize L2fw Helper last, including State Engine Reset. Fix Initialization of all L2fw TRM cards to write all 1's in both Test Data Registers A&B so that the L2 Answer TRM defaults to Accepting all Specific Triggers by using the content of its Test Data Register A. L2FW Programming ExpoGroupGeoSectList Fix bug in BAD programming that was not updating the register content but overwriting it with the channel it was trying to add while losing any previous channel that may already have been enable in the same register. The effect was to only keep the highest intended channel enabled in each control register. Fix L2BAD programming that was only adding new GeoSect without removing previous ones (after they were no longer in any Expo Group). Note: COOR-TCC communication is missing an Expo Group Deallocate message to tell TCC it no longer uses an Expo Group so that TCC can remove those GeoSect from the list of the ones the L2FW listens to. Monitoring Data Server: Define the content of the the next phase of Monit Data Block. - drop the use of L2IOGEN, simply use C struct instead - add header with a data type and version number - add Tick and Turn Crossing Number and describe derivation of Rate from counts. - fix definition of int64 so that it works on NT/VC++ - make all scalers 64 bit wide - add an array of Andor Term Fired Counts - add an array of Andor Term Allocated i.e. Non-Zero if at least one SpTrg is using the AoTerm The new file is called Tcc_Monit_Data.hpp This new definition has been sent to Taka, but not yet implemented. Single Chance Test: New sanity checks in L1fwCardXXX cause two InternalError "blue messages" during SCT intialize, both of these messages should be ignored: - L1FwHelper: because this card is initialize from the address in the dialog box instead of via its Card ID. - FOM++: because this card is still tested as an FOM only in SCT. In fact SCT needed to start disabling FOM++ features to work since the FOM++ is now fully initialized (minus Miguels). The disabling of FOM++ features has to be done via the L2fw overall class since these registers are not part of the TesterTRMCard used by SCT. This means SCT is still requiring to have done L1fw intialize at least once after power up. Internal: Add function SynchroScalerReset to FpgaL1fwHelper and L1FwCardL1fwHelper to pulse the Scaler Reset timing signal. This will reset all scalers of the system that have been enabled for timing signal reset. This is currently used in the L2FW TRM ForceFifoCounterReset. In RegBase, add PulseBitsHigh (and PulseBitsLow) functions to toggle the state of some bit(s) First High then Low (and vice versa). Common VME Interface FPGA initialization now clears the Fpga Interrupt Enable Mask. And Clear the Fpga Configure Enable Mask (intentional overkill since this was already left cleared after Fpga Configuration). Add CaptureMonitData function to L2fwCardL2fwHelper. Added sanity check in L1fw/L2fwCardXXX to verify the class is used for a card ID that it is expecting. -------------------------------------------------------------------------------- TRICS II Version 8.2 Release Notes ------------------------- 03-Mar-2000 08-Mar-2000: (Rev 5) General: Continue with L2FW card initialization, cf. below. Start programming L2FW. Finish the Board Support Fpga initialization to match the file bsf_fpga_programming.txt on the web. Force-add Geographic Section #127 to all Exposure Group definitions. This is required in the L2fw to notice when at least one SpTrg has been accepted, and thus wake up L3. Start allowing Spec Triggers to listen to their - Exposure Group Andor Requirements - and L1 Front-End Busy requirement. L2FW Initialization: Fill in the classes for fpga, card, and l2fwcard for BAD, DLatchFM, L2FWHelper. Split off L1fwAONM, and TRM cards to start L2fwAONM and TRM. Note there is no reason to split the code for L2fwFOM as there are no difference in card handling, or initialization, so create a simple L2fwFOM file that simply #defines is as synonym to L1fwFOM. Find bug in l2fw.cpp that was skipping the L2 reject AONMs initialization. Add forgotten FM DLatch for L1 Trig Num and L3 Transf Num. L2FW Programming ExpoGroupGeoSectList when COOR defines the list of geographic sections associated with an exposure group, keep/rebuild a list of all geosect currently allocated, i.e. used by at least one ExpoGroup. Update the L2BAD programming to enable/disable the GeoSect according to the list above. SpecTrigExpoGroup Program the Accept and Reject FOMs just like the L1 Fired FOMs Program the L2 AONMs for Accept/Reject of this Spec Trig SpecTrigDeallocate/default initialized state Still missing removing/deprogramming the sptrg from the L2 resources, but since it won't fire at L1 it is not a disaster. Internal Create new enumerated type for L2 BAD EFeBusyCtrl = eFeBusyDisable/eFeBusyEnable/eFeBusyForceHigh FpgaBAD has a function to enable/disable/force a given channel FpgaFOMPP only has the registers that do not exist on an FOM L2fwCardL2fwHelper has a function to force L2fw Capture Monit Data Start create new card type for FOM++. Not filled in, not used yet. -------------------------------------------------------------------------------- TRICS II Version 8.1 Release Notes ------------------------- 02-Mar-2000 07-Mar-2000: (Rev 3) General: Make Monitoring Server actually send SpTrg Fired counts, cf. below. Taka's monitoring system can display these numbers. Fix Coor_Access, Remote_Console, and Toy TrgMon clients to be able to connect to a remote node (e.g. d0tcc1). Start Adding the L2FW card initialization, cf. below. (still no L2FW programming). Update the class for the Board Support Fpga to match the updated design. A lot of registers have been dropped since the development design used to study HSRO (to control special modes and view the operation of the HSRO), and start default initialization of the card's BSF but hold back on serious changes, as the per card specific modifications do not yet exist on this version. L2FW Initialization: Add a L2fwCardAddress to list which cards exists, and give their slot coordinates. Add a L2fw class with all L2fw cards, including the L1 Fired TRMs (which were considered part of L1fw before) and the L3 Transfer number FMLatch which are both in M123_bottom. Initialize L2fw TRMs according to the trm_initialization.txt on the web. Create classes for fpga, card, and l2fwcard for BAD, DLatchFM, L2FWHelper, mostly empty of real action, but placeholder of things to come. Monit Data Server: The Monit Data Server now sends current data. The Monit Data Server simply reads the scalers every time the client asks for a new block. It does not cause a manual capture monit data. If a SpTrg is firing, the monitoring information is already updating with every L1 Accept (at the moment via Init_auxi). Internal: Add "#ifndef __xxxxx__" to nearly every header file to prevent double definition. This could be/was avoided, theoretically, with effort, but it is a standard thing to do, when handling a large number of files. Tune up the name of Fpga register description constants to include the type of the Fpga in the beginnning of the name (e.g. KiAonmRegAddrProgrinfoBase) to avoid conflict and/or confusion. Add a GetSpTrgFired function to the L1fw object as a quick way to get Monit Server going. -------------------------------------------------------------------------------- TRICS II Version 8.0 Release Notes ------------------------- 11-Feb-2000 01-Mar-2000: (Rev 0) General: Switch Client Server Messaging from D0me to ITC Also convert Coor_Access, Remote_Console clients to ITC. (but for the moment only connect to the "local" node). Add a new Server (on IP Port #52162) for the prototype of a Monitoring Server. cf. below. Create a Toy TrgMon to view the data sent by TCC. Typing gets a new block, and display a list of SpTrg Fired Counts for all SpTrg Allocated. Monit Data Server: First prototype waits for an ITC "Opaque message", and sends one Opaque Message back with monitoring data consisting of an array of "SpTrg Allocated" booleans (i.e. flagging the SpTrg used by COOR) and an array of "SpTrg Fired" 32 bit Counts. There is only one type of information sent at the moment, and TCC does not look inside the request message at the moment. The data sent is test data, claiming that only SpTrg #5 is allocated, and incrementing all SpTrg Fired counts by one every time the client asks for a new block. We tried using L2IOGEN to build a data class for the description of and access to the content. It turns out that Taka's client does not really benefit from IOGEN's features, as he has a C++ layer that only receives the messages, and then re-package it up to hand over to Python. We can drop using IOGEN for this purpose as it is extra work, and causes one extra memory copy. In the future, a C struct declaration will fit the needs. The IOGENerated files are MonTest_L1fwData and MonTest_L1fwIO (.hpp and .cpp) and MonTest.hpp to define new data types. Internal: HandleD0meClient, HandleD0meServer are now obsolete, but still there and there is a pair of compile-time switch TRICS_MSG_USE_ITC/TRICS_MSG_USE_D0ME that tell VC to use ITC. We can get rid of these files once we are sure we don't want to go back. HandleItcClient, HandleItcServer are the new files CommandFileSelfMsg, HandleCoorConnection, and HandleRemoteConsole had to be switched to ITC (using the compile-time switch). D0mePortNumber.h now called IpPortNumber.h -------------------------------------------------------------------------------- TRICS II Version 7.2 Release Notes ------------------------- 23-Feb-2000: (Rev 5) General: Update the initialized state of the sytem, see below. The state of the initialization of SCT has not changed. A few more Coor Commands now available, see below for list. Fix weakness: keep low the AONM/FOM CSR bit which allow programming of the lookup memories except for when the memory is actually written Update Environment Variable %CNX% to point to \Trics\D0_Cnx at Fermilab and \Trics\MSU_Cnx at MSU. cf. http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/environment_variables.txt for full set of defined Environment Variables. Initialization: See the following file for complete description. http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/trics_ii_initialization.txt Highlight of changes are: AOIT TRM: initialize AOIT TRM error checking registers Enable all FIFO error checking, but DO NOT enable automatic error clearing (i.e. errors remain stored in Error Reporting Register until TCC manually clears them) Clear any initial errors in the Error Reporting Register by pulsing the corresponding control bit for > 21 us. AONM: Fix oversight that was preventing advertized initialization of AONMs TDM: enable correlated disable #3 i.e. skip next crossing enable de-correlated disable #3 i.e. Global Disable / Coor Pause All Cards: initialize all FPGA CSR Reg 0 with 0x0000 to disable interrupts. Coor Commands: Current Coor Command implementation status (V7.2 changes noted with a "*"): L1FW_Configure Done Initialize Done SCL_Initialize Done Start/Stop Run Not Implemented (informational message) Pause/Resume Run Not Implemented (informational message) Begin/End Store Not Implemented (informational message) L1FW Pause/Resume Done ExpoGroupAndOrList Done ExpoGroupGeoSectList Done SpecTrigAndOrList Done SpecTrigL1Qualifier Not Implemented ** SpecTrigExpoGroup Done ** SpecTrigCoorEnable Done * SpecTrigObeyFeBusy Done * SpecTrigAutoDisable Done (add implicit ReEnable) SpecTrigPrescale Done SpecTrigReEnable Done * SpecTrigDeallocate Done (reinitialize the SpTrg TDM Fpga and reprogram AONM, FOM, FOM++) **: Now program the FOM++ Skip Next One BeamX Fpgas and skip N BeamX Fpgas. Still not listening to Exp Group Andor Input nor Exp Group FrontEnd Busy. (This is intentional, code exists, but commented out by choice). (Note: We can manually enable Exp Group Front-End Busy for tests by using an explicit SpecTrigObeyFeBusy command) Still incomplete programming of FOM++. Only Programmed as an FOM, any FOM++ specific registers need to be programmed via the init_auxi files. Connectivity Test: Fix truncation of connection description tags displayed on screen (and in logfile) when an error is detected. Multiline descriptions were truncated after about 132 characters of payload. This fix is done by using new HandleConsole::WriteMultiLine function. Internal: Fix bugs in controlling the various bits of TDM disable control register 81 where some other bit states could have been lost during Sptrg programming (I don't think it actually ever happened the way we are using it). Also remove the control of the now obsolete bits of reg 82 to enable the front-end busy inputs and adjust its ReadMask. Move SpTrg Initialize detailed actions from L1fwCardTDM to an FpgaTDM member function Use existing compile-constants instead of hardcoded values in the math to compute the proper card indices in CoorCommandExecuter. Fix bug partially blakning out the acknowledgement message to Coor auto_disable messages. Add set of member functions to control the Error Checking Control of the TRM Fpgas. Waiting on directives for TRM initialize actions. Adjust the card dependent read/write masks for all Fpga lower CSR (Reg 0). Add a WriteMultiLine function to HandleConsole that looks for "\n" in the input string and calls WriteLine and WriteMultiLine recursively. -------------------------------------------------------------------------------- TRICS II Version 7.1 Release Notes ------------------------- 27-Jan-2000: (Rev 4) General: Update the initialized state of the sytem, see below. The state of the initialization of SCT has not changed. A few more Coor Commands now available, see below for list. There are enough commands implemented to let COOR program and control specific triggers and geographic setions and generate L1 Accepts. Register IO: Add a "Refresh Monit Data" now button in Register IO menu (clicking on that button also automatically re-reads the selected register) Master Command Files: MCF menu button label renamed from "Download L1FW" to "L1FW Configure". Initialization: See the following file for details. http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/trics_ii_initialization.txt Highlight of changes are: All AONM's AndOr Term #255 required Low (while guaranteed DC-High) The result is: output low L1FW Helper Function Sets Helper in "normal" (vs. "test") mode. Initialize the TS Channel control registers for normal operation. FOM++: Still No special initialization of FOM++ beyond normal FOM registers. Coor Commands: There is a new set of COOR commands L1FW_Pause/Resume and the old Pause/Resume commands were renamed to Pause_Run/Resume_Run Current Coor Command implementation status (V7.1 changes noted with a "*"): L1FW_Configure Done Initialize Done SCL_Initialize Done Start/Stop Run Not Implemented (informational message) * Pause/Resume Run Not Implemented (informational message) Begin/End Store Not Implemented (informational message) * L1FW Pause/Resume Done * ExpoGroupAndOrList Done * ExpoGroupGeoSectList Done SpecTrigAndOrList Done SpecTrigL1Qualifier Not Implemented ** SpecTrigExpoGroup Done (but still not actually listening to Expo Group Andor Input or Front-End Busy) SpecTrigCoorEnable Done SpecTrigObeyFeBusy Not Implemented SpecTrigAutoDisable Done SpecTrigPrescale Done SpecTrigReEnable Done SpecTrigDeallocate Not Implemented Programming of AONM and FOM cards are surrounded by "Micro-pause/resume" to prevent affecting the trigger operation during programming. **: still minimal programming of FOM++ during SpecTrigExpoGroup programming : Only Programmed to generate the 4x global L1 Accept signals. Internal: Add Card IDs for L1Fw Helper Function FM Card and Tick/Turn Scaler Card. The L1fw helper function is now treated as a real card and fully initialized and controlled by SCT and L1FW_Init. Rename FpgaHelperFunction to FpgaL1fwHelper and upgrade content Rename CardHelperFunction to CardL1fwHelper and upgrade content Add L1fwCardL1fwHelper, TesterCardL1fwHelper Note that HSRO test was NOT updated to actually use the new functions, but is still writing directly to registers, and is outdated. Add "Unspecified" to enumerated type EIgnoreObey in CustomDataTypes.h This is to make the programming of FOMs more similar to AONMs where the terms not specified are set to "dont_care". In FpgaAonmCommon::f_okPreProgOneOutputAllInput, treat "Unspecified" as equivalent to "Ignore" in programming FOMs. Find bug in GlobalConstants.h that was setting KiL1fwTotSpTrg to 8*64. This error had no effect until I used this upper limit in a loop control. In L1fw.cpp link all cards in a single chain, as opposed to SCT which links each card type separately to check for existence of each species. This single chain will help future scanning of the card set to look for a particular register address. In L1fw.cpp initialize new member variables to hold trigger programming. L1FW_Init used to (like SCT) verify the state of all outputs since it was controlling TRM inputs during initialize. Not any more. We can later restore some kind of sanity checking, but it wouldn't be exactly like SCT. -------------------------------------------------------------------------------- TRICS II Version 7.0 Release Notes ------------------------- 14-Jan-2000: (Rev 3) General: Update the initialization state of the sytem, see below. The state of the initialization of SCT has not changed. Subset of Coor Commands now available, see below for list. Add a new type of command file for Trics to send commands to itself. At the moment we only have COOR L1FW commands. cf. www/hep/d0/ftp/tcc/trics_ii/syntax_rules_self_message.msg A Master Command file can execute such a file using "Call_Self_Msg:" cf. www/hep/d0/ftp/tcc/trics_ii/syntax_rules_master_command_files.mcf Add a dialog box menu for these L1FW messages and command files. Radio buttons provide a template of the syntax for each message type. Update the Master Command File menu to add buttons to execute specific command files to support current commissioning effort. Button Name Master Command File Name ----------- ------------------------ "SpTrg #0 Init (Disabled)" -> %CONFIG%\\SpTrg0_Init.mcf "SpTrg #0 AO(224) &Enable" -> %CONFIG%\\SpTrg0_Ao224.mcf "SpTrg #0 AO(251) &Enable" -> %CONFIG%\\SpTrg0_Ao251.mcf "SpTrg #0 AO(224&251) &Enable" -> %CONFIG%\\SpTrg0_Ao224_Ao251.mcf "SpTrg #0 Presc(7M) &Enable" -> %CONFIG%\\SpTrg0_Presc_7M.mcf "SpTrg #0 Presc(48k) &Enable" -> %CONFIG%\\SpTrg0_Presc_48k.mcf "SpTrg #0 AutoDis &Enable" -> %CONFIG%\\SpTrg0_AutoDis.mcf "SpTrg #0 Disable" -> %CONFIG%\\SpTrg0_Disable.mcf "UnNamed 0" -> %CONFIG%\\UnNamed_0.mcf "UnNamed 1" -> %CONFIG%\\UnNamed_1.mcf "UnNamed 2" -> %CONFIG%\\UnNamed_2.mcf cf. www/hep/d0/ftp/tcc/trics_ii/button_mapping_master_command_files.txt for full list. Update all syntax_rules_xxxxxxxxxxxxxxx.yyy files to describe the "MilliSecond_Sleep:" keyword and syntax that was added in V6.2. Initialization: See the following file for details. http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/trics_ii_initialization.txt Highlight are: AndOr TRM's normal fifo input mode except for Andor Terms 224:255 set to Bypass fifo mode All other TRM's bypass fifo mode All AONM's Ignore all And-Or Terms (Don't Care) except for AndOr Term #255 required High (while guaranteed DC-low) The result is: output low Initialize all Spec Trig - to enable both andor inputs - to disable all Exp Group Enable and Front-End Busy Inputs - to disable all source of disable, prescaler, and Auto-disable - to be disabled (by COOR) The result is: output low All FOM's, FOM++ All Outputs listen to NONE of the inputs The result is: output low Coor Commands: Implement SpTrg Prescale and Re-Enable action routines in CardTDM/FPGATDM. There is an algorithm to pick the "optimal" combination of number of bits to load the circ shift register with and an AfterBurner Ratio. The combination that comes closest to the desired ratio is picked, after rejecting choices that would cause a cyclic pattern locked onto a subset of the bunches (i.e. AfterBurner has to be prime with 159, i.e. 3 and 53). There is a prepared table of Circ Shift Bit Patterns with (as much as possible) evenly spaced which bits are on. Current Coor Command implementation status: L1FW_Configure Done Initialize Done SCL_Initialize Done Start/Stop Run Not Implemented Pause/Resume Not Implemented Begin/End Store Not Implemented ExpoGroupAndOrList Not Implemented ExpoGroupGeoSectList Not Implemented SpecTrigAndOrList Done SpecTrigL1Qualifier Not Implemented SpecTrigExpoGroup Not Implemented SpecTrigCoorEnable Done SpecTrigObeyFeBusy Not Implemented SpecTrigAutoDisable Done SpecTrigPrescale Done SpecTrigReEnable Done SpecTrigDeallocate Not Implemented Internal: HandleCommandFiles: change default flag for the Open and Close file Hooks from Illegal Keyword to NULL so that particular command file types can chose to override it, but don't have to if they don't do anything. Add keywords "Call_Self_Msg:" and "Coor_L1fw_Msg:" New HandleD0meClient.cpp to create a client D0me connection. A static pointer and static functions are available to handle the connection to the COOR command D0me port. Remove the virtual qualifier from the base card, fpga, etc, destructors Create a new classes L1FWCardXXXX that implements the generic funcionality formely in TesterCardXXXX that now derives from these classes. The L1FW object uses the L1FWCard base classes while SCT uses the TesterCard derived classes. Add a utility to UtilStrings to convert floating point number to a string with specified number of digits after the decimal point. Implement a Card/FpgaTRM::f_okSetNormalMode and f_okSetBypassMode Calculate the maximum prescaler ratio (cf. CoorCommand.h), but define it as one count short as the prescaler picking algorithm doesn't work for the max count. -------------------------------------------------------------------------------- TRICS II Version 6.2 Release Notes ------------------------- 4-Nov-1999: 18-Nov-1999: General: Defines the new environment variables: logical MSU target D0 target ------- ---------- --------- CONFIG MSU_CONFIG D0_CONFIG (sorry, I forgot to warn you!) L1FW_RND MSU_L1FW_RND D0_L1FW_RND L1FW_CNX MSU_L1FW_CNX D0_L1FW_CNX The old environment variables RND, CNX, and MSU_CNX are still defined at the moment and will be removed once we are happy with the conversion (to be determined). Log files go to D0_Log or MSU_Log depending on the site. No environment variable is needed here. Add a new time delay keyword, valid in all types of command files: "MilliSecond_Sleep:" where execution of the command file is suspended for the specified number of milliseconds (integer only). Add initialization of the G-Link Control register of the Board Support Fpga of all SCT-Tested Cards, and MCF-Initialized Cards. Parse and reply to all COOR messages directed to the L1FW. No action taken except for the 2 commands specified below. Update documentation on the web at http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/ 000_trics_ii_release_notes.txt This file of release notes. syntax_rules_*****.*** Syntax rules for each command file type. environment_variables.txt Logical names available in command files. button_mapping_master_command_files.txt Which MCF files gets executed. Download FPGAs: Handles 4036XLA S-Record files: 0x19682 byte stream VME IO: Add control options in VME IO dialog to control the VME Address Modifier to allow Supervisory vs Non-Priviledged and Program vs Data Access Mode (block mode is still not supported) Modes Number Implemented Address All Defined Modes in Trics Bits N 3F 24 Standard supervisory block transfer Y 3E 24 Standard supervisory program access Y 3D 24 Standard supervisory data access N 3B 24 Standard non-privileged block transfer Y 3A 24 Standard non-privileged program access Y 39 24 Standard non-privileged data access Y 2D 16 Short supervisory access Y 29 16 Short non-privileged access 10 - 1F undefined User defined N 0F 32 Extended supervisory block transfer Y 0E 32 Extended supervisory program access Y 0D 32 Extended supervisory data access N 0B 32 Extended non-privileged block transfer Y 0A 32 Extended non-privileged program access Y 09 32 Extended non-privileged data access don't care state 3 IACK cycle (uses A01-A03) Note: The access mode for THE Card Registers is Supervisor Data Access Coor Commands: Add a new D0me Server for Coor access on port #52160 The only 2 messages that are connected to some code are - the Spec Trig Coor Enable/Disable message. - the Spec Trig list of And/Or Terms. The idea is that this can support a minimal interface for Coor to "control" a run. The Master Command File Init L1FW must have been run (manually) before sending these message, and also the start SpTrg #0 MCF. I have a program that can send COOR messages to TCC. High Speed Readout Test: Undo what was done in V6.1 to return the Helper Function for the HSRO test to slot #2 of the crate holding the cards with the HSRO modules tested. Only the L1fw helper function was split/moved as referenced in V6.1 while the HSRO helper function stayed in crate 0/0. Note that the HSRO test only applies to the MSU testrack site. Single Chance Test: Override SCT random programming of the TDM to ignore anything coming on Correlated Global Disable #3, a.k.a Skip Next Beam X. This is a temporary measure until SCT can properly deal with this history dependent behavior. Internal: CBit3Adaptor61x constructor now accepts two more parameters to control the "Privilege" (Supervisory vs Non-Priviledged) and "Type" (Program vs Data Access) HandleD0meServer/D0meServerThread and /D0meProcessor constructor now have a parameter to specify an optional message consumer (unused for Remote Console, but used for COOR Access). Move the pointer to the L1fw from dlg_master_command_files.cpp to a static variable in the CL1fw class create an intialization member function in the CFpgaVmeInt and CFpgaSupport Classes Add preprocessor directives to avoid redefinition in HandleConsole.h in case it is included multiple times. Extensive rework of the HandleD0meServer Class. Make HandleD0meServer.h independent of the Dome, Thread_Util and Ace definitions so that modules which include this file to create a new D0me channel do not have to be compiled separately with all the necessary directories for include files. Try various methods to exit all threads and allow the program to terminate when the exit button is pushed. No success. Tried calling the cancel, cancel_all, kill and kill_all ace methods with no success. Rework the VC++ Trics_II project to add separate configurations depending on what Ace library is requested: MFC or no MFC and run time DLL or no DLL. Fix bug in HandleSRecordFiles that made itself seen with the new length of the 4036XLA: the minimum number of items on the line was tested as < 5 instead of <= 5. -------------------------------------------------------------------------------- TRICS II Version 6.1 Release Notes ------------------------- 30-Aug-1999: 17-Sep-1999: General: Add new sub-dialog to invoke Master Command Files with additional buttons connected to special MCF files to download, initialize the FW, initialize the SCL, etc. (cf the documentation available from within that menu) The "Initialize L1FW" button duplicates the initialiation steps of the Single Chance Test. This means that it puts the TRMs in Test mode and programs the TRM test patterns, then all the resources on the AONM, TDM, FOM to a known state, then kick the helper function and verifies that the data readout matches the predicted output. New Environment variable %CONFIG% for \Trics\Config New Environment variable %DCF% for \Trics\Dcf Download Fpga now takes explicit control of the board level CSR Interrupt Enable bit (set Low) JTAG Controller Enable bit (set High) JTAG Controller Active bit (set High) Previously, the state of these lines was not forced until after the first FPGA download (but was thus under control for a second download). The rest of the CSR bits were already under control Main Signal Array Fpga Output Enable (set Low) Boar Support Function Fpga Output Enable (set Low) Add a New type of Command File: Master Command File The role of this command file is to be able to call any type of specific command files. At the moment no other action besides calling command files of other types (or calling other MCF) are defined for the Master Command Files. High Speed Readout Test: Cosmetic change of Dialog Box of HSRO test: add reminder of slot numbers of cards to test. Location of helper function now follows site dependent. It used to be a fixed slot in the same crate as the cards under test as selected in the dialog box. Single Chance Test: Make set of cards displayed in single chance test automatically follow site dependent information. That is done in Dlg_Test_Card_Select by disabling the buttons of the cards that don't exist. Upgrade to the new Tick and Turn Scaler Type. Read both the L1 Time Zone and the Geo Sect Time Zone Scalers Also check (at each loop) that the count difference remains 26. Also fix leak: delete those scaler objects along with other cards All Command File Handling (except CNX): (Reg IO, VME IO, CBUS IO, Download FPGA) Pull the command file handling code out of the Dialog Box Handling classes and into their own CommandFilexxxx files. But without losing the ability to make the controls of the dialog box move during the execution of the command file (e.g. show FPGA download) Having a dialog box to update is not required. This is necessary when the command files are invoked from a Master Command File which will thus not display the dialog box of the associated type \ (at least not for now). Download Command File: Also pull out the downloading of a set of Fpga from the dialog control class into HandleDownloadFpga. Now downloading of Fpgas uses the following hierchichal structure Dlg_IO_Load_Fpga or CommandFileDownloadFpga / HandleCommandFiles HandleDownloadFpga HandleSRecordFiles FpgaVmeInt Suppress some of the messages about file opened and number of records found. (in order to limit the number of messages painted on the screen for fpga download) Internal: Add Project Documentation to Workspace for all documentation files. Change FOM Card ID Tag from "...SpTrg..." to "...SpTrg_Fired..." Add an f_osBaseAddress to the CardBase Object to return "Master/Slave/Slot" Add an f_osBaseAddress to the FpgaBase Object to return "Mst/Slav/Slot/Chip" Add Keywords "Call_Download_Fpga" "Call_Reg_IO" "Call_Vme_IO" "Call_CBus_IO" to HandleCommandFile Add constants Ki_Exist_L1fw_xxxx for every card in L1fwCardAddresses to flag which cards exist at MSU vs D0 Add Class RegScaler16 for 16 bit registers (in fact unused) Add Class RegScalerTickTurn for the 8/32 bit Tick and Turn Scalers Add Class L1fw to regroup all the cards defined in Single Chance Test and provide member functions to Initialize the framework in a manner similar to the initialization of the Single Chance Test at the moment, but which will evolve into the official coor initialize. -------------------------------------------------------------------------------- TRICS II Version 6.0 Release Notes ------------------------- 16-Jul-1999: General: Add project Remote_Console in directory /RemCons to create client program to display TRICS' remote console using D0me port # 52161. IP port number 52160:52169 are reserved for TCC. Every screen message is copied to the remote console if one client is connected to the D0me server. The message is copied only to the last connection made. New HandleD0meServer: Class D0meProcessor with a dumb sinking message receiver Class D0meServerThread to create a D0meProcessor New HandleRemoteConsole: only two functions: Initialize the remote console by creating a D0meServer Thread Copy a message to the remote Console Trics_II.cpp always initialize the remote console with a D0me server waiting for a connection. -------------------------------------------------------------------------------- TRICS II Version 5.9 Release Notes ------------------------- 22-Jul-1999: 26-Jul-1999: General: Add Site Dependence for the address of all L1FW Cards in L1FWCardAddresses.h so that the Single Chance Test can run on the MSU Framework. Add Compile Constants to select MSU vs DZERO location (TRICS_SITE_MSU or TRICS_SITE_DZERO) Add Compile time message advertizing the choice of TRICS_IO_*** and TRICS_SITE_*** Single Chance Test: Make the Helper Function default location in the dialog box site dependent. Make the location of the Beam Crossing Tick and Turn site dependent. In VerifyScalerIncrements display the Tick and Turn Increments on Error. S-Record: Fix bug detected by the compiler where an un-initialized variable was used instead of the proper field. This code was not used in normal situations. -------------------------------------------------------------------------------- TRICS II Version 5.8 Release Notes ------------------------- 2-Jul-1999: 6-Jul-1999: 22-Jul-1999: General: Add another logical Bit3 Interface to handle access to L1CalTrig via an Ironics parallel IO card. Add MSU_CNX environment variable for test files special for MSU hardware configuration. Replace all file selection filter from ".xyz" to ".xyz*" in order to include for example all ".xyz_msu" New HandleCbusIo Class CCbusInterface with ReadPort and WritePort routines to handle the Ironics ports Class CCbusReg with ReadReg and WriteReg to perform CBUS Read/Write (and also a RegAddress function to return a formatterd string) New CBUS IO Menu To Read/Write a L1CT register via an ironics card for prallel IO with ability to run a command file (cf. /doc/syntax_rules_cbus_io.cio) VME IO Menu: Add Command files of VME IO with default extension *.vio cf. doc/synrax_rules_vme_io.vio for syntax rules High Speed Readout Test: 6-Jul-1999: Add explicit menu selection to pick master, Slave of Helper Function, and change default location.of helper function Test Random Register: 22-Jul-1999: Fix bug in rejecting non-existent registers that was not totally unwinding. There were two different bugs affecting both manual register range entry and command file entries Single Chance Test: Change default location of Helper Function -------------------------------------------------------------------------------- TRICS II Version 5.7 Release Notes ------------------------- 5-May-1999: 12-May-1999: 3-Jun-1999: General: Make the explicit VME IO menu maximally flexible including inverting data to help using the Ironics IO card VME IO Menu: Add selection of Address Space VME A16/A24/A32 and Dual Port Memory Add selection of access Mode: Memory Mapped vs Calls to Bit3 API Add Selection of Bit3 Model 617/618 Adapter Number Add option to flip the data content on write (for Ironics IO) VME Access: Replace HandleVMEAccess with HandleFrameworkAccess and HanldeBit3Adaptor61x HanldeBit3Adaptor61x is the only module that manipulates the Bit3 Interfaces a bit3 interface is now an object so that several logical interfaces can now be allocated onto the same (or different) physical interface with different mapping characteristics (e.g. A24 vs A32). Add option TRICS_IO_FAKE, similar to TRICS_IO_NONE in the sense that there are no attached framework, but instead of altogether skipping data access, bulk virtual space is allocated where the VME space would be memory mapped. This is useful to check for proper allocation/de-allocation. HandleFrameworkAccess is the module that calls the lower level routines to map card size chunks of VME space and Read/Write a VME Register. High Speed Readout Test: 12-May-1999: Add options to select between 16 and 20 bit G-Link modes (which doesn't change the data content, just the setup of the Support FPGA) Single Chance Test: 3-Jun-1999: Flip polority of signal to kick the helper function; was normally low and pulse high, and now is normally high and pulse low, so that the high state lasts longer than a few microseconds. -------------------------------------------------------------------------------- TRICS II Version 5.6 Release Notes ------------------------- 14-Apr-1999: 6-Jun-1999: VME Access: Add routines to specify data transfer size (in addition of the normal 16bit word THE card register access routines) VME IO Menu: Add selection of data transfer size D8/D16/D32 High Speed Readout Test: Make the data transfer size (D16 vs D32) for FIFO readout a menu option Add a dump of the first 32 longwordsof the buffer when an error is detected -------------------------------------------------------------------------------- TRICS II Version 5.5 Release Notes ------------------------- 10-Feb-1999: Handle VME Access: Add Interrupt Service Routines to catch Interface Error Interrupt VME Interrupts Programmed Interrupts With a flag set by the ISR when an error (e.g. VME Bus Error) was detected Add routine to check if remote VME crate is powered Register Base Class: Check the ISR flag after every Read and Write to detect remote bus errors. Card CSR: Remove explicit check of the Bit3 status to detect access failures after every IO because there is now an interrupt service routine to catch those and the read and write register routines can find out the ISR has been called High Speed Reaout Tests: Our test VRB was having problems with D32 VME accesses to readout the FIFO so we replaced the D32 accesses with two D16 accesses each. Random Register Test: Test register existence by writing a 0x0000 instead of 0xffff since 0xfff is the default value that would be returned when the register doesn't exist. -------------------------------------------------------------------------------- TRICS II Version 5.4 Release Notes ------------------------- 26-Jan-1999: No functional change except for the addition of the Logfile flood protection. This feature will stop copyint messages to the logfile after 5,000 messages closer than 0.1 second together in time. The flood will be declared over after a gap between messages greater than 1.0 second. All these parameters are settable in the file HanldeLogFile.cpp HandleVmeAccess.cpp was updated to use the new Bit3 Sofware Interface. We had Bit3 Windows NT support sofware Model 983 V1.1, and we now use V2.1. This software supports the Model 618 PCI-VME bus Adaptor with built-in Optical interface. -------------------------------------------------------------------------------- TRICS II Version 5.3 Release Notes ------------------------- 12-Jan-1999: General: Add LogFile Flood Prevention = stop recording after 5,000 messages generated less than .1 sec apart. Try one more (and only one more) Write Register attempt if the first write failed with a Post-Write Check Error. This includes, but is not limited to, the VME DTACK errors. Add a new "Set Random Seed" button item in the main menu dialog to call a sub-dialog and pick a new random number seed. Understand how to prevent the application to hang while the console is waiting during cursor select/copy actions: the console properties must just be changed to remove the "QuickEdit mode" Download Fpga: Add check boxes to set or clear Board CSR bits after Fpga Download: These bits can be either Set or Cleared, but will always be written to Enable Main Array Fpgas Output (default is set) Enable Board Support Function Fpga (default is set) Jtag Scan Path Controller Enable (default is set) Jtag Scan Path Controller Activate (default is set) Main Array ECL Output Enable (default is clear) Global Card Interrupt Enable (default is clear) These bits can be either clear or skipped, i.e. ignored VME Interface Fpga Reconfigured Flag (default is clear) VME Bus Error Flag (default is clear) Note that during a Download Command Files (.dcf) TRICS_II will behave the same way as for single Fpga Download and obey the same flags for ALL the fpgas downloaded by the command file. (the command files cannot change the state of these check boxes from one card to the next, and cannot initialize them either) Random Register Test: Use new random number generator routine to go past 2**15 registers. Add Button to cycle through all the registers in the test and verify their current content. (only the registers that have already been written to at least once, of course) Add Check Box Option to verify all registers on error. Fix bug that was preventing from defining some registers, running some loops, adding more registers and trying to run again. Change test value written into register when it is defined to verify its existence from 0xffff ot 0x0000 since the value returned by a non-existent register is 0xffff. Fix Loop number display past 2*31 (2 Gigaloops) which was displaying a negative number. Connectivity Test: Use new random number generator routine to go past 2**15 connections Internal: Add more functions to VMEIntFpga class to set/reset the Board CSR bits. Allow the RegBase ReadReg member Function to be called with no arguments, as the Last_Read member variable will hold the value read. Add Integer to string conversion routines to handle all combinations of signed and unsigned int and long. -------------------------------------------------------------------------------- TRICS II Version 5.2 Release Notes ------------------------- 24-Dec-1998: General: Improve the Single Chance Test: Now include all scalers on TRM, AONM, FOM, and TDM. Read Reference Scaler Increment from M123, Lower Backplane, Slot 19. Single Chance Test: For Every loop take _TWO_ new snapshots (i.e. kick Helper Function) to read a base count, and final count in order to compute a Scaler increment. (In other words: the scaler counts for Loop N are NOT used as base counts for Loop N+1). No longer truncate TRM, AONM, and FOM monitoring data to 0x0fff. Add TimeStamps at start, end, error, every 1,000 loops. Display Current and Base Count with Scaler Increment Error Message. Replace the "One More Chance" Button with 3 new buttons: "Verify All Again" = Re-Read, Predict and Verify all Card Scaler increments and all non-scaler monitoring data. (i.e. without kicking the Helper function and without changing the Scaler Base Sample) "Kick Helper Function" = Kick the helper function (without changing the Scaler Base Sample) note that this will expose the Pattern B for one more crossing and thus for example increment by one the scalers that would only increment on Pattern B "New Scaler Base" = Take current Monitoring data as Scaler Base Count (i.e. without kicking the Helper function) Add memberfunctions CaptureBaseCounts, PredictScalerIncrements, and VerifyScalerIncrements to TesterCardTRM/AONM/FOM/TDM Internal: Create Class FpgaTermScalers with the scalers common to the TRM, AONM, FOM Add new class RegScaler32 derived from RePair. With member functions ReadCurrent, StoreBaseCount, ReadIncrement. Add Functions AsciiTime and TimeStamp to UtilsStrings.cpp/h Add function SaveContent to class RegPair. -------------------------------------------------------------------------------- TRICS II Version 5.1 Release Notes ------------------------- 18-Dec-1998: General: Improve the Single Chance Test: Now all TDM inputs are programmed and used (still no scalers). Single Chance Test: Add FpgaTDM and CardTDM functions to control the Obey/Ignore control of all sources of disable. -------------------------------------------------------------------------------- TRICS II Version 5.0 Release Notes ------------------------- 10-Nov-1998: 15-Dec-1998: General: First Full Implementation of the Single Chance Test: This version exercize all the TRM, AONM, FOM, TDM cards, but the TDM only listens to its Physics And-Or Inputs. NO scalers are tested. The old single chance test is still temporarily available. Update Helper Function to the new version with 8 channels, etc. Single Chance Test: Create FpgaAONMCommon to cover both the AONM Card and FOM Fpga. Goal: The code is only written in one place and can handle either Fpga. FpgaAONM and FpgaFOM are derived from it. They are only a thin interface to modify the arguments a bit. Same thing for CardAONMCommon, CardAONM, CardFOM Add functions to CardTRM and FpgaTRM to set in simu mode, initialize, modify A/B bit pattern Connectivity Test Collapse TesterConXSrc.cpp/.h with the smaller TesterConXRcv.cpp/.h into the single TesterConX.cpp/.h High Speed Readout: No longer skip the first two words of transferred data. Move location of Support Function Crate from Master #0 to 1 (Slave # is still selected via dialog box) Internal: Move pre-processor constants (i.e. #define) from CustomDataTypes.h to new GlobalConstants.h and include both files in stdafx.cpp so that they become part of the VCC pre-compiled header. Add a new constructor to CardBase where you can give it a Card ID and it will retrieve the Card Address (i.e. VI Master, Slave, Slot) from L1FWCardAdresses.h This constructor will also fill the three new CardBase variables: SpecificCardCode, CardChannelOffset, and the string CardDescription, Add a contructor to each Card type to create a card using its card ID instead of its coordinates. Add functions ForceRegBits and ClearRegBits to RegBase Class Update random number generator to generate values up to 32-bit instead of the raw 15-bit (~30,000) limit of the rand system routine. -------------------------------------------------------------------------------- TRICS II Version 4.4 Release Notes ------------------------- 26-Oct-1998: 05-Nov-1998: General: - Create a logfile with a name including the current date so that an alphabetical listing will order the files in chronological order. e.g. TRICS_II_981026_V4_3.log;3 The files are created in the directory \Trics\Log. The (vms-style) version number is set to 1 for the first file created, and incremented for subsequent files. All information going to the console is copied to the log file. The latest entries are explicitely flushed to the logfile when a sub-menu is closed, when a test is completed and when a command file has been executed. - replace all command file name entry boxes with "Combo boxes", i.e. they now have a drop down list of the previously entered names - change directory structure for all trics support and command files. X:\TRICS \L1FW_CNX \L1FW_SCT \Card_Commiss \Test_Crate \CNX (holds files common to more than one test types) \internal \inter_cards \EXO (holds files common to more than one test types) \aonm \aonm_ct \bsf \helper_function \bigben \RND (holds files common to more than one test types) \RIO (holds files common to more than one test types) \LOG \DOC - The default directory offered when using the "Find..." file button of all sub-menus is no longer static (was \users\default). It now remembers the directory from which the last file was selected. The initial default directory is the base \trics directory - fix bug in CheckBit3Status function that was failing to properly report some (i.e. most) errors. Command Files: - fix command file reader so that the last command line does NOT have to end with a - implement symbols in command files: e.g. $Slot_AONM= 5 ... Slot: $Slot_AONM - shorten some keywords: card_slot -> slot to_card_slot -> to_slot register_address -> register to_register_address -> to_register chip_address -> chip to_chip_address -> to_chip the old syntax is still accepted - allow use of environment variable for path in included files (i.e. Call_File:) in command files. e.g. %EXO%\Aonm\aonm_5_1.exo. or %EXO%\Aonm_CT\aonmct_1_2.exo - IMPORTANT: the behavior of these path variables is to FIRST look for the requested file in the current default directory, and, if the file doesn't exist there, only LAST in the directory/directories specified by the environment variable. This might be useful to temporary override some official file, for example in a temporary scratch subdirectory. But this may also be a cause of confusion. - Yes, the environment variable can specify a "search list" of several directories. No, we are not planning on using this feature at the moment. - The following environment variables are created (or overwritten) by TRICS: TRICS= \\Trics CNX= \\Trics\\Cnx EXO= \\Trics\\Exo DOC= \\Trics\\Doc RND= \\Trics\\Rnd RIO= \\Trics\\Rio Note that the disk name is NOT included, which allows running on files from a remote node with a similar directory structure (e.g. running on msutcc using files on msul1a). - These environment variables are not case sensitive because the command file parser converts the strings to uppercase. Windows NT directory and file names are not case sensitive eiter. - environment variables cannot be changed from within a command file - any additional environment variable existing in the context of the executable before it is run is also accessible. e.g. %TEMP% Note: It also seems to be non-case-sensitive while the documentation suggests otherwise. Register IO: - Register IO menu: The value written to a register was already read back and verified; it is now also written back to the Data Read dialog box Tests: - Connectivity Test now offers a mode switch to pick its behavior when and error is encountered and after it has been reported: - ignore the erroneous value read and keep expecting the correct value - or adjust the expected value to match what was actually read - fix bug in verifying that a new source doesn't overlap with ones already defined. It was incorrectly complaining when a source register had several separate source masks even if they didn't overlap. - High Speed Readout Test now verifies the bit3 status in case of initialization or loop error (since VRB reads are not based on the trigger register IO routines which do this automatically on write error) - Random Register Test default command file types has changed .TST -> .RND Internal: - rename ConsoleAccess.h,cpp to HandleConsole.h,cpp - create HandleLogfile.h,cpp to create and manipulate logfiles - create HanldeSymbols.h, cpp to create and manipulate symbols and sets of symbols. -------------------------------------------------------------------------------- TRICS II Version 4.3 Release Notes ------------------------- 20-Oct-1998: - Register IO Menu: - Use the "full" WriteReg function instead of WriteOnly and thus verify the content of the register after a Write - Random Register Test: - Change behavior to reset the registers at beginning of test - and do NOT assume previous register content has been preserved i.e. power may have been turned off. - Connectivity Test Menu: - Default to a quiet mode when loading the .CNX File. - Do not assume previous register content is known at Start/Reset i.e. the power could have been turned off - Fix bug that prevented parsing of the "To_Card_Slot" Keyword - Hsro Test: - Allow for a variable number of G-Links in Test (with dialog box field) - The TRM cards being read out are expected in the following card slots: Trm #1 at Card Slot 3, #2 at slot 5, #3 at 13, and #4 at 15 - The VTM/VRB channels used must now start from chan #0 (was VRB chan #4) - All Tests: - Fix bug that was executing N+1 loops instead of the requested N loops. - All Command Files: (i.e. Reg IO, ConX, ...) - Add Keyword "Call_File:" This will open and read the specified file The context (i.e. keywords already defined in the calling file) will be passed to the called file Any context change made in the called file will NOT be propated back to the calling file - The former "Include_File:" Keyword is now OBSOLETE But is still accepted with its old behavior to handle existing files - Load Fpga Menu: - separate the dialog box status message field which is related to the execution of a .DCF download command file from the message field related to the download of a particular S-Record .EXO file to a (set of) Fpga(s) Internal: --------- - Separate Zeroing of registers from TesterConXSrc::GetReadyForTest and create new ZeroAllConX - Display line number of the calling file when encountering called file - fix bug that caused reading 4 times too many words out of the VRB during HSRO test. (The extra words were not actually checked.) - Add member variable and member function to base register to save its content. This is used by the connectivity test to keep track of expected values -------------------------------------------------------------------------------- TRICS II Version 4.2 Release Notes ------------------------- 14-Oct-1998: - No functional change - Move all source code (*.cpp and *.h) from the main directory to a new "/Src" sub-directory Also move the /res directory to become /Src/Res Also move the Trics_II.rc file into /Src -------------------------------------------------------------------------------- TRICS II Version 4.1 Release Notes ------------------------- 02-Oct-1998: - Activate Release Notes Button on Main Menu Internal: -------- - remove from argument list to FpgaBase (and RegBase) Constructor the link to the previous Fpga (RegBase), as it can be retrieved from the mother CardBase (FpgaBase) LastFpga (LastReg) member variable - no longer do a WriteOnly in ConX Test to avoid pre-write error - Add code (not yet used, not tested) to program andor terms in FpgaAonm - Reorder arugments to RegBase Constructor to have the Read/Write masks come before the init values, default values,... - Add FpgaCommon Class derived from FpgaBase which have the additionnal features of Main Array Fpgas. The VmeIntFpga is derived directly from the FpgaBase, all Main Array and Support Fpgas are derived from FpgaCommon. e.g. FpgaCommon has CSRlow and CSRHigh Registers - member variables of RegBase, FpgaBase and CardBase are now protected. - Add access privilege (i.e. "friends") to FpgaBase and CardBase so that RegBase can retrieve slot number, fpga address,... - Add access privilege (i.e. "friends") to FpgaBase and CardBase so that RegBase and FpgaBase can retrieve slot number, fpga address,... - create a few functions to access the values of ReadMask, WriteMask, PrevReg, VmeAddress, LastWrite, LastRead. - add AddToReadMask and AddToWriteMask routines to RegBase for use by Connectivity test - Add SetFlagVolatile to RegBase for FpgaAonm this is saying that the content of a Read/Write register may have changed without having written to it. - Rename RegPairCtrl to RegPair and no longer derive from RegBase, since it is made of two RegBase but isn't a register itself -------------------------------------------------------------------------------- TRICS II Version 4.0 Release Notes ------------------------- 25-Sep-1998: ------------ - Finish Porting the Play 5.0 functionality into Trics II - Register IO - Load FPGA - Card CSR (including new CSR bits) - Direct VME IO - Random Register Test (no more arbitrary size limit) - change/improve menu layout and consitency - consistent behavior of the data format Dec/Hex/Bin buttons - Random Register Test Command files use a syntax different from the old play syntax: The syntax was changed slightly from the Play program for consistency with the Connectivity Test File syntax Keywords and should now be replaced with Keywords and The obsolete syntax is still accepted for existing old files - Exiting and re-entering a particular menu will restore last user parameters Internal: -------- - reverse order of parameters in CardBase for consistency with RegBase, and to allow default value (i.e. make optional) for the PrevCard parameter in the case were the card is isolated, and not part of a linked chain. - fill the VmeAddress field of the fpgabase and cardbase objects - miscellaneous improvement and unifomization of menus, test loop control,.. - Add to fpgaVmeInt object functions to control Fpga download InitiateFpgaDownload Write_FPGA_Config TerminateFpgaDownload and EnableMainArrayFpgaOutput EnableSupportFpgaOutput - Also add functions to read/write the various Control/Status Registers GetBoardSpeciesID GetInterrupterID SetInterrupterID GetCSR SetCSR GetFpgaConfigEnable SetFpgaConfigEnable GetFpgaConfiguredMask GetFpgaIntEnable SetFpgaIntEnable GetFpgaStatus GetFpgaIntRequest SetFpgaIntRequest - modify RegBase::f_okWriteReg so that the first time it is called for a newly created register, it skips check/compare of the current register content to what was last written. The register is still read back/verified after being written. - add to RegPairCtrl functions to read/write the double registers f_okReadReg f_okWriteReg f_okWriteOnly - Create HandleSRecordFiles.cpp derived from Play's FPGA_Config_Files.cpp - Add member function WarningLine to ConsoleAccess to write brigth white - Make uniform the loop control handling of all tests, and status messages - Make uniform the banners displayed to the console when entering a sub-menu - Add initialization of the (existing)VmeAddress member variable of FpgaBase and CardBase - Add kewords register_start and register_count to HandleCommandFiles These keywords are no longer in the official syntax, but added for backwards compatibility -------------------------------------------------------------------------------- TRICS II Version 3.2 Release Notes ------------------------- 15-Sep-1998: ------------ High Speed Readout Test: ------------------------ - Add HSRO Test Option: - fill 1 or 2 of every seven G-Link Frames - add buffer number in error messages - when abort-on-error is selected, abort at first buffer error while sequentially checking all the buffers consecutively transferred. (instead of waiting for end of loop, after having checked all buffers) -------------------------------------------------------------------------------- TRICS II Version 3.1 Release Notes ------------------------- 11-Sep-1998: ------------ High Speed Readout Test: ------------------------ - Add HSRO Test Options: - control how many words/card are transferred - use the "pipelined" read ot f the VRB output FIFO - allow multiple HSRO consecutive transfers before checking the data - Check VRB Header fields, and skip data checking on error - Add Debug button to intentionnaly cause an exception and call the debugger - try to start with a "full reset" of the VRB (independently of the partial reset to set it up), but this causes great confusion, and most of the time makes the VRB totally unaccessible from VME. - Allow a variable number of G-Links (but only via compile constants) - move the mapping of the VRB to the initialization of the menu, instead of repeating this at every start of test. - clean up and modularize the various steps of VRB buffer transfer, and checking of buffer header, and buffer data. - improve byte swapping management. - explicit wait during each step of buffer transfer: input->buffer->output Porting Play's Functionality: ----------------------------- - start porting Load Fpga menus from Play 5.0 -------------------------------------------------------------------------------- TRICS II Version 3.0 Release Notes ------------------------- 27-Aug-4-Sep-1998: ------------ - Add High Speed Readout Test - Implement management Memory Mapped Access to VME space to allow access to any crate/card - Do not delete submenus objects when closed, and thus restore the environment when the same menu is called again - Drop powerPC support. - start porting Register IO and VME IO menus from Play 5.0 VME Access: ----------- - no longer use brute force memory mapping of the whole Vertical slave Space - map one memory segment per card - keep track of which cards have already been mapped - map a whole card, if necessary, any time a register is created. - split checkbit3status and clearbit3status routines from RegBase into HandleVmeAccess.cpp. - HandleVmeAccess.cpp now includes the former bit3 initialization steps from the now deleted mapvmespace.cpp - HandleVmeAccess.cpp now has routines to map and unmap memory segments, and - CRegBase now has ConvertToVmeOffset (derives chip+reg offset off of a card base address) and UnpackVmeAddress (to recover vertical, card, chip, register coordinates from a VME Address) Internal: -------- - add kknow registers to FpgaSupport - fix bug in HandleCommandFiles.cpp (initialize the return variable) that showed up for an application that didn't use the File_Opened hook. - split the common part of the different RegBase constructor into a common subroutine: BasicConstruct -------------------------------------------------------------------------------- TRICS II Version 2.1 Release Notes ------------------------- 14-Jul-1998: ------------ Single Chance Test ------------------ - Add Single Chance Test Options - select vertical slave number - select Test Pattern 0/F or 5/A - Select the number of AONM cards in the test - select whether the TRM or AONM readout should be truncated to 0x0fff - test extended to check andor decisions - modify the andor pattern from what is expected every 1 out of 3 loops -------------------------------------------------------------------------------- TRICS II Version 2.0 Release Notes ------------------------- 09-Jul-1998: ------------ - Add Single Chance Test - improve screen layout management: control position of sub menu created, and shrink main meny while a submenu is active. Internal: -------- - cleanup file names: - use Reg, Fpga, Card as Prefix instead of Postfix - use Utils as prefix (e.g. UtilsStrings.cpp, UtilsBits.cpp) - create new objects; - FpgaAonm, FpgaTrm, FpgaHelperFunctions - CardAonm, CardTrm, CardHelperFunctions -------------------------------------------------------------------------------- TRICS II Version 1.2 Release Notes ------------------------- 26-Jun-1998: ------------ - initialize the console position away from the left edge of the screen so that it doesn't overlap with the menus. Internal: -------- - Add a CConsole::ErrorLine routine to write a line in Red. - Add a CConsole::InternalErrorLine routine to write a line in Blue. - check for existence of a console before writing a line, and create one if it doesn't exist yet - add CConsoleAccess::GetConsoleHwnd to get a handle to the console window -------------------------------------------------------------------------------- TRICS II Version 1.1 Release Notes ------------------------- 19-Jun-1998: ------------ Connectivity Test: ------------------ - Add a Check-All button to check all connections after test (e.g. after abort-on-error) - Add resume/continue test (e.g. after abort-on-error) - add test option: beep-on-error (doesn't work properly) - check bit3 status on loop error - change all screen messages about source or receiver "mask" into "field" - detect register initialization errors and abort test on init errors VME Access: ----------- - modify CBaseRegister::f_okReadReg masks off bits not in the ReadMask before returning - modify CBaseRegister::f_okWriteReg first verify data is what was last written (only the bits that can be read back) and read back and check the new data - add CBaseRegister::f_okWriteOnly to just write the register; no checking - modify CBaseRegister::f_okReadReg, f_okWriteReg, and f_okWriteOnly to return an error when using API IO method - add CBaseRegister::f_okCheckBit3Status and f_okClearBit3Status -------------------------------------------------------------------------------- TRICS II Version 1.0 Release Notes ------------------------- 12-Jun-1998: ------------ - fix direct memory access that was broken in V0.1 (in BaseRegister.cpp) Connectivity Test: ------------------ - Add Stop on Error, check connection before modify, and variable number of extra connections checked - modify the way reciever expectations are updated only once per change (testerconxsrc.cpp) -------------------------------------------------------------------------------- TRICS II Version 0.1 Release Notes ------------------------- 28-MAY-1998: ------------ - Allow access to any Vertical Slave VME Access: ----------- - Add (and use) compile time option to use the Bit3 API for VME read/write instead of the direct memory mapping. Picking Memory Mapped Access or Bit3 API access is done with a preprocessor variable #define TRICS_IO_BIT3 for memory mapping #define TRICS_IO_BIT3_PIO for API calls (and #define TRICS_IO_NONE for no VME access, e.g. for Alpha environment) - switch handling of VME addresses from a word offset (used in pointer math) to the true VME address. The difference is a shift of one bit. - changed BaseRegister.cpp, mapvmespace.cpp and vmeio.h -------------------------------------------------------------------------------- TRICS II Version 0.0 Release Notes ------------------------- 15-APR-22-MAY-1998: ------------ - New Connectivity Test Internal: --------- - Create BaseRegister, BaseFpga, BaseCard, ... -------------------------------------------------------------------------------- 12345678901234567890123456789012345678901234567890123456789012345678901234567890 -------------------------------------------------------------------------------- TRICS II Version 5. Release Notes ------------------------- - -1998: ------------ General: -------- - Internal: -------- -------------------------------------------------------------------------------- 12345678901234567890123456789012345678901234567890123456789012345678901234567890 --------------------------------------------------------------------------------