Trigger Control Computer 
                Initialization of Cards in HSRO Crate 

Rev 8-MAR-2001, as of Trics V9.1 Rev I

The initialization steps happen in the following order.

I) Initialize each VRB
   one at a time, starting with lowest slot number, and in slot order.

   A24 Base Card Address is e.g. 0x130000 for VRB in Slot #19 
        etc. cf. http://www.pa.msu.edu/hep/d0/ftp/l1/framework/hsro/
        hsro_notes.txt

    a) Read Card ID
        A24/D16 at Address Offset 0x00  Read    all VRBs return 0x0003 

    b) Read Serial Number
        A24/D16 at Address Offset 0x06  Read    e.g. 0x0158 for VRB in Slot #19

    c) Read Date Code
        A24/D16 at Address Offset 0x04  Read    e.g. 0x0a25 for Slot #19, i.e. 25 Oct 2000

    d) Enable VRB Channels actually being used
        A24/D16 at Address Offset 0x70  Write   e.g. 0x00ff for VRB in Slot #19

    e) Set NO Gray Coding
        A24/D16 at Address Offset 0x76  Write   0x0000

    f) New VRB setup step to be added in next Revision of Trics 
       
       Prepare the list of starting addresses for 16x 2kB VRB buffers
       These addresses will be ingested at the next VRB Reset.

       Buffer #1  A24/D16 at Address Offset 0x0300  Write   0x0000
       Buffer #2  A24/D16 at Address Offset 0x0302  Write   0x0800
       Buffer #3  A24/D16 at Address Offset 0x0304  Write   0x1000
       Buffer #4  A24/D16 at Address Offset 0x0306  Write   0x1800
       Buffer #5  A24/D16 at Address Offset 0x0308  Write   0x2000
       Buffer #6  A24/D16 at Address Offset 0x030A  Write   0x2800
       Buffer #7  A24/D16 at Address Offset 0x030C  Write   0x3000
       Buffer #8  A24/D16 at Address Offset 0x030E  Write   0x3800
       Buffer #9  A24/D16 at Address Offset 0x0310  Write   0x4000
       Buffer #10 A24/D16 at Address Offset 0x0312  Write   0x4800
       Buffer #11 A24/D16 at Address Offset 0x0314  Write   0x5000
       Buffer #12 A24/D16 at Address Offset 0x0316  Write   0x5800
       Buffer #13 A24/D16 at Address Offset 0x0318  Write   0x6000
       Buffer #14 A24/D16 at Address Offset 0x031A  Write   0x6800
       Buffer #15 A24/D16 at Address Offset 0x031C  Write   0x7000            
       Buffer #16 A24/D16 at Address Offset 0x031E  Write   0x7800

    g) Write Vrb Header User Data
        A24/D16 at Address Offset 0x0E  Write   e.g. 0xb101 for VRB in Slot #19
        cf. http://www.pa.msu.edu/hep/d0/ftp/l1/framework/hsro/
        summary_of_fw_data_readout.txt

    h) Reset VRB and VTM
        A24/D16 at Address Offset 0x3C  Write   0x0001

    i) Wait 50 milliseconds

    j) Read Current Status 
        A24/D16 at Address Offset 0x38  Read    e.g. 0x0000

    k) Reset latched version of Current Status 
        A24/D16 at Address Offset 0x3A  Write   0x0000



II) Initialize the VRBC

   A24 Base Card Address is 0x480000
   A16 Base Card Address is 0xC000

    a) Read Crate ID
        A16/D16 at Address Offset 0xD0  Read    0x001f

    b) Read Serial Number
        A24/D8  at Address Offset 0xB4  Read    0x18

    c) Reset VRBC
        A24/D16 at Address Offset 0x0A  Write   0x0000

    d) Wait 50 milliseconds

    e) Select PDAQ
        A24/D8  at Address Offset 0xB2  Write   0x01

    f) Check SCL Status
        A24/D8  at Address Offset 0xD2  Read    expect 0x70, typically read 0x74



III) Initialize the VBD

   A24 Base Card Address is 0x380000
   A16 Base Card Address is 0x6000

    a) Un-Lock the VBD's CSR block and load DMA time-out.                           
        A16/D16 at Address Offset 0x0000    Write   0x000C

    b) Load the Crate Type
        A16/D16 at Address Offset 0x0008    Write   0x0002

    c) Load the address where the VBD can read the "event number" (on the VRBC)
        A16/D16 at Address Offset 0x000A    Write   0xC0D2 

    d) Load the address where the VBD can read the Crate ID
        A16/D16 at Address Offset 0x000C    Write   0xC0D0

    e) Tell the VBD what format to use to read the event data and Word Counts from the VRB's
        A16/D16 at Address Offset 0x0010    Write   0xBBF9

    f) Tell the VBD what format to use to read the "parameters"  
        A16/D16 at Address Offset 0x0012    Write   0xEDED

    g) Load the upper address bits that the VBD should use for parameter reads.
        A16/D16 at Address Offset 0x0014    Write   0xFF0A

    h) Load the list of addresses where the VBD can read the word counts
        A16/D16 at Address Offset 0x1000    Write   e.g. 0x000032 for VRB in Slot #19 (and all VRBs)

        etc, One entry (1x A16/D16 Write) for each VRB

        End this list with two D16 Words of 0x0000

    i) Load the list of starting addresses

        Upper Part of A24 Address 
        A16/D16 at Address Offset 0x1800    Write   e.g. 0x0013 for VRB in Slot #19

        Lower Part of A24 Address 
        A16/D16 at Address Offset 0x1802    Write   e.g. 0x0018 for VRB in Slot #19 (and all VRBs)

        etc, One entry (2x A16/D16 Writes) for each VRB

        End this list with two D16 Words of 0x0000

    j) Reset the VBD and clear its error FIFO 
        A16/D16 at Address Offset 0x0000    Write   0x00CC

    k) Wait 5 milliseconds

    l) Load the VBD DMA time-out value and lock the VBD Control Memory.
        A16/D16 at Address Offset 0x0000    Write   0x001C