http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/Trics_II_Initialization.txt -------------------------------------------------------------------------------- Trics System Initialization steps during the execution of an "Init" message from COOR ------------------------------------- Rev: Trics V9.3 Rev A (12-Sept-2001) Note: The Master Command File Menu Button "Initialize L1&L2 Frameworks" actually generates a COOR Initialize message and has thus the same result. The "Initialize" sequence is: 0) Display and Clear any previous Bit3 Errors, if present. 1) If (0) failed and Trics cannot clear bit3 errors (e.g. power off), declare "bad" status, and jump to (11) 2) Execute the Init_Pre_Auxi Master Command File (currently empty, but could receive "magical IOs" needed to guarantee proper initialization, or high level messages to direct the rest of the initialization, e.g. L1CT eta coverage) 3) If (2) failed, declare "bad" status, and jump to (11) (it is not expected that we would encounter errors during the simple Init_Pre_Auxi commands). 4) Display and Clear any previous Bit3 Errors, if present. 5) Call L1FW_Initialize 5.0) declaring the L1FW "non-operational". 5.1) Init L1FW Cards (If failed, return, i.e. jump to (6) ) 5.2) Display and Clear any previous Bit3 Errors, if present. 5.3) Init L2FW Cards (If failed, return, i.e. jump to (6) ) 5.4) Display and Clear any previous Bit3 Errors, if present. 5.5) Init L1FW VRB Readout Crate Cards (If failed, return, i.e. jump to (6) ) 5.6) Display and Clear any previous Bit3 Errors, if present. 5.7) Init_Post_Auxi_L1FW Master Command File (Initializing the SCL hub-end happens in Init_Post_Auxi_L1FW) (If failed, return, i.e. jump to (6) ) 5.8) Display and Clear any previous Bit3 Errors, if present. 5.9) If everything ok this far, the L1FW is declared "operational". (otherwise no subsequent COOR message can be executed). 6) If (5) failed, declare "bad" status, and jump to (11) 7) Call L1CT_Initialize (which is something that can be called directly) 7.1) if the Cal Trig is currently flagged "ignored" return, i.e. jump to (8) 7.2) Init L1CT Cards for current eta/phi coverage (only CTFE cards at the moment) (If failed, return, i.e. jump to (8) ) 7.3) Display and Clear any previous Bit3 Errors, if present. 7.4) Init_Post_Auxi_L1FW Master Command File (note that the eta/phi coverage in any .tti file must match the current eta/phi coverage) (If failed, return, i.e. jump to (8) ) 7.5) Display and Clear any previous Bit3 Errors, if present. 8) If (7) failed, declare "bad" status, and jump to (11) 9) Initialize the SCL Hub End Crate cf. Hub_End_Initialization_Steps.txt in http://www.pa.msu.edu/hep/d0/ftp/tcc/trics_ii/ 10) Even if (9) failed, do NOT declare "bad" status (This will change as soon as we are confident we test this new step for initializing the SCL Hub End Crate) 11) Write the LBN_At_Last_Init.lbn File 12) If the L1FW has been declared operational call the Increment_LBN message handler which will push a Lum Monit Data Block out the door The last two steps are not in logical order, but their order here makes no functional difference. The down side is that the LBN number written is the one before the initialize, instead of the first LBN number after the initialize, but the LBN recovery functionality is not affected. =============================================================================== State of L1FW resources after a COOR Initialize message ------------------------------------------------------- Rev: 25-May-2000 valid for Trics V8.6 This is a description of what is done by TRICS only, and thus excluding of all modifications made in Init_Auxi files. Level 1 Framework Cards ======================= L1 TRM ------ L1 AndOr TRM's Special timing signal distribution (0x2121) to latch inputs later than tick clock Set normal fifo input mode except for Andor Terms 224:255 set to Bypass fifo mode Fifo Error Checking enabled, ReSynch the Fifo, and clear errors. Missing: Enable Interrupts from all Fpga's at VME Interface L1 Front-End Busy TRM's Special timing signal distribution (0x2120) bypass fifo mode L1 Indiv Spec Trig Dis TRM's Special timing signal distribution (0x2120) bypass fifo mode L1 Global Spec Trig Dis TRM Special timing signal distribution (0x2120) bypass fifo mode All L1 TRM's Pattern A = 0's Pattern B = 1's Note: Pattern B will have to change to become what the terms are overridden to when a fifo error is detected. Reset all Scalers (using L1 helper synchronous reset method, but one fpga at a time) L1 AONM ------- L1 Physics AONM's Ignore all And-Or Terms (Don't Care) except for AndOr Term #255 required Low (while guaranteed High) The result is: output low L1 Exp Group AONM's Ignore all And-Or Terms (Don't Care) except for AndOr Term #255 required Low (while guaranteed High) The result is: output low All L1 AONM's Standard timing signal distribution (0x2440) Reset all Scalers (using L1 helper synchronous reset method, but one fpga at a time) L1 TDM ------ Standard timing signal distribution (0x2440) Special P5 IO Control (0x1010) Initialize all Spec Trig - to be disabled (by COOR) - to obey both andor inputs - to ignore all Exp Group Enable inputs - to ignore all Exp Group Front-End Busy Inputs - to obey the correlated source #3 of global disable. This is the Skip Next Beam Crossing signal. - to ignore all other correlated sources of global disable - to obey the de-correlated source #3 of global disable. This is the Global Disable/COOR Pause signal. - to ignore all other de-correlated sources of global disable - to obey the de-correlated source #0 of individual disable This is the L3 per SpTrg Disable Signal - to ignore the de-correlated source #1 of individual disable - to disable the prescaler - to disable the Auto-disable Reset all Scalers (using L1 helper synchronous reset method, but one fpga at a time) L1 FOM ------ L1 Start Digitize FOM's All Outputs listen to NONE of the inputs The result is: output low L1 Front-End Busy FOM All Outputs listen to NONE of the inputs The result is: output low All L1 FOM's Standard timing signal distribution (0x2440) Reset all Scalers (using L1 helper synchronous reset method, but one fpga at a time) L1 FOM++ -------- All L1 Qualifier Outputs listen to NONE of the inputs The result is: output low Special timing signal distribution (0x2330) to control the multiplexing of the L3 Transfer Number Enable and setup all bit fields of both copies of the L3 Transfer Number mulitplexed on L1 Qualifiers 0:15 and 16:32 Enable the Skip Next N Beam Crossing Channels, all initialized to a comparator value of 0 Except the Skip Next N Crossing Comparator #0 initialized with a count of 18 for minimum gap of 20 Beam X between L1 Accepts, i.e. ~>2.6 us This is FOM++ Channel #40, and Andor Input term #247 which should be required in veto for all SpTrg Andor Requirements. Reset all Scalers (using L1 helper synchronous reset method, but one fpga at a time) L1 Helper Function ------------------ Sets Helper in "normal" (vs. "test") mode. Delay of 5 Ticks between L1 Accept and Transport HSRO Data. This channel will cycle with every L1 Accept. Delay of 4 Ticks between L1 Accept and Capture HSRO Data. This channel will cycle with every L1 Accept. Delay of 4 Ticks between L1 Accept and Capture Monitor Data. This channel will only cycle when "armed" by TCC. Constraint: this channel's delay must be setup with the same delay as for the "Capture HSRO Data" channel. Note: This is currently overwritten by Post_Init_Auxi. Allow normal "Maginot Line" processing. Output will go high if the "TRM FIFO Error" input signal goes high. "Scaler Reset" TS output set low. Write something to the Test Mode Control Registers. Currently write same thing as SCT initialize, but maybe should write zeroes for simplicity. These registers are not functional because the card is in "normal" mode. Set TCC Global Disable LOW. Set the other 2 unallocated TCC Controllable outputs LOW. Tick and Turn Scalers --------------------- Special timing signal distribution (0x2300) Setup both scalers as Geographic Section Time Zone Framework Time Zone Set GeoSect TTN for FIFO Error Checking and clear any latched errors Set GeoSect TTN to use TTN muxed with FIFOed TTN sent to output Set GeoSect TTN to use delayed Turn Marker Reset and Synchronize the two Tick and Turn Scalers (using L1 helper synchronous reset method) Level 2 Framework Cards ======================= L2 TRM ------ L1 SpTrg Fired TRM's Special timing signal distribution (0xa220) gets the Capture Monit Data from a special TS Special P5 IO Controln (0x1110) Set normal fifo input mode No Fifo Error Checking enabled (why?) L1 Auxiliary Data TRM's Special timing signal distribution (0x2220) Special P5 IO Control (0x1010) Set normal fifo input mode No Fifo Error Checking enabled (why?) L2 Global Answer TRM's Special timing signal distribution (0x2220) Special P5 IO Control (0x1010) Set simulated data mode while there is no L2 Global No Fifo Error Checking enabled while there is no L2 Global All TRM's Pattern A = 1's Pattern B = 1's Set L2 Mode Force Fifo Counter Reset by pulsing a bit in each Fpga Scaler Force Reset Register Manually Clear Error Enable in VME Interface Interrupts from all MA Fpga's Reset all Scalers (using L1 helper synchronous reset method, but one fpga at a time) L2 AONM ------- L2 Accept AONM's L2 Accept AONM's Special timing signal distribution (0x2420) Initialize all outputs to require all And-Or Terms High The result is: output low note: "AoTerm" for L2FW is in fact also a SpTrg, lower half are L1 Fired and upper half are L2 GLobal Answer L2 FOM ------ L2 Accept FOM's L2 Accept FOM's Special timing signal distribution (0x2420) All Outputs listen to NONE of the inputs The result is: output low Reset all Scalers (using L1 helper synchronous reset method, but one fpga at a time) L2 BAD ------ Standard timing signal distribution (0x2440) Disable all Channels The result is: output low (no GeoSect can stall a L2 Cycle) L2 FM D-Latches --------------- L1 Trigger Number and L3 Transfer Number FM D-Latch Special timing signal distribution (0xa430) gets the Capture Monit Data from a special TS Special P5 IO Control (0x1110) L2 Specific Trigger Fired FM D-Latch Special timing signal distribution (0x2430) L2 Helper Function ------------------ L2 Answer Strobe sourced by L2 Global Set State engine in "L2 GLobal Bypass" mode (0x0001) Resets the L2 Helper State Engine