Topology for TCC access to L2 Trigger Processor Crates ------------------------------------------------------ Updated: 28-Jun-01 =============================================== H L2 Trigger Control Computer H H (L2 TCC = d0tcc2.fnal.gov) H H _ in M125 H H |B| H H |i| H H |t| H H |3| H H | | H H | | H H | | Windows NT H H | | Intel CPU H H .+. PCI-Bus H H | H ===|=========================================== | | +--|------------------------------------------+ | | 7 Slot PCI Expansion Backplane | | | Bit3 Model 2132 (=SS32) in M125 | | .+. _ _ _ _ _ _ _ | | |B| |B||B||B||B||B||B||B| | | |i| |i||i||i||i||i||i||i| | | |t| |t||t||t||t||t||t||t| | | |3| |3||3||3||3||3||3||3| | | | | | || || || || || || | | | | | |6||6||6||6||6||6||6| | | | | |1||1||1||1||1||1||1| | | | | |8||8||8||8||8||8||8| | | ._. .+..+..+..+..+..+..+. | | | | | | | | | | +----------------|--|--|--|--|--|--|----------+ | | | | | | | Optical | | | | | | | Links | | | | | | .____ Spare | | | | | | | | | | | ._____________________________ | | | | | | ___________________. | | | .___________________ | | | | | | | | _________. | ._________ | | | | | | | | | | | | | | +-|--------+ +-|--------+ +-|--------+ +-|--------+ +-|--------+ +-|--------+ | | L2CMU | | | L2FMU | | | L2CAL | | | L2CTT | | | L2PS | | | L2GBL | |.+. | |.+. | |.+. | |.+. | |.+. | |.+. | ||B| L2 | ||B| L2 | ||B| L2 | ||B| L2 | ||B| L2 | ||B| L2 | ||i| Centrl| ||i| Forwrd| ||i| Calor | ||i| Centrl| ||i| Pre- | ||i| Global| ||t| Muon | ||t| Muon | ||t| Triggr| ||t| Trckng| ||t| Shower| ||t| Triggr| ||3| Triggr| ||3| Triggr| ||3| Pre- | ||3| Triggr| ||3| Triggr| ||3| Proc | || | Pre- | || | Pre- | || | Proc | || | Pre- | || | Pre- | || | Crate | ||6| Proc | ||6| Proc | ||6| Crate | ||6| Proc | ||6| Proc | ||6| | ||1| Crate | ||1| Crate | ||1| | ||1| Crate | ||1| Crate | ||1| | ||8| | ||8| | ||8| | ||8| | ||8| | ||8| | |._. | |._. | |._. | |._. | |._. | |._. | | | | | | | | | | | | | |(9U-VIPA) | |(9U-VIPA) | |(9U-VIPA) | |(9U-VIPA) | |(9U-VIPA) | |(9U-VIPA) | +----------+ +----------+ +----------+ +----------+ +----------+ +----------+ -------------------------------------------------------------------------------- Access to the Level 2 Trigger Processor Crates ============================================== The Level 2 Processor Crates VME Space must be accessible from the the L2 Trigger Control Computer (L2 TCC). The L2 TCC is a separate computer, independent of L1 TCC, and handling only the programming and monitoring of the L2 Trigger Crates. Each L2 Processor Crate is connected to the L2 TCC via a Model 618 PCIbus to VMEbus Adapter with optical interconnection. There will be as many independent Bus Adaptors as there are L2 Processor Crates. The L2 Trigger Control Computer uses a Bit3 7 slot PCI expansion backplane to accomodate all the L2 Processor Crates. On the Level 2 Processor Crate side the Bit3 Model 618 module will be configured as VME Crate Controller, in Slot #1. Each Bit 3 Model 618 card installed in its L2 Processor Crate will also receive a dual port Memory option (e.g. 1 MByte). This dual port memory is mapped onto the L2 Crate VME space and can be written to by any master inside the L2 Crate, including any of the alpha procesoor boards. This dual port memory can also be accessed directly from the remotely connected Bit 3 Model 618 Card *without generating any VME cycle in the local VME Crate*. This means that TCC can access data from a L2 Processor Crate Dual Port Memory without generating VME cycles inside the crate. During data taking, TCC should keep out of the L2 Processor Crates and not interfere with VME activity (e.g. VBD readout). But Monitoring information should still be retrieved at regular time intervals from the L2 Processor Crates. The L2 Administrator Processor in the L2 Processor Crate will write to the Dual-Port Memory at an appropriate time, and TCC can retrieve that information at its leisure without interfering with Trigger activity. TCC will want to access two types of resources inside each Level 2 Processor Crate. First, TCC may want to see each L2 Processor Memory Space and the hardware control registers of all supporting VME cards (e.g. the MBT). The second type of Access by TCC to a L2 Processor Crate (and only type of access while a run is under way) is to read the dual-ported memory on the Bit3 interface of each remote crate to retrieve Monitoring information. The dual port memory address space is mapped onto TCC's address space separately from the mapping of the L2 Processor VME address space. But these two independent address spaces will still compete for address mapping resources on the Model 617 or 618. A maximum of 32 MBytes of TCC's process virtual space can be mapped through each Bus Adaptor at a given time. One important point is that TCC does not *need* to have the whole VME space mapped at all times, and in fact that TCC probably does not *want* to have most parts of the L2 Processor Crate VME space mapped except when it needs to access it. TCC should only need to look inside the L2 Processor crates on special occasions (e.g. event dump or system dumps). In order to protect against accidental access to an L2 Processor VME crate, we should not have this space mapped by default, but only map it and release it on demand. The Dual Port Memory Address Space of each L2 Processor crate (or parts of it) will probably be mapped at all times.