Handel-C is a C-based programming language for Alterra and Xilinx FPGA's. You trade higher-level expression of algorithms for less source-level control over implementation. Explicit parallelism is implemented by wrapping with a synchronizing flipflop. The timing model is simple and predictable, with all assignment taking one clock cycle. The language includes control over signal path width and distinguishes several memory models. C's ability to express complex sequential control often obviates the need for state machine design. Special chip capabilities, external hardware, or other FPGA modules can be described behaviorally by their interfaces. The environment includes a fast simulator, compiles to an architecture-aware netlist or VHDL, and allows designs to mix VHDL and Handel-C.

The smaller detail load is claimed to result in substantially faster development time, and smaller source code (better intellectual control), with comparable performance and resource use. The compiler knows the target chip architecture, and the chip manufacturer's fitter still allows influence over final place and route. However, I've heard from several folks that this, rather than the logic specification, is where is where the bulk of the time is spent. You could also imagine a much smaller gap between the trigger-simulation code and the actual hardware.

Mike Levine felt that the biggest problem for physicists was learning to think concurrently. His project was in Handel-C 2.1, which had a number of limitations compared to the 3.0 version. But 3.0 also was slower and introduced problems, which they are fixing (and he is buying more PC memory). The test bench/simulator is a good learning tool, but they used make rather than the gui for builds. He'd steer a physicist towards Handel-C: it's easier. But an EE already proficient with VHDL he'd leave alone. You have to learn by experience what constructs generate good code with a given chip. He's used it for a card with several FPGA's, some of them pretty full (talk, further comments). Compile times are small compared to fitter times.