Level 2 Trigger Hardware

• Magic Bus and Alpha in VME (including software)
  • D0 VME and CDF VME Crate specs
  • Hand-wired connections on J2 Backplane in D0 L2 crates
• Beta Processor Project
• SLIC (Second Level Input Computer) DSP board
  • SLIC page at Nevis
• Data Transfer : Formats, Sizes, and I/O Cards
  • L2 Header/Trailer and DataTypeID's and Crate ID's
  • L1 Qualifier Bits
  • Cypress circuits and protocol
  • Magic Bus Transceiver (MBT)
  • Fiber Input Converter (FIC)
  • Cable Input Converter (CIC) and Serial FanOut (SFO)
  • CDF Upgrade page, including VRB and Trigger Information
  • DØ VRB and VBD information and VBD Manual
• Contents of Each L2 Crates and count of each card type
• Power consumption of Crates
• Safety Information

The Serial Command Link (SCL) connects the Level 1 and 2 Frameworks to the detector Front-Ends. The Electronics Certification Board (ECB) page describes the SCL and its mezzanine card, as well as the Geographic Section protocol.

• Want to program FPGA's in C?

linnemann@pa.msu.edu