DSKA => DSP Starter Kit Assembler Rev 1.00 Thu Jun 10 21:53:20 1993 Copyright (c) 1992-1993 Texas Instruments Incorporated 0001 - ---- ---- **************************************************************************** 0002 - ---- ---- * * 0003 - ---- ---- * File: Temp_1.ASM * 0004 - ---- ---- * * 0005 - ---- ---- * This is the program section for the first test program of DSP L15 Cal * 0006 - ---- ---- * Trig filtering. * 0007 - ---- ---- * * 0008 - ---- ---- * First we will scan through the Trigger Towers that this DSP Node is * 0009 - ---- ---- * responsible for (i.e. eta's n+2,n+3,n+4,n+5) and look for Trigger * 0010 - ---- ---- * Towers that are above the L15 Ref Set. * 0011 - ---- ---- * * 0012 - ---- ---- * When we find a Trig Tower above its entry in the L15 Ref Set we will * 0013 - ---- ---- * set a bit in a mask and then branch immediately to the L15 algorithm * 0014 - ---- ---- * processing before finishing the scan for Trig Towers above the L15 * 0015 - ---- ---- * Ref Set. This is because we do not want to have to scan through the * 0016 - ---- ---- * mask to see where in eta and phi to run the L15 algorithm because it * 0017 - ---- ---- * will take almost as long to scan the mask as it took to build it in * 0018 - ---- ---- * the first place. * 0019 - ---- ---- * * 0020 - ---- ---- * The L1 rack data and the L15 Ref Set data in loaded via an include * 0021 - ---- ---- * file. The layout of this data is explained in the include file. It * 0022 - ---- ---- * is stored in internal memory B3 and can thus be used with either * 0023 - ---- ---- * CONF 1 or CONF 2. * 0024 - ---- ---- * * 0025 - ---- ---- * When a tower is found above L15 Ref Set then a routine is called * 0026 - ---- ---- * to execute the L15 Algorithm. There are 4 versions of this * 0027 - ---- ---- * algorithm stored in program memory. They differ only in the details * 0028 - ---- ---- * of their "hard wired" addressing (i.e. was the Trigger Tower above * 0029 - ---- ---- * the L15 Ref Set an eta n+2, n+3, n+4, or n+5 tower). * 0030 - ---- ---- * * 0031 - ---- ---- * Recall the arrangement of eta's in the racks: * 0032 - ---- ---- * * 0033 - ---- ---- * Rack Rack #1 Rack #2 * 0034 - ---- ---- * Signal -------------------- --------------------- * 0035 - ---- ---- * Names n n+1 n+2 n+3 n+4 n+5 n+6 n+7 * 0036 - ---- ---- * * 0037 - ---- ---- * This DSP Node -------------------------- * 0038 - ---- ---- * is Responsible n+2 n+3 n+4 n+5 * 0039 - ---- ---- * for these eta's * 0040 - ---- ---- * * 0041 - ---- ---- * * 0042 - ---- ---- * For convenients only the n+3 version of the L15 algorithm will be coded.* 0043 - ---- ---- * * 0044 - ---- ---- * AR0 is the Aux Reg increment value * 0045 - ---- ---- * AR1 is the pointer to Rack 1 EM data. * 0046 - ---- ---- * AR2 is the pointer to Rack 2 EM data. * 0047 - ---- ---- * AR3 is the pointer to Rack 1 L15 Ref Set data. * 0048 - ---- ---- * AR4 is the pointer to Rack 2 L15 Ref Set data. * 0049 - ---- ---- * AR5 is the counter for the phi index. * 0050 - ---- ---- * AR6 is the pointer to the summation list. * 0051 - ---- ---- * AR7 is * 0052 - ---- ---- * * 0053 - ---- ---- * * 0054 - ---- ---- * * 0055 - ---- ---- * * 0056 - ---- ---- * * 0057 - ---- ---- * * 0058 - ---- ---- * * 0059 - ---- ---- **************************************************************************** 0060 - ---- ---- 0061 - ---- ---- .Text ; Make this a Program Section. 0062 - ---- ---- .PS 0fb00h ; Set the Prog Sect address i.e. right 0063 - ---- ---- ; after the DSKD monitor. 0064 - ---- ---- .Entry ; Declare this the entry point. >>>>> ENTRY POINT SET TO fb00 0065 - ---- ---- 0066 - ---- ---- Cnst2 .Set 0002h ; The value 2 is loaded into AR0 so 0067 - ---- ---- ; that AR0 may be used to "double 0068 - ---- ---- ; increment" other Auxiliary Registers 0069 - ---- ---- ; by using "*0+" addressing. 0070 - ---- ---- 0071 - ---- ---- Rk1EM .Set 0600h ; The beginning address of Rack 1 EM Et 0072 - ---- ---- ; Data. 0073 - ---- ---- Rk2EM .Set 0640h ; The beginning address of Rack 2 EM Et 0074 - ---- ---- ; Data. 0075 - ---- ---- 0076 - ---- ---- Rk1Tot .Set 0680h ; The beginning address of Rack 1 Total 0077 - ---- ---- ; Et Data. 0078 - ---- ---- Rk2Tot .Set 06C0h ; The beginning address of Rack 2 Total 0079 - ---- ---- ; Et Data. 0080 - ---- ---- 0081 - ---- ---- RS1Data .Set 0700h ; The beginning address of Rack 1 0082 - ---- ---- ; L15 Reference Set data. 0083 - ---- ---- RS2Data .Set 0780h ; The beginning address of Rack 2 0084 - ---- ---- ; L15 Reference Set data. 0085 - ---- ---- 0086 - ---- ---- PhiCnt .Set 0031 ; This this the number of loops to make 0087 - ---- ---- ; through the Phi Index in order to 0088 - ---- ---- ; have loop through all of the phi's 0089 - ---- ---- ; looking for Trigger Towers above 0090 - ---- ---- ; the L15 Reference Set. Because of 0091 - ---- ---- ; the BANZ instruction this will run 0092 - ---- ---- ; through the eta loop 32 times. 0093 - ---- ---- 0094 - ---- ---- 0095 0 fb00 ce3d BegInt: CONF 1 ; B0 is Program Space $FA00:$FBFF 0096 - ---- ---- ; B1 is Data Space $0400:$05FF 0097 - ---- ---- ; B2 is Data Space $0060:$007F 0098 - ---- ---- ; B3 is Data Space $0600:$07FF 0099 - ---- ---- 0100 0 fb01 ce06 RSXM ; Clear the sign extend bit is the Status 0101 - ---- ---- 0102 - ---- ---- ; Reg #1. i.e. all positive numbers. 0103 - ---- ---- 0104 0 fb02 d000 IntStr: LRLK AR0,Cnst2 ; Aux Reg 0 will be used for *0+ adrsing. 0105 - ---- ---- 0106 - ---- ---- 0107 0 fb04 d100 LRLK AR1,Rk1EM ; Aux Reg 1 points to Rack 1 EM data. 0108 0 fb06 d200 LRLK AR2,Rk2EM ; Aux Reg 2 points to Rack 2 EM data. 0109 0 fb08 d300 LRLK AR3,RS1Data ; Aux Reg 3 points to Rack 1 L15 Ref Set. 0110 - ---- ---- 0111 0 fb0a d400 LRLK AR4,RS2Data ; Aux Reg 4 points to Rack 2 L15 Ref Set. 0112 - ---- ---- 0113 - ---- ---- 0114 - ---- ---- ; Move the pointer for Rack 1 and 2 to 0115 - ---- ---- ; skip over eta's n and n+1 for both 0116 - ---- ---- ; the rack data and the Ref Set data. 0117 0 fb0c 5589 LARP AR1 ; Select Aux Reg 1, i.e. Rack 1 data. 0118 0 fb0d 7e01 ADRK 1 ; Skip Rack 1 data for eta n and n+1. 0119 0 fb0e 558b LARP AR3 ; Select Aux Reg 3, i.e. Ref Set Rack 1. 0120 - ---- ---- 0121 0 fb0f 7e02 ADRK 2 ; Skip Ref Set 1 data for eta n and n+1. 0122 - ---- ---- 0123 - ---- ---- 0124 0 fb10 c808 LDPK 8 ; Select Data Page #8 i.e. adrs 400h. 0125 - ---- ---- 0126 0 fb11 d500 StrPhi: LRLK AR5,PhiCnt ; Aux Reg 5 will be the loop counter for 0127 - ---- ---- ; running through all 32 phi's. 0128 - ---- ---- 0129 0 fb13 5589 LARP AR1 ; Select Aux Reg 1, i.e. Rack 1 EM data. 0130 - ---- ---- 0131 - ---- ---- 0132 - ---- ---- ; Everything is now set for looping over 0133 - ---- ---- ; all 32 phi's looking for Trigger Towers 0134 - ---- ---- 0135 - ---- ---- ; that are above the L15 Ref Set. 0136 - ---- ---- 0137 0 fb14 208b Loop1: LAC *,0,AR3 ; Load Rack 1 EM data for eta's n+2, n+3 0138 - ---- ---- ; Set ARP=3 i.e. select Rack 1 Ref Set 0139 - ---- ---- ; data. Do not left shift of the data. 0140 - ---- ---- 0141 0 fb15 4e00 AND LowByt ; Mask the high byte i.e. keep eta n+2. 0142 0 fb16 10a9 SUB *+,0,AR1 ; Subtract the Ref Set data for eta n+2. 0143 - ---- ---- ; Increment the Ref Set data pointer. 0144 - ---- ---- ; Do not shift the Ref Set data. 0145 - ---- ---- ; Set ARP=1 i.e. select Rack 1 EM data. 0146 - ---- ---- 0147 - ---- ---- 0148 0 fb17 f380 BLZ NxTst3 ; If Tower n+2 was not above threshold 0149 - ---- ---- ; then the next test is tower n+3. 0150 - ---- ---- 0151 0 fb19 fe80 CALL HotN2 ; Call the routine for the L15 algorithm 0152 - ---- ---- ; for an eta n+2 Trigger Tower above 0153 - ---- ---- ; l15 Ref Set. 0154 - ---- ---- 0155 0 fb1b 20eb NxTst3: LAC *0+,0,AR3 ; Load Rack 1 EM data for eta's n+2, n+3. 0156 - ---- ---- 0157 - ---- ---- ; Set ARP=3 i.e. select Rack 1 Ref Set 0158 - ---- ---- ; data. Do not left shift of the data. 0159 - ---- ---- 0160 - ---- ---- ; Add 2 to the Rack 1 EM data pointer. 0161 0 fb1c 4e00 AND HiByte ; Mask the low byte i.e. keep eta n+3. 0162 0 fb1d 10eb SUB *0+,0,AR3 ; Subtract the Ref Set data for eta n+3. 0163 - ---- ---- ; Add 2 to the Ref Set data pointer. 0164 - ---- ---- ; Do not shift the Ref Set data. 0165 - ---- ---- ; Keep ARP=3 i.e. select Rack 1 Ref 0166 - ---- ---- ; Set data. 0167 - ---- ---- 0168 0 fb1e f380 BLZ NxTst4 ; If Tower n+3 was not above threshold 0169 - ---- ---- ; then the next test is tower n+4. 0170 - ---- ---- 0171 0 fb20 fe80 CALL HotN3 ; Call the routine for the L15 algorithm 0172 - ---- ---- ; for an eta n+3 Trigger Tower above 0173 - ---- ---- ; l15 Ref Set. 0174 - ---- ---- 0175 0 fb22 10aa NxTst4: SUB *+,0,AR2 ; This SUB is just a fast way to 0176 - ---- ---- ; increment the pointer to the Rack 1 0177 - ---- ---- ; Ref Set data i.e. now it points to 0178 - ---- ---- ; the next phi eta n+2. 0179 - ---- ---- ; Set ARP=2 i.e. select Rack 2 EM data. 0180 - ---- ---- 0181 - ---- ---- 0182 - ---- ---- ; Now do the 2 eta's from the second 0183 - ---- ---- ; rack before switching to the next 0184 - ---- ---- ; higher Phi Index. 0185 - ---- ---- 0186 0 fb23 208c LAC *,0,AR4 ; Load Rack 2 EM data for eta's n+4, n+5 0187 - ---- ---- ; Set ARP=4 i.e. select Rack 2 Ref Set 0188 - ---- ---- ; data. Do not left shift of the data. 0189 - ---- ---- 0190 0 fb24 4e00 AND LowByt ; Mask the high byte i.e. keep eta n+4. 0191 0 fb25 10aa SUB *+,0,AR2 ; Subtract the Ref Set data for eta n+4. 0192 - ---- ---- ; Increment the Ref Set data pointer. 0193 - ---- ---- ; Do not shift the Ref Set data. 0194 - ---- ---- ; Set ARP=2 i.e. select Rack 2 EM data. 0195 - ---- ---- 0196 - ---- ---- 0197 0 fb26 f380 BLZ NxTst5 ; If Tower n+4 was not above threshold 0198 - ---- ---- ; then the next test is tower n+5. 0199 - ---- ---- 0200 0 fb28 fe80 CALL HotN4 ; Call the routine for the L15 algorithm 0201 - ---- ---- ; for an eta n+4 Trigger Tower above 0202 - ---- ---- ; l15 Ref Set. 0203 - ---- ---- 0204 0 fb2a 20ec NxTst5: LAC *0+,0,AR4 ; Load Rack 2 EM data for eta's n+4, n+5. 0205 - ---- ---- 0206 - ---- ---- ; Set ARP=4 i.e. select Rack 2 Ref Set 0207 - ---- ---- ; data. Do not left shift of the data. 0208 - ---- ---- 0209 - ---- ---- ; Add 2 to the Rack 2 EM data pointer. 0210 0 fb2b 4e00 AND HiByte ; Mask the low byte i.e. keep eta n+5. 0211 0 fb2c 10ec SUB *0+,0,AR4 ; Subtract the Ref Set data for eta n+5. 0212 - ---- ---- ; Add 2 to the Ref Set data pointer. 0213 - ---- ---- ; Do not shift the Ref Set data. 0214 - ---- ---- ; Keep ARP=4 i.e. Rack 2 Ref Set data. 0215 - ---- ---- 0216 0 fb2d f380 BLZ NxTst2 ; If Tower n+5 was not above threshold 0217 - ---- ---- ; then the next test is tower n+2. 0218 - ---- ---- 0219 0 fb2f fe80 CALL HotN5 ; Call the routine for the L15 algorithm 0220 - ---- ---- ; for an eta n+5 Trigger Tower above 0221 - ---- ---- ; l15 Ref Set. 0222 - ---- ---- 0223 0 fb31 10ad NxTst2: SUB *+,0,AR5 ; This SUB is just a fast way to 0224 - ---- ---- ; Increment by 2 the Rack 2 pointer. 0225 - ---- ---- ; Ref Set data i.e. now it points to 0226 - ---- ---- ; the next phi eta n+2. 0227 - ---- ---- ; Set ARP=5 i.e. select the Aux Reg 0228 - ---- ---- ; for the phi loop counter. 0229 - ---- ---- 0230 0 fb32 fb99 BANZ Loop1,*-,AR1 ; Test to see if we have looked at all 0231 - ---- ---- ; 32 phi's. Set ARP=1 to select the 0232 - ---- ---- ; Rack 1 EM data. 0233 - ---- ---- 0234 - ---- ---- ; We exit via the BANZ instruction when 0235 - ---- ---- ; all 32 phi's have been scanned. The 0236 - ---- ---- ; next instruction will be the first 0237 - ---- ---- ; one to execute after scanning all 0238 - ---- ---- ; 32 phi's for Trigger Towers above 0239 - ---- ---- ; the L15 Reference Set. 0240 - ---- ---- 0241 - ---- ---- >>>>> LINE:0242 WARNING: BAD OR MISSING NUMERIC FIELD 0242 0 fb34 8300 IN InTar,PA3 ; Read Port Address 1 and store it in 0243 - ---- ---- ; address $0410. We are currently on 0244 - ---- ---- ; data memory page 8 so all is OK. 0245 - ---- ---- ; This is just to make a wire wiggle 0246 - ---- ---- ; outside of the chip. 0247 0 fb35 558d LARP AR5 ; Select Aux Reg 5. This is the phi 0248 - ---- ---- ; loop control register which will 0249 - ---- ---- ; need to be initialized again before 0250 - ---- ---- ; starting the phi loop again. 0251 0 fb36 ff80 B IntStr ; Jump to the start of the Phi Loop 0252 - ---- ---- 0253 - ---- ---- 0254 0 fb38 ce1f Idle 0255 - ---- ---- 0256 - ---- ---- 0257 0 fb39 ce1f HotN2: Idle 0258 0 fb3a ce1f HotN3: Idle 0259 0 fb3b ce1f HotN5: Idle 0260 - ---- ---- 0261 0 fb3c 288a HotN4: LAC *,8,AR2 ; This is the beginning of the L15 0262 - ---- ---- ; algorithm for n+4 Trigger Towers 0263 - ---- ---- ; above the L15 Ref Set. We arrive 0264 - ---- ---- ; here with ARP=2 i.e. the Rack 2 0265 - ---- ---- ; EM data. AR2 still contains the 0266 - ---- ---- ; address of the EM tower that was 0267 - ---- ---- ; above L15 Ref Set. Get the n+4, 0268 - ---- ---- ; n+5 data. 8 left shifts. Keep ARP=2. 0269 0 fb3d 6000 SACL EMPrt1 ; Store eta n+4, phi cent in EMPrt1. 0270 - ---- ---- 0271 0 fb3e 41e8 ZALS *0+,0,AR2 ; Load Rack 2 EM Et for eta n+4, n+5. 0272 - ---- ---- ; No shifts. Add 2 to AR2 i.e. next 0273 - ---- ---- ; phi. Keep ARP=2 i.e. Rack 2 EM. 0274 0 fb3f 4e00 AND HiByte ; Mask the low byte i.e. keep eta n+5. 0275 0 fb40 6000 SACL EMPrt2 ; Store eta n+5, phi cent in EMPrt2. 0276 - ---- ---- 0277 0 fb41 288a LAC *,8,AR2 ; Load Rack 2 EM Et for eta n+4, n+5, 0278 - ---- ---- ; phi = cent+1. Shifts by 8. 0279 - ---- ---- ; Keep ARP=2 i.e. Rack 2 EM. 0280 0 fb42 6000 SACL EMPrt3 ; Store eta n+4, phi cent+1 in EMPrt3. 0281 - ---- ---- 0282 0 fb43 41d8 ZALS *0-,0,AR2 ; Load Rack 2 EM Et for eta n+4, n+5, 0283 - ---- ---- ; phi=Cent+1. No shifts. Sub 2 from 0284 - ---- ---- ; AR2. Keep ARP=2 i.e. Rack 2 EM. 0285 0 fb44 4e00 AND HiByte ; Mask the low byte i.e. keep eta n+5. 0286 0 fb45 6000 SACL EMPrt4 ; Store eta n+5, phi cent+1 in EMPrt4. 0287 - ---- ---- 0288 0 fb46 7f02 SBRK 0002h ; Subtract 2 from AR2, now phi = cent-1. 0289 - ---- ---- 0290 0 fb47 288a LAC *,8,AR2 ; Load Rack 2 EM Et for eta n+4, n+5, 0291 - ---- ---- ; phi = cent-1. Shifts by 8. 0292 - ---- ---- ; Keep ARP=2 i.e. Rack 2 EM. 0293 0 fb48 6000 SACL EMPrt5 ; Store eta n+4, phi cent-1 in EMPrt5. 0294 - ---- ---- 0295 0 fb49 41e8 ZALS *0+,0,AR1 ; Load Rack 2 EM Et for eta n+4, n+5, 0296 - ---- ---- ; phi=Cent-1. No shifts. Add 2 to 0297 - ---- ---- ; AR2. Set ARP=1 i.e. Rack 1 EM. 0298 - ---- ---- ; AR2 is now back to the value that 0299 - ---- ---- ; it arrived with in this routine. 0300 0 fb4a 4e00 AND HiByte ; Mask the low byte i.e. keep eta n+5. 0301 0 fb4b 6000 SACL EMPrt6 ; Store eta n+5, phi cent-1 in EMPrt6. 0302 - ---- ---- 0303 0 fb4c 41d8 ZALS *0-,0,AR1 ; Load Rack 1 EM Et for eta n+2, n+3, 0304 - ---- ---- ; phi=Cent+1. No shifts. Sub 2 from 0305 - ---- ---- ; AR1. Keep ARP=1 i.e. Rack 1 EM. 0306 - ---- ---- ; AR1 is now phi = cent. 0307 0 fb4d 4e00 AND HiByte ; Mask the low byte i.e. keep eta n+3. 0308 0 fb4e 6000 SACL EMPrt7 ; Store eta n+3, phi cent+1 in EMPrt7. 0309 - ---- ---- 0310 0 fb4f 41d8 ZALS *0-,0,AR1 ; Load Rack 1 EM Et for eta n+2, n+3, 0311 - ---- ---- ; phi=Cent. No shifts. Sub 2 from 0312 - ---- ---- ; AR1. Keep ARP=1 i.e. Rack 1 EM. 0313 - ---- ---- ; AR1 is now phi = cent-1. 0314 0 fb50 4e00 AND HiByte ; Mask the low byte i.e. keep eta n+3. 0315 0 fb51 6000 SACL EMPrt8 ; Store eta n+3, phi cent in EMPrt8. 0316 - ---- ---- 0317 0 fb52 4188 ZALS *,0,AR1 ; Load Rack 1 EM Et for eta n+2, n+3, 0318 - ---- ---- ; phi=Cent-1. No shifts. 0319 - ---- ---- ; Keep ARP=1 i.e. Rack 1 EM. 0320 - ---- ---- ; AR1 is still phi = cent-1. 0321 0 fb53 4e00 AND HiByte ; Mask the low byte i.e. keep eta n+3. 0322 0 fb54 6000 SACL EMPrt9 ; Store eta n+3, phi cent in EMPrt9. 0323 - ---- ---- 0324 0 fb55 7e04 ADRK 4 ; Put AR1 back to phi = Cent+1 i.e. 0325 - ---- ---- ; the value that it arrived with. 0326 - ---- ---- 0327 - ---- ---- ; Now all the 9 EMprt% to make the 3x3 0328 - ---- ---- ; EM Et sum. 0329 0 fb56 ca00 ZAC ; Clear the accumulator. 0330 - ---- ---- ADD EMPrt1 ; Get EM Et Part 1 0330 0 fb57 0000 ADD EMPrt1 ; Get EM Et Part 1 0331 - ---- ---- ADD EMPrt2 ; Get EM Et Part 2 0331 0 fb58 0000 ADD EMPrt2 ; Get EM Et Part 2 0332 - ---- ---- ADD EMPrt3 ; Get EM Et Part 3 0332 0 fb59 0000 ADD EMPrt3 ; Get EM Et Part 3 0333 - ---- ---- ADD EMPrt4 ; Get EM Et Part 4 0333 0 fb5a 0000 ADD EMPrt4 ; Get EM Et Part 4 0334 - ---- ---- ADD EMPrt5 ; Get EM Et Part 5 0334 0 fb5b 0000 ADD EMPrt5 ; Get EM Et Part 5 0335 - ---- ---- ADD EMPrt6 ; Get EM Et Part 6 0335 0 fb5c 0000 ADD EMPrt6 ; Get EM Et Part 6 0336 - ---- ---- ADD EMPrt7 ; Get EM Et Part 7 0336 0 fb5d 0000 ADD EMPrt7 ; Get EM Et Part 7 0337 - ---- ---- ADD EMPrt8 ; Get EM Et Part 8 0337 0 fb5e 0000 ADD EMPrt8 ; Get EM Et Part 8 0338 - ---- ---- ADD EMPrt9 ; Get EM Et Part 9 0338 0 fb5f 0000 ADD EMPrt9 ; Get EM Et Part 9 0339 - ---- ---- ; The accumulator now holds the 3x3 EM 0340 - ---- ---- ; Et. The LSB of the sum is in 0341 - ---- ---- ; accumulator bit 8, accumulator bits 0342 - ---- ---- ; 0:7 are zero. 0343 0 fb60 6800 SACH EMPrt2 ; Store the High Accumulator in EMPrt2. 0344 0 fb61 6000 SACL EMPrt1 ; Store the High Accumulator in EMPrt1. 0345 - ---- ---- 0346 0 fb62 558a LARP 2 ; Select Aux Reg 2 i.e. the Aux Reg that 0347 - ---- ---- 0348 - ---- ---- ; we arrived with in this routine. 0349 0 fb63 ce26 RET ; Return to the calling routine. 0350 - ---- ---- 0351 - ---- ---- 0352 - ---- ---- 0353 - ---- ---- .Data ; Declare a Data Memory Program Section. 0354 - ---- ---- .DS 0400h ; Set the Data Memory Address at the 0355 - ---- ---- ; beginning of internal memory B1. 0356 - ---- ---- LowByt: .Word 00FFh ; Mask for the lower byte. 0356 1 0400 00ff 0357 - ---- ---- HiByte: .Word 0FF00h ; Mask for the upper byte. 0357 1 0401 ff00 0358 - ---- ---- SumEm: .Word 0000h ; Memory location for building the 3x3 0358 1 0402 0000 0359 - ---- ---- ; EM Et sum. 0360 - ---- ---- EMPrt1: .Word 0000h ; 1st of 9 parts of the 3x3 EM Et Sum. 0360 1 0403 0000 0361 - ---- ---- EMPrt2: .Word 0000h ; 2nd of 9 parts of the 3x3 EM Et Sum. 0361 1 0404 0000 0362 - ---- ---- EMPrt3: .Word 0000h ; 3rd of 9 parts of the 3x3 EM Et Sum. 0362 1 0405 0000 0363 - ---- ---- EMPrt4: .Word 0000h ; 4th of 9 parts of the 3x3 EM Et Sum. 0363 1 0406 0000 0364 - ---- ---- EMPrt5: .Word 0000h ; 5th of 9 parts of the 3x3 EM Et Sum. 0364 1 0407 0000 0365 - ---- ---- EMPrt6: .Word 0000h ; 6th of 9 parts of the 3x3 EM Et Sum. 0365 1 0408 0000 0366 - ---- ---- EMPrt7: .Word 0000h ; 7th of 9 parts of the 3x3 EM Et Sum. 0366 1 0409 0000 0367 - ---- ---- EMPrt8: .Word 0000h ; 8th of 9 parts of the 3x3 EM Et Sum. 0367 1 040a 0000 0368 - ---- ---- EMPrt9: .Word 0000h ; 9th of 9 parts of the 3x3 EM Et Sum. 0368 1 040b 0000 0369 - ---- ---- 0370 - ---- ---- InTar: .Word 0000h ; Target memory location for the IN read. 0370 1 040c 0000 0371 - ---- ---- 0372 - ---- ---- 0373 - ---- ---- 0374 - ---- ---- .ListOff 0377 - ---- ---- 0378 - ---- ---- .End >>>>> LINE:378 .END ENCOUNTERED >>>>> FINISHED READING ALL FILES >>>>> ASSEMBLY COMPLETE: ERRORS:0 WARNINGS:1