
Check_DMA   IDNT                         ; Title of  Cyclic Section

         SECTION   Sect_Check_DMA,4,C    ; Declare a noncommon code section.
                                         ; Align to Longwords.

***************************************************************************
*                                                                         *
*   Check DMA                                          Rev. 15-JAN-1993   *
*                                                                         *
***************************************************************************

***************************************************************************
*                                                                         *
*  Check DMA Section of the Cyclic Operation.                             *
*        This sections checks to see if a VBD DMA list cycle is running.  *
*        If one is running then this routine waits for it to either       *
*          finishe or else to time out.                                   *
*                                                                         *
*            Zero the DMA time out counter.                               *
*            Wait for the DMA to finish; increment the DMA time out       *
*               counter with each loop of testing the DMA status.         *
*            If the DMA times out then send a message to the 68020        *
*               terminal and continue. If it does not time out then       *
*               when the DMA is finished just return to the calling       *
*               routine.                                                  *
*                                                                         *
*                                                                         *
*  Control of the Trouble Warning Bits                                    *
*        If the DMA cycle times out then set the TWB #1  i.e. the DMA     *
*          Cycle timed out TWB.  If the DMA Cycle completes OK then       *
*          make certain that this Trouble Warning Bit is cleared.         *
*                                                                         *
*                                                                         *
*  Control of the State Bits                                              *
*        During the period of time that this routine is waiting for the   *
*          VBD to finish running its DMA list keep the State Wait DMA     *
*          set.  This state is only set while we are actually waiting     *
*          for the VBD to finish its DMA list.                            *
*                                                                         *
***************************************************************************

*************************************************************************
*       This section defines program-specific macros:                   *
*                                                                       *
*            WRIO:  Write bit(s) to the IRONICS I/O card                *
*                                                                       *
*************************************************************************

WrIO    MACRO                             ; Write byte to Ironics I/O Port.
        NOT.B   \1                        ; Complement data byte \1.
        MOVE.B  \1,\2                     ; Move to Ironics port at adrs \2.
        ENDM


***************************************************************************
*                                                                         *
*  Check DMA Section of the Cyclic Operation.                             *
*                                                                       *
*************************************************************************

Begin_Check_DMA   Move.B  #StateWaitDMA,StatePortAdrs

                                          ; Set the State Bit to indicate that
                                          ;   we are waiting for the VBD to
                                          ;   finish running its DMA list.

         Move.L  WaitDMATime,D4           ; Initialize the register to wait
                                          ;  for the DMA cycle to finish.

ChkDMA   CLR.L   D0                       ; Clear all bits in data reg 0.
         Move.W  VBDCSR2,D0               ; Move the VBD CSR2 into D0.
         And.L   MskDMARunning,D0         ; Mask all but the CSR2 bits that
                                          ;   indicate if either VBD buffer is
                                          ;   currently running a DMA cycle.

        BEQ     NCycExit                  ; If DMA status is zero then neither
                                          ;   VBD Buffer is runniong a  DMA
                                          ;   cycle has finished.
                                          ;   Jump to the normal exit
                                          ;   processing.

        SubI.L  #$1,D4                    ; DMA cycle has not finished.
                                          ;   Decrement its time out counter.
        BNE     ChkDMA                    ; Not timed out, check status again.


                                       ; If we reach here then we have
                                       ;   waited too long for the VBD
                                       ;   DMA cycle to finish.

        Move.B  TWBData,D0             ; Set the VBD DMA Cycle Timed Out bit
        OrI.B   #$02,D0                ;   in the Trouble Warning Bits to
        Move.B  D0,TWBData             ;   flag the problem for monitoring.
        WrIO    D0,TWBPortAdrs         ;   Send the new TWB's out their port.

        PEA.L   GiveUpDMA              ; Timed out, Push message on stack.
        JSR     ChrStrgOut             ; Display VBD DMA time out message.

        Move.B  #AllBitsLow,StatePortAdrs    ; Clear the Waiting for DMA
                                             ;   state bit and then exit.

        RTS                            ; Return to the calling routine.



NCycExit   Move.B  #AllBitsLow,StatePortAdrs   ; We are finished waiting for
                                               ; VBD DMA Cycle to complete so
                                               ; clear all of the state bits.

        Move.B  TWBData,D0             ; Clear the VBD DMA Cycle Timed Out
        AndI.B  #$FD,D0                ;   bit in the Trouble Warning Bits.
        Move.B  D0,TWBData             ;   We have finished the DMA cycle
        WrIO    D0,TWBPortAdrs         ;   OK so there is not DMA time out.

        RTS                            ; Return to the calling routine.



*************************************************************************
*  Define Constants:                                                    *
*                                                                       *
*  Data used to send messages to the 68k terminal screen.               *
*                                                                       *
*************************************************************************

              ALIGN   4                ; Align to Longword Address.


GiveUpDMA     DC.B    35,$0D,$0A,'The VBD DMA cycle has timed out.',$0A


*************************************************************************
*  Define Constants:                 External References                *
*                                                                       *
*************************************************************************

       XDEF   Begin_Check_DMA                       ; Export this symbol
                                                    ; to other modules.

       XREF   ChrStrgOut                            ; Symbols referenced
       XREF   MskDMARunning                         ; in this program
       XREF   StateWaitDMA                          ; module but defined
       XREF   VBDCSR2                               ; in another module
       XREF   WaitDMATime                           ; Main_Symbols.Include
       XREF   AllBitsLow
       XREF   StatePortAdrs
       XREF   TWBPortAdrs
       XREF   TWBData


       END

