
Cycle_Master   IDNT                            ; Title of  Cyclic Section

   SECTION   Sect_Cycle_Master,4,C       ; Declare a noncommon code section.
                                         ; Align to Longwords.

***************************************************************************
*                                                                         *
*   Cycle Master  Event by Event Processing            Rev. 16-MAR-1993   *
*                                                                         *
***************************************************************************

*****************************************************************************
*                                                                           *
*  Cycle Master   Event by Event Cyclic Operation section.                  *
*                                                                           *
*                                                                           *
* 1.  VTC sets up the buffers so that C1 and V1 are ready for loading       *
*       and C2 and V2 are ready for reading,  i.e. C1L, V1L, C2R, V2R.      *
*       (This step is done by the Init_Hard_Soft routine and is done        *
*       again in the Init_Pulser routine.)                                  *
*                                                                           *
* 2.  VTC waits for either the Start Jet List signal or else the Slave      *
*       Ready signal and then it Reads the Vertical Interconnects           *
*       into V1.  COMINT will be building a Data Block in C1.               *
*                                                                           *
* 3.  VTC waits for the COMINT Data Block Builder to finish building in C1. *
*                                                                           *
* 4.  VTC verifys that the VBD is finished runing its DMA List. There is a  *
*       time out around this step if the DMA cycle does not appear to end.  *
*                                                                           *
* 5.  VTC swaps buffers to new state:  C1R, V1R, C2L, V2L.                  *
*                                                                           *
* 6.  VTC sends the Data Cable Driver Finished Signal.                      *
*                                                                           *
* 7.  VTC Prepairs the Data in C1 and V1.                                   *
*                                                                           *
* 8.  VTC runs the Error_Checking routine to verify that the L1             *
*       Data Block is in good condition.                                    *
*                                                                           *
*     Skip step #9 if the Transfer-Event flag is not set.                   *
*                                                                           *
* 9.  VTC looks for and finds a free VBD buffer and starts it Running       *
*       the DMA List.  The VBD is reading from C1 and V1.  There is a       *
*       time out if VTC can not find a free VBD buffer.                     *
*                                                                           *
* 10. VTC waits for either the Start Jet List signal or else the Slave      *
*       Ready signal and then it Reads the Vertical Interconnects           *
*       into V2.  COMINT will be building a Data Block in C2.               *
*                                                                           *
* 11. VTC waits for the COMINT Data Block Builder to finish building in C2. *
*                                                                           *
* 12. VTC verifys that the VBD is finished runing its DMA List. There is a  *
*       time out around this step if the DMA cycle does not appear to end.  *
*                                                                           *
* 13. VTC swaps buffers to new state:  C1L, V1L, C2R, V2R.                  *
*                                                                           *
* 14. VTC sends the Data Cable Driver Finished Signal.                      *
*                                                                           *
* 15. VTC Prepairs the Data in C2 and V2.                                   *
*                                                                           *
* 16. VTC runs the Error_Checking routine to verify that the L1             *
*       Data Block is in good condition.                                    *
*                                                                           *
*     Skip step #17 if the Transfer-Event flag is not set.                  *
*                                                                           *
* 17. VTC looks for and finds a free VBD buffer and starts it Running       *
*       the DMA List.  The VBD is reading from C2 and V2.  There is a       *
*       time out if VTC can not find a free VBD buffer.                     *
*                                                                           *
* 18. Go to step 2.                                                         *
*                                                                           *
*                                                                           *
*****************************************************************************


*************************************************************************
*                                                                       *
*  Cycle Master   Event by Event Cyclic Operation section.              *
*                                                                       *
*                                                                       *
*************************************************************************


                     ALIGN   4                ; Align to Longword Address.


Begin_Cycle_Master  JSR  Begin_Wait_Start_Read

                    JSR  Begin_Check_DMA

                    Move.B  #$EE,Ironics_Port_5     ; $EE is the invert of $11
                                                    ; Enable C1R,V1R,C2L,V2L
                    JSR  Begin_Signal_Finished

                    JSR  Begin_Prepair_Data

                    JSR  Begin_Error_Checking

                    IF.L  TransEvent <EQ> #0  THEN.S   ; If the Transfer-Event
                      JMP  NextEvent2L                 ;   flag is not set for
                    ENDI                               ;   this event then do
                                                       ;   NOT transfer to L2.
                    JSR  Begin_Find_Start_VBD



NextEvent2L         JSR  Begin_Wait_Start_Read

                    JSR  Begin_Check_DMA

                    Move.B #$DD,Ironics_Port_5      ; $DD is the invert of $22
                                                    ; Enable C1L,V1L,C2R,V2R
                    JSR  Begin_Signal_Finished

                    JSR  Begin_Prepair_Data

                    JSR  Begin_Error_Checking

                    IF.L  TransEvent <EQ> #0  THEN.S   ; If the Transfer-Event
                      JMP  Begin_Cycle_Master          ;   flag is not set for
                    ENDI                               ;   this event then do
                                                       ;   NOT transfer to L2.
                    JSR  Begin_Find_Start_VBD


                    JMP  Begin_Cycle_Master    ; Return to the step where we
                                               ;   wait for an event to load
                                               ;   buffer #1.




*************************************************************************
*  Define Constants:                 External References                *
*                                                                       *
*************************************************************************

       XDEF   Begin_Cycle_Master                    ; Export this symbol
                                                    ; to other modules.

       XREF   Ironics_Port_5                        ; Symbols referenced
       XREF   Begin_Wait_Start_Read                 ; in this program
       XREF   Begin_Check_DMA                       ; module but defined
       XREF   Begin_Signal_Finished                 ; in another module
       XREF   Begin_Prepair_Data                    ; Main_Symbols.Include
       XREF   Begin_Find_Start_VBD
       XREF   TransEvent
       XREF   Begin_Error_Checking

       END

