/* Program: mem_time_fpga.c Revision: 8-Feb-2025 This is the program to calculate the signal delays between the FPGA Memory Controller and its DDR4 Memory Chips. This program uses the following input files: aux_fpga_memory_routing_data_packed.txt mem_fpga_2d_trace_lenghts.txt package_delays_all_columns_bank_0_ordered_packed.txt These 3 files are each 71 lines long and each of them has information about 71 signals all in the same net name order. These 3 files contain no blank lines or comments. Notes: - all Lengths are in mm all Delays are in psec - Because of the different propagation velocities along these signal paths, all of the delays must be summed in terms of time (not in terms of physical path length) - At the end, the time error in a signal path is converted back into the equivalent physical length using the propagation velocity for a PCB layer where it is possible to make a routing adjustment. - For now I will assume that the propagations delays of the various PCB layers are: Surface Layer: Dk = 3.45 ---> 6.19 psec/mm Internal Layer: Dk = 3.59 ---> 6.32 psec/mm Via Internal Path: Dk = 4.00 ---> 6.66 psec/mm Recall that 1/c is 3.33 psec/mm - From the package_delays_all_columns_bank_0_ordered_packed.txt file this program learns the time delay from the FPGA Memory Controller to the individual Pins on the FCG1152 package. These delays expressed in psec are in the 10th column of this file. - From the mem_fpga_2d_trace_lenghts.txt file this program learns the 2d X,Y path length for all of the FPGA memory signals. These path lengths are expressed in mm and are in the 2nd column of this file. - From the aux_fpga_memory_routing_data_packed.txt file this program learns: The Fraction of the PCB signal path that is routed on a surface layers (vs an internal layer) This fraction ( 0.00 to 1.00 ) is in Column #3 The length of the signal path in the FPGA BGA Escape Via, i.e. the vertical distance from top layer L1 down to whatever layer this signal is routed on next. This length in mm is in Column #4. The length of the signal path in the Re-Surface Via by the memory chip pin, i.e. the vertical distance from what ever layer the signal is on up to the top layer L1. This length in mm is in Column #5. The length of the signal path in a 3rd Via if a 3rd Via is used in this signal path, i.e. the vertical distance between the incoming signal layer and the out going signal layer. This length in mm is in Column #6. - Until we know the details of the DK Stackup I will assume: L1 Top Traced & Pads 0.000 mm 0.00 mils L2 Ground Plane 0.123 4.85 L3 Traces 0.284 11.20 L4 Traces 0.640 25.20 L5 Ground Plane 0.801 31.55 L6 1 oz Power Fills 0.930 36.60 --- Center 41.3 mils 1.049 mm L7 1 oz Power Fills 1.168 46.00 L8 Ground Plane 1.297 51.05 L9 Traces 1.458 57.40 L10 Traces 1.814 71.40 L11 Ground Plane 1.975 77.75 L12 Bot Traced & Pads 2.098 82.60 - Based on the above copper layer locations, the distances between routing layers are: L1 L3 L4 L9 L10 L12 L1 ---- L3 11.2 ---- all in mils L4 25.2 14.0 ---- L9 57.4 46.2 32.2 ---- L10 71.4 60.2 46.2 14.0 ---- L12 82.6 71.4 57.4 25.2 11.2 ---- L1 L3 L4 L9 L10 L12 L1 ----- L3 0.284 ----- all in mm L4 0.640 0.356 ----- L9 1.458 1.173 0.818 ----- L10 1.814 1.529 1.173 0.356 ----- L12 2.098 1.814 1.458 0.640 0.284 ----- - The basic calculations that this program does are the following: First calculate the total delay time in psec for each of the 71 signals. A given signal's total delay time is the sum of its: Package_Delay + XY 2d Trace Length x Fraction on Surface x Surface Layer Propagation Constant + XY 2d Trace Length x ( 1.0 - Fraction on Surface ) x Internal Layer Propagation Constant + ( the sum of its Via Lengths ) x Via Propagation Constant Next for each of the 5 groups of signal we calculate the Group Average Delay time for that group in psec. The 5 groups are: The CA Bus 25 signals and a Differential Clock D0:D7 Data Bus 9 signals and a Differential Strobe D8:D15 Data Bus 9 signals and a Differential Strobe D16:D23 Data Bus 9 signals and a Differential Strobe D24:D31 Data Bus 9 signals and a Differential Strobe But note that the Clock and Strobe signals themselves are NOT included in calculating the Group Average Delays. This makes sense because the Group Average Delays should be calculated based just on the data type signals in that group and then the clock signal for that group should match that average and not an average that has been skewed by the clock signal itself. There are 71 signals total for which we need to make a timing analysis. The Reset_B, Alert_B, and TEN signals are not part of the timing analysis. Finally for each of the 71 signals calculate its error in psec relative to the average delay for the signals in its group. Express this error both as a time in psec and as a distance in mm on the PCB layer where this signals physical routing length could be adjusted. - There are a number of source files that are combined into into the overall source for this program when it is built. These source files are: mem_time_fpga_introduction.c mem_time_fpga_read_files.c mem_time_fpga_calculate_delays.c mem_time_fpga_output_differences.c - The order of these 71 memory signals in all three of the files that are inputs to the delay calculation program is the following. This is the same for both the FPGA memory data and for the CPU memory data. The Line Number in a file starts at "1". The Element Number of C Array starts at "0". File Line Numb Signal ---- --------- 1 CLK_DIR 2 CLK_CMP 3 CLK_ENB 4 ADRS0 5 ADRS1 6 ADRS2 7 ADRS3 8 ADRS4 9 ADRS5 10 ADRS6 11 ADRS7 12 ADRS8 13 ADRS9 14 ADRS10 15 ADRS11 16 ADRS12 17 ADRS13 18 ADRS14_WE_B 19 ADRS15_CAS_B 20 ADRS16_RAS_B 21 BA0 22 BA1 23 BG0 24 CS_B 25 PARITY 26 ACT_B 27 ODT 28 DQS0_DIR 29 DQS0_CMP 30 DM0_B 31 DQ0 32 DQ1 33 DQ2 34 DQ3 35 DQ4 36 DQ5 37 DQ6 38 DQ7 39 DQS1_DIR 40 DQS1_CMP 41 DM1_B 42 DQ8 43 DQ9 44 DQ10 45 DQ11 46 DQ12 47 DQ13 48 DQ14 49 DQ15 50 DQS2_DIR 51 DQS2_CMP 52 DM2_B 53 DQ16 54 DQ17 55 DQ18 56 DQ19 57 DQ20 58 DQ21 59 DQ22 60 DQ23 61 DQS3_DIR 62 DQS3_CMP 63 DM3_B 64 DQ24 65 DQ25 66 DQ26 67 DQ27 68 DQ28 69 DQ29 70 DQ30 71 DQ31 */