Sony 1 Simulation
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.WIDTH IN=72 OUT=80
.OPT NODE
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* Power Supply for the JFET
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VCC 11 0 5
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* Sweep the input voltage from 0.1 MHz to 10 MHz in 100 steps.
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.AC LIN 100 0.1MEGHz 10MEGHZ
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* Voltage Source 5K Ohms
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VIN 1 0 AC 1
RS1 1 3  5K
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* Input Series L||C
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LSERIES1 3 4  0.82UH
CSERIES1 3 4     2PF
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* Second Series L||C
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LSERIES2 4 5  0.82UH
CSERIES2 4 5     3PF
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* Input Shunt L||R-C  Normal Operation
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LSHUNT1 5 9  220UH
RSHUNT1 5 9   10K
CSHUNT1 9 0   82PF
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* Input Shunt R-L-C  Added for Low Frequency Operation
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RSHUNT2 5 7  150
LSHUNT2 7 8   15UH
CSHUNT2 8 0  560PF
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* Series L||R
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LSERIES3 5 6  3.3UH
RSERIES3 5 6    1K
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* Gate Bias Resistor
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RBias1 6 0  470K
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* Source Follower JFET
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JFET1  10 6 12 MOD1
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* Drain Bypass Capacitors
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CBYPASS1  10 0  0.01UF
CBYPASS2  10 0    47UF
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* Drain Decoupling Resistor
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RDECOUP1 10 11  47
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* Source Load LR Series Circuit
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LSLOAD1 12 13  8.2UH
RSLOAD1 13 0   100
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* Source Follower Output Coupling Capacitor
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CCOUPLE1 12 14  0.01UF
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* Series L||C Circuit
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LSERIES4 14 15  0.82UH
CSERIES4 14 15    10PF
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* Shunt R||C Circuit
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CSHUNT4 15 0  82PF
RSHUNT4 15 0  10K
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* Series L||R||C Circuit
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LSERIES5 15 16    1UH
CSERIES5 15 16    1PF
RSERIES5 15 16  4.7K
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* Shunt L+C Circuit
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LSHUNT6 16 17  0.82UH
CSHUNT6 17  0     9PF
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* Load Measuring Resistor
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RLOADM1  16 18  100
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* Return the Cold End of Load to Ground  R||C
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CLDCOLD1 18 0  0.01UF
RLDCOLD1 18 0   2.2K
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*
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.MODEL MOD1 NJF   VTO=-2.0    BETA=1.0E-3    LAMBDA=1.0E-4     PB=0.6
+                  RD=50        RS=50           CGS=5PF       CGD=1PF
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.PRINT AC VM(16,18) VP(16,18)
.PLOT  AC VM(16,18) VP(16,18)
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.END