PMT Analog Design for the Signal Going Into the ADC ----------------------------------------------------- Initial Rev. 13-Feb-2023 Current Rev. 25-May-2023 The intent of this file is to collect information about and to describe the design of the analog circuits on the Disco board that carry the PMT signals from their connector at the edge of the Disco pcb to the analog input pins on the ADC. To understand the PMT analog circuits on the Disco board one also needs to understand the input stage of the ADC chip. Description of the PMT Analog Signal: ------------------------------------- Below are various descriptions that I've heard of the PMT signal shape and amplitude. All of these descriptions are probably ture in various situations. This whole subject of PMT signal shape is going to be cleaned up in the near future and information will be added about what information needs to be extracted from the PMT signal to enable Physics to be done. - One simple description is 10 nano Coulombs coming out of the PMT in a pulse that has a full width of 100 nsec. - Another description includes a smaller 2nd bump on the side of the main pulse described above. The main peak and 2nd smaller peak are typically separated by 30 nsec or more. The second bump comes from the tau decay. - Another description is that this 100 nsec full width pulse starts from about 5000 photo electrons total. - Another description is of a much smaller signal. To see these small signals we will need all of the 12 bit dynamic range of the ADC and all of the dynamic range of the PMT and need to control any crosstalk between channels on the DK board. - Another description is of a PMT signal that lasts for upto about 1 usec. This long signal has a rising edge of about the same rate and amplitude as the 100 nsec signal described above but then has a long slow falling edge that lasts upto 1 usec. 1 usec is the longest signal that P-ONE cares about. - Doing some quick simulations just now, we will sometimes saturate the phototubes on bright events, so we probably want to set the range for the electronics to match the full range of the tubes rather than worrying about physics. Per Hamamatsu, the PMT starts going significantly non-linear at an anode current of 30 mA. They don't quote where it actually saturates fully, and those lab tests haven't been done yet, but it probably is not too much higher -- the non-linearity more than doubles between 20 and 30 mA. Given that, I don't see too much point in going very much beyond 30 mA at the high end. Maybe ~ 40-50 mA to have some margin. - Our target is to have an SNR of ~ 10 on pulses from individual photons so that we can meet our timing requirements, which scale more or less as 5 ns / sqrt(12 * SNR) < 0.5 ns. I would like things to be a bit better than that to have some margin. Each photon should make ~ 150 uA of current at peak at our target gain with an LPF at ~ 100 MHz (making sure of this is something where it would be good to have a test circuit). If 40 mA is the ceiling, and we have a 12-bit ADC with internal noise slightly above 1 count, that should give an SNR of a bit above 15 on individual-photon pulses, which seems like everything fits together tightly. - The big 100 nsec signal is about 5000 photons arriving over the 100 nsec period. If each of these photons results in one photo-electron at the PMT cathode and if we need this to result in a 0.81 Volt pulse across a 50 Ohm load this will require about 16.2 mAmp of current to flow for about 100 nsec or about 1.62 nano-coulombs of charge. The required PMT gain is: 1.62 nano-Coulomb X 6.24 x 10E18 electrons / Coulomb ----------------------------------------------------------- 5000 original photo-electrons which gives a required PMT gain of 2 x 10E6 Note that a gain of 2 million is a rational value for the Hamamatsu R14374 R14689 PMT. - The smallest signal is one photo making I assume one photo-electron and if the resulting signal lasts for 6 nsec (which is the number that I've heard) and if the PMT gain is 2 x 10E6 then this 6 nsec long signal will have an amplitude across 50 Ohms of about 2.67 mV. 2 x 10E6 electrons X 1.60 x 10E-19 Colombs / electron ------------------------------------------------------------ 6 nsec gives a current of 53.4 uAmps or 2.67 mV across 50 Ohms. - At a PMT gain of 2 million the biggest signal is 0.81 Volts and the smallest signal is 2.67 mV which is a ratio of 303. If the biggest signal gives 4096 ADC counts then the smallest signal will give about 13 ADC counts. So we must design the Disco-Kraken to provice an ADC noise and cross-talk well below 13 counts. PMT to ADC Input Circuit Design to Recover 1/2 of the ADC's Dynamic Range: --------------------------------------- The PMT signal is a negative going signal that will arrive in a 50 Ohm environment. We need to flip over this negative going signal so that it causes positive going values to come out of the ADC. Flipping the polarity of the current pulse that comes out of the PMT is done with a transformer on the DK board in the input circuit of the fast PMT ADC. We also need to DC bias the input to the ADC so that we can use most of the ADC's overall dynamic range for the normal main now positive swing of the PMT signal. Using the recommended - nominal values of the differential input voltage to the ADC, i.e. the nominal Vmax is 1.8 Vpp and the recommended 0.7 V common mode at the input to the ADC, implies: Positive Full Scale is: +Vin = 1.15 V -Vin = 0.25 V Negative Full Scale is: +Vin = 0.25 V -Vin = 1.15 V Now to have 90% of the ADC's overall dynamic range for positive swings and 10% of the overall dynamic range for negative swings we want to set the DC Bias to 80% of the negative full scale swing. That is we want the quiescent DC bias at the input of the ADC to be: +Vin = 0.34 V -Vin = 1.06 V This DC Bias can be generated by the standing DC current that I understand is present in the inputs to this ADC. This current comes from the 1.1 V common mode that the ADC actively maintains at the input to its Input Buffer and the Rin = 381 Ohm on each side between the inputs to the ADC's Input Buffer and the input pin pair on the ADC chip. Using the recommended 0.7 V common mode at the inputs to the ADC chip results in a nominal standing current of about 1.05 mA on each side when there is zero differential input signal to the ADC. Using this standing input current and an input transformer with a split secondary the required DC Bias can be generated with 2 external resistors. The low side of both halves of the split secondary are clamped to AC ground with capacitors that span the required frequency range while maintaining a low ESR, i.e. low compared to the value of the resistors. The input transformer is a 1:1:1 toroidal unit so with a 50 Ohm input it provides a 1:2 voltage step up and thus requires a 200 Ohm termination. This termination is provided by the 381 Ohm series resistors on each side of the input and an external 272 Ohm AC termination. Two series 136 Ohm external resistors (coupled by a capacitor) in parallel with the two internal series 381 Ohm resistors provides the 200 Ohm termination from below the low frequency cutoff of the input transformer up to the 125 MHz 3dB cutoff of the ADCs input anti-aliasing filter. Specifications of the AD9083 ADC Analog Input Section: ------------------------------------------------------ Values shown are for 2.0 GSPS Page 4 Resolution: 12 bits min to 16 bits max Ofset Error: -0.86 min +0.33 typ +1.55 max % Full Scale Offset Matching: +0.75 typ +1.66 max % Full Scale Gain Error: -10 min +5.2 typ +20 max % Full Scale Gain Matching: +1.1 typ +3.7 max % Full Scale Offset Stability: 14.1 typ ppm/C Gain Stability: 0.2 typ ppm/C Voltage Reference Stability: 0.1 typ ppm/C <---- <---- Differential Input Voltage Range: 0.5 min 1.0 typ 2.0 max Vp-p Common-Mode Voltage (VCM) 0.5 min 0.7 typ 1.0 max V Common-Mode Input Series Resistance Rin typ Ohms (RIN6) Differential Input Termination 100 min 200 typ 2xRin max Ohms Resistance (RTERM) Differential Input Capacitance 0.35 typ pF Analog Full-Power Bandwidth 125 typ MHz Page 5 Rin = 8 kΩ/Kvti, where Kvti is proportional to the ADC front-end gain factor, Rin = 1000 Ohms for fS = 1 GSPS, Rin = 381 Ohms for fS = 2 GSPS. Use of EN_HP increases the SNR by 2.5 dB at an increased power dissipation. There is an adjustable parameter called "Backoff". Backoff is the reduction in front-end gain for increased linearity. So I understand that if you use Backoff then you need a larger input signal to obtain a full scale output from the ADC. Crosstalk 90 dB presumably this is chanel to channel presumably this is actually -90 dB Pages 6, 7 For a 2.0 GSPS sampling rate these pages show the ADC's performance at a number of settings of Backoff and EN_HP. Backoff = 0 Backoff = 3 Backoff = 6 Backoff = 0 EN_HP = 0 EN_HP = 0 EN_HP = 0 EN_HP = 1 ----------- ----------- ----------- ----------- NSF at 100 MHz fs/20 dB FS / Hz -145 -143 -140 -147 SNR DC to 100 MHz dB FS 66 64 61 69 SFDR/HD3 at fs/20 dBc -60 -63 -66 -60 IMD3 at fs/20 dBc -60 -63 -66 -60 These tables show that turning On EN_HP improves noise performance. But turning Up the Backoff seems to reduce noise performance. I do not understand Backoff, i.e. the opposite of note on page 5. NSD == Noise Spectral Density SNR == Signal to Noise Ratio SFDR/HD3 == Spurious Free Dynamic Range / Third Order Harmonic Distortion IMD3 == Third order Intermodulation Distortion Pages 17 : 24 All graphs under various conditions. Look at the 2 Gsps graphs. Figures 8 and 9 show that as the Backoff parameter is turned up: - Noise performance decreases this is "bad" - Harmonic Distortion decreases this is "good" Figure 13 shows better noise performance with a 2 Volt input than with a 0.5 Volt input (but what else was changed or adjusted ?) Figures 20 and 21 show the best Harmonic Distortion performance when using a Backoff of 6. Is this 6 dB ? Figures 44, 45, 46 show better Two Tone FFTs with a Backoff of 0 than with a Backoff of 6. That is the Backoff = 0 noise performance is better and its IMDs performance is better. Page 25 Figure 47 Important drawing of the Input Circuit. Page 27 NSD is the noise power normalized to 1 Hz bandwidth (at a particular frequency) relative to the full-scale of the ADC (dBFS). NSD is given in units of dBFS/Hz. IMD3 is a figure of merit used to quantify the linearity of a component or system. Two equal amplitude, unmodulated carriers at specified frequencies (f1 and f2) injected in a nonlinear system exhibiting third-order nonlinearities produce IMD components at 2f1 − f2 and 2f2 − f1. Page 28 The AD9083 ADC uses a first-order, CTSD modulator architecture that provides first-order quantization noise shaping and inherent first-order, sinc shaped, antialias filtering. This oversampling, combined with the inherent antialias filtering, eliminates thermal noise folding into the band of interest. This feature enables a fast signal settling time when compared to the settling time of Nyquist rate converters, which require highly selective antialias filters to eliminate noise folding. Built into the ADC front end is a programmable termination resistor, programmable gainadjust, and a programmable, single-pole, low-pass filter (LPF). A low power mode is available with a noise density increase of 3 dB for half the converter power. ADC in the AD9083 requires a set of user-defined variables that set up the ADC in the use case specified by the application. These variables are: fs, the sample clock of the converter core 1.0 GSPS to 2.0 GSPS Vmax, the differential peak-to-peak input full scale 0.5 V p-p, differential, to 2.0 V p-p, differential fc, the cutoff frequency of the LPF 125 MHz to 800 MHz Rterm, the differential input termination resistance finmax, the maximum input signal frequency Backoff, the reduction in front-end gain for increased linearity EN_HP, which increases the SNR by 2.5 dB by doubling the ADC power dissipation Figure 55 Important drawing of the ADC Circuit and its input. Page 29 "Description of the Low Pass Sigma-Delta ADC" Currently I have almost zero understanding of this page. This ADC is basically a VCO, that is sampled to make an accumulated phase measurement, this accumulated phase measurement is digital value, you make differences between adjacent measurements, that gives you the average frequency between adjacent measurements, and that tells you the value of the control voltage to the VCO. NSD == Noise Spectral Density VCO == Voltage Controlled Oscillator CTSD == Constant Time Sigma-Delta DDC == ??? FIR == Finite Impulse Response OSR == Oversampling Ratio NTF == ??? ICRO == Current Controlled Ring Oscillator Page 30 At signal frequencies below fs/64, the dominant noise source is white thermal noise. Above this frequency, the noise is dominated by shaped quantization noise rising at 6 dB/octave. At the maximum signal bandwidth of fs/16, quantization noise is the dominant noise source. Note that we want to work at fs/20. The analog input to the AD9083 is a differential buffer. The internal common-mode voltage of the buffer is 1.1 V when ac coupling. When dc coupling, the allowable (common-mode) level is 0.5 V to 1.0 V. The nominal Vmax level of the ADC is 1.8 V p-p differential. <---- This VMAX level is programmable from 0.5 V p-p to 2.0 V p-p. The inputs of the AD9083 are terminated using a programmable differential resistor. This differential resistor can be programmed to: 100 Ohms, 200 Ohms, or can be left open. Following the termination resistor is a programmable single-pole LPF. The maximum signal bandwidth of the AD9083 is 125 MHz (fs/16) for a 2 GHz ADC fs. The fc of the LPF can be programmed to be between 125MHz to 800 MHz to reduce input noise to the ADC. Differential Input Considerations: Word for Word repeat of text from page 28. Then Therefore, there is no need for an antialiasing filter in the front end. The inputs can be differentially coupled using a balun or transformer or an amplifier. The inputs can also be AC or DC coupled. Figures 58 : 61 showing transformer and opamp coupling and AC and DC coupling. They show 1:2 transformers and 100 Ohm internal termination - which must be a mistake. Page 31 CTSD modulator used in the AD9083 has some inherent antialiasing that lessens the antialias filtering requirements. The antialiasing property results from the signal processing inherent to the ADC architecture. The intrinsic STF of the ADC is that of a first-order sinc filter. Additionally, a single-pole, first-order, programmable LPF is integrated in front of the ADC. This filter is SPI programmable between the 125 MHz to 800 MHz bandwidth. The STF + LPF filtering at the front end reduces aliasing of undesired signals near the sample rate, fs. STF == ??? Input Common Mode: The analog inputs of the AD9083 are programmable resistors internally dc biased to 1.1 V. <---- The device typically expects a common-mode input of 0.5 V to 1.0 V with a nominal voltage of 0.7 V. <---- An internal reference loop automatically senses the input common mode and sources a current across the input resistor network to generate the appropriate common-mode level shift across each RIN (see Figure 64). The circuit driving the AD9083 must be able to sink this common-mode current. To set the value of the current use the following equation: Isink = ( 1.1 V - Vcm ) / Rin Note for values of Rin see page 5 Setting the device so that Vcm = 0.7 V is recommended <---- for optimum performance. However, the device can function over a wider range with reasonable performance. Input Termination A differential input termination can be enabled via the SPI register. This termination value can be either 100 Ohm, 200 Ohm, or high impedance. On-chip foreground calibration is performed after startup to reduce the device to device variation of resistor and capacitor values due to tolerances associated with the device process. This calibration improves the termination value tolerances, as well as the LPF tolerances discussed previously Input Signal Overload Unlike a traditional CTSD ADC, the AD9083 ADC saturates much like a flash converter. The ADC does not become unstable (as with a traditional CTSD ADC), and the recovery time is one clock cycle. <---- <---- Page 54 Programming Sequence to setup the ADC This mentions things like: fc: -3dB LPF cutoff frequency vmax: differential peak-to-peak input full-scale rterm: termination resistance en_hp: enable high performance mode backoff: dB backoff in terms of noise (dB value × 100) finmax: maximum input frequency, should be set to fADC/20 Page 56 Example list of ADC Parameters that need to be setup: Sample rate = 2 GSPS. On-chip PLL reference = ??? MHz. finmax = 100 MHz (sample rate/20). Low pass filter cut-off frequency (fc) = ??? MHz. Vmax = 2.0 V. ??? Rterm = 100 Ohm. EN_HP = 0. Backoff = 0 dB. ??? Mixer bypassed (real data). CIC decimator bypassed. Decimate by J = 8. ??? Output bandwidth = 100 MHz. Transport parameters L = 4, M = 16, F = 6, S = 1, K = 32, NP = 12 Each lane = 15 Gbps. ??? Page 61 Analog Devices SPI Registers Page 64 Digital Datapath Setup Registers Page 86 Temperature Diode Control Registers On-Chip PLL Configuration Registers Page 87 This page mentions 3 Registers that are used to program: FILT_MAIN_0 D_FILT_CBIG FILT_MAIN_1 D_FILT_R FILT_MAIN_2 D_FILT_CSMALL I think this all has to do with a PLL Loop Filter not with the analog input low pass filter. Page 88 G/H Sync Mode Control Registers Where are the registers to setup the analog part of the ADC ??? Tests of the AD9083 to Learn How It Works: ------------------------------------------ Most of these tests were done by: on one channel of the demo board just add flag wires at the actual ADC inputs so that you can see the actual input to the ADC (while also looking at its digital output with demo board software), on another channel remove the transformer, add a 500 Ohm resistor from each ADC input to Ground, and watch the DC value at the ADC input, this allows you to calculate the value of Rin for a given configuration. - Yes, BackOff just reduces the gain of the Input Buffer and then makes up for this loss by gaining up the backend digital section. Using a 6 dB BackOff drops the gain of the Input Buffer by about a factor of 2 (i.e. the ADC itself operates just in the middle 1/2 of its range) but the digital output from the overall ADC is unchanged because the digital value is multiplied by about a factor of 2 in the backend digital section. - Measurements of the ADC's Rin when operating at 1.6 GHz sample clock, Fc = 125 MHz, Fin_max = 125 MHz, BackOff = 0 dB, and High Performance Mode = Disabled. Measurements of Rin were made for different valuse of Vin_max using Channel 5 which had its transformer removed and two 499 Ohm resistors tied between ground at that channel's ADC input. Specified Standing Vin_max Ch 5 Rin Current Volts Volts Ohms mA --------- ----- ---- -------- 2.0 0.418 814 0.8377 1.9 0.418 814 0.8377 1.8 0.443 740 0.8878 1.7 0.443 740 0.8878 1.6 0.466 679 0.9339 1.5 0.487 628 0.9760 1.4 0.507 584 1.0160 - Rin appears to be independent of the value of Fc and weakly dependent on the specified vaule of Fin_max. The data sheet says that the RC circuit at the input of the AD9083 can provide an Fc between 125 MHz and 800 MHz but the Demo board software lets you specify Fc values down to 100 kHz or lower. With standard values of the other Rin controlling parameters, I adjusted FC over the range of 100 kHz to 800 MHz and saw no change in the value of Rin, i.e. in the value of the voltage drop across the 499 Ohm resistors between ground and the inputs to the Channel 5 ADC remained constant. Specifying a value for Fc that is even just one Hz higher than 800 MHz causes the demo board software to cry out tilt but the software lets you specify values below 125 MHz without a complaint. With the Rin controlling parameters at their standard values (1.6 GHz sample, 1.8 Vmax, 0 dB Backoff, HP Mode Off, Fc 125 MHz) I adjusted Fin_max and saw the following variation in Rin: Fin_max 100 kHz to 105 MHz Rin = 628 Ohm (0.487 V Ch 5) Fin_max 106 MHz to 115 MHz Rin = 679 Ohm (0.466 V Ch 5) Fin_max 116 MHz to 125 MHz Rin = 740 Ohm (0.443 V Ch 5) This dependance of Rin on the value of Fin_max makes no sense - why should there be any dependance and why have more gain a lower values of Fin_max. Why do they care about Fin-max at all in the first place in the mode that we are using this ADC ? Standard DK Board Setup of the AD9083 ADC: ------------------------------------------ fs, sample clock of the converter 1.6 GHz Vmax, maximum differential input voltage 1.8 V fc, cutoff frequency of the analog LPF 125 MHz Rterm, internal input termination Open finmax, maximum input signal frequency 120 MHz Backoff, reduce buffer gain add digital gain 0 dB EN_HP, enable High Performance mode Disable CIC, Bypass the CIC back end section Yes Decimation, total overall decimation 8 JTX Subclass 0 Lanes L = 4 Virtual Converters M = 16 (Octets/Frame)/Lane F = 6 Bits Packed NP = 12 Resolution Bits N = 12 Frames in a Multi-Frame K = 32 (Samples/Converter)/Frame S = 1 Lane Line Rate 12 Gbps Pulse Transformer: ------------------ The required pulse transformer for this circuit must have a low loss frequency range from under 0.5 MHz (i.e. we need good fidelity for pulses lasting as long as 1 usec) up to above 100 MHz (the Niquest cutoff for the ADC is at 104 MHz. The transformer needs to have a single winding primary setup to work with a 50 Ohm input and a split winding secondary so that we can separately control the DC Bias to both sides of the ADC's differential analog input. Murata: 78601/4JC or 78601/3JC MiniCircuits: T-622-KK81+ or T2-613-1-KK81+ The first 3 of these transformers have 1:1:1 windings so their differential output will be twice the amplitude of their single-ended coax input. The T2-613-1-KK81+ transformer has 1:1:2 windings. If used its "2" winding would be the single-ended input and its two 1:1 windings would be the differential output at the same differential level as the single-ended input. The pinout and foot prints of these transformers are basically the same so that selection could be made even post layout. Other PMT Input Circuit Questions and Issues: --------------------------------------------- - We may need or want to include a coaxial chokes or baluns at the PMT signal inputs to the DK board. - An associated issue is do we connect the shields from the 16 PMT coax cables to the ground plane on the DK board. - Also involved with this is the capacitive coupling through the 1:1:1 split secondary transformer, i.e. how balanced is its output and how free of common mode is its output. - There is the question of does the AD9083 have any common mode rejection in our frequency range of interest. The data sheet for the AD9083 says nothing about the common mode rejection of its differential inputs. - There is the posibility of using the Vin_max parameter for the AD9083 to adjust the DC Offset value of its digital output. AD9083 Clock Type Inputs: Clk, SysRef, Trig, SyncInb: ------------------------------------------------------- Information on various pages of the AD9083 datasheet: - 10 Specification Table for the various clock type inputs Typ 700 mVpp input, 0.5 V Common Mode supply is built in, 100 Ohm internal terminator, stated LVDS compliance - 14, 15 Pinout table and diagram - 25 Clk, SysRef, and Trig Equivalent Input Circuit, 100 Ohm fixed input terminator, 172k Ohm each side to a 0.5 Volt common mode supply - 26 SyncInb Equivalent Input Circuit, can run differential or single-ended high Z - 32 Description of the Clk input signal and requirements, recommend AC coupled input, "improved phase noise performance can be achieved with a higher clock input level", I assume that the recommended AC coupling and the built in 0.5 V common mode supply means that 0.5 V is the optimum common mode - but it must also work OK at 1.2 V for use with LVDS - 46 Some description of the SYNCINB input - 51 Some description of the SysRef input