AD9546 Timing Generator Notes ------------------------------- Initial Rev. 2-July-2023 Current Rev. 20-Nov-2023 Reader's Guide to the AD9546 data sheet: Block Diagram pg 6 Pin Diagram 39 Theory of Operation starts 40 Mx Reference Clocks Inputs 48 Input Circuits 49 Clock Output Circuits 50 Analog Loopback 71 System Clock (not Ref Clk) 74 Reference Clock Receivers 77 Outputs 91 Auxiliary NCOs 162 Auxiliary NCO Output 165 Mx pins 180 Mx pin control of power up 180 The Analog Loopback section starting on page 71 give a description of a 3 chip system, a master with 2 slaves, where it wants the output signals of the slaves to all be synchronous and be synchronous with the reference to the master. The AD9546 provides a high degree of backward compatibility with the AD9545, but with enhancements to support digitized clocking. Terminology: Pg 47 -------------------- Time Base - is a frequency source, the period of which denotes the passage of time. Time Scale - is the accumulation of the periods of a time base. A time scale allows identifying a particular instant as having a particular time value. The starting point of a time scale (its epoch) is arbitrary. Epoch - is the starting time associated with a time scale. For example, the epoch of the UTC time scale is midnight, January 1, 1970. Time Stamp - in the context of the AD9546, time stamp is a digital (numeric) time value with an arbitrary epoch suitable for internal device usage. Time Stamps are based on the System Clock. Time Code - in the context of the AD9546, time code is a time stamp with a defined epoch suitable for general usage by other AD9546s external to the AD9546 that created the Time Code. Time Codes are based on the Common Clock. Theory of Operation: Pg 48 ---------------------------- Input/Output Termination Recommendations: Pg 49 ------------------------------------------------- Digitized Clocking: Pg 52 --------------------------- I do not fully understand this but in general it seems like implementing a "Digitized Clocking System" requires a periodic Synchronization input to the AD9546s in a system along with loading into each AD9546 the "time" associated with each "Synchronization Trigger". I believe that this is all part of setting up a common To fom the Common Clock and involves the Common Clock Synchronizer block. I believe that this process of establishing a To in each AD9546 in an overall system involves a synchronization input, synchronization trigger, which I believe is (or can be) carried by phase modulation on the falling edge of the Common Clock. In some sence establishing this Common Clock and an appropriate To in each AD9546 may just be called seting up a common Epoch on all of the AD9546. The Common Clock DPLL and the Common Clock Synchronizer are complicated, I do not fully understand them, they appear to be critical to implementing a "Digitized Clocking System" and I do not know how much of these block are actually used in the clock setup that Nathan is planning. Common Clock DPLL (CCDPLL): Pg 56 ------------------------------------ The purpose of the Common Clock DPLL is to produce a Local Time Scale. The Common Clock DPLL uses the System Clock for internal timing, but the phase locks to a Reference Time Base, i.e. the Common Clock Reference. The output of the Common Clock DPLL is the Local Time Scale, which constitutes the accumulated period of cycles of the Common Clock Reference and provides an internal sense of time for the Digitized Clocking components. The CCDPLL embodies most of the hardware associated with the auxiliary DPLL (see the Compensation Method 3 subsection of the System Clock Compensation section). However, the CCDPLL incorporates additional enhancements to the auxiliary DPLL hardware to meet the needs of a digitizedclocking system. The CCDPLL takes are Inputs: the approximately 25 MHz "Core Clock" that comes directly from the System Clock via division by 96 and Time Stamps from the Physical Clock Converter that receives the Reference for the Common Clock. The output of the CCDPLL is the Local Time Scale which is Common Clock Synchronizer (CCS): Pg 59 ----------------------------------------- The common clock synchronizer provides a precision method for assigning an epoch to the local time scale yielding the common time scale. Essentially, the user provides a synchronization trigger event, the rising edge of an external analog input signal, which the device time stamps. The time stamp serves as an internal trigger event. Immediately following the trigger event (and before the next trigger event), the user programs the device with a time code corresponding to the time associated with the trigger event and asserts an IO update, which aligns the common time scale with the programmed time code. In this way, the common time scale carries the proper time. By carrying out the synchronization process across all nodes (with a distributed common clock as the time base for every node) and properly accounting for time delay in the system, the common time scale of every node increments at the same rate and carries the same epoch. Thus, all nodes are time aligned to a high degree of precision. User Time Stamper (UTS): Pg 65 --------------------------------- A User Time Stamper (UTS) converts internal Time Stamps to "Time Codes" (numeric time values based on the Common Time Scale) and provides the user with a means to read these Time Codes. The Time Stamps arrive, e.g. from the TDCs in the Physical Clock Converters, in terms of the System Clock i.e. the clock based on the X0A and X0B inputs. Because Time Codes relate to the Common Time Scale, the User Time Samper provides a means to export a digitized clock signal to remote digitized clocking nodes. Inverse User Time Stamper (IUTS): Pg 69 ------------------------------------------ An IUTS provides the user with a means to send a digital clock signal to a node (a digital clock signal being a continuous series of uniformly increasing numeric time codes). An IUTS converts the digital clock signal to time stamps (based on the common time scale), which can be distributed internally as needed. Analog Clock Loopback (Measurement of the Round Trip Delay): Pg 71 --------------------------------------------------------------------- This is described starting on page 71. Note that the Analog Loopback only works with the REFB-REFBB inputs to the device so the Common Clock reference needs to be connected to REFB- REFBB. As shown the Analog Loopback uses the M4 pin as the output from the device to return a sample from the Slave AD9546 to the Master AD9546. Their drawings so a network connecting the processors together that are connected to the SPI ports on the Master AD9546 and the multiple Slave AD9546 but their scheem for measuring RTD does not seem to use the connection between processors. At many levels I do not understand their description of their Analog Loopback. I thought that the main point of the AD9546 was to implement a "Digitized Clocking System" and that the main point of a Digitized Clocking System was to eliminate the nead for Analog Loopback paths and replace it with digitized network connections. I thought that a main point of the AD9546 was to setup a Common Clock Time Scale with a common To. Note that if the Common Clock Reference Frequency is faster than the RTD (which ours will be, i.e. > 100 MHz and RTD about 10 usec) then measuring RTD by Analog Loopback, "is beyond the scope of this data sheet". System Clock PLL: Pg 74 ------------------------- The System Clock is used by the chip's: Time to Digital Converters to generate Time Stamps The System Clock is the time base for the Numeric Controlled Oscillators that generate the Output signals from the AD9546, The System Clock is one of the two clock inputs that the Common Clock DPLL uses to generate the local Time Scale. Page 169 says, "The NCOs and the TDCs of the AD9546 derive their timekeeping from the system clock". "Therefore, the frequency accuracy of any of the NCOs relates directly to the accuracy of the System Clock. Likewise, an inferred frequency based on the difference between successive TDC time stamps is subject to the accuracy of the System Clock. Therefore, the stability of the System Clock is crucial to the accuracy of the NCOs and TDCs within the AD9546". The System Clock is controlled by the external crystal resonator or the external clock source, e.g. a crystal oscillator. - The AD9546 synthesizes its system clock via a system clock PLL that upconverts the frequency applied to the system clock input pins, XOA and XOB. The system clock input pins accept frequencies from 20 MHz to 300 MHz from an external clock source. Alternatively, the user can connect a crystal resonator (25 MHz to 80 MHz) directly across the XOA and XOB pins. The output of the system clock PLL is the primary time base for time keeping functions within the AD9546. - The system clock PLL typically uses an external crystal resonator as a frequency source, which tends to offer optimal overall phase noise performance. The system clock PLL synthesizes a high frequency internal system clock signal (~2.4 GHz) from the external frequency source, which provides the basic internal timing for the device. The TDCs of the device use the system clock to generate time stamps (see the Time to Digital Converter (TDC) section). Note that the internal system clock signal is one of the two frequency sources the common clock DPLL component uses to generate the local time scale. - System Clock PLL Overview page 74 The system clock PLL (see Figure 57) comprises an Integer N frequency synthesizer with a fully integrated loop filter and VCO. The VCO output is the AD9546 system clock with a frequency range of 2250 MHz to 2415 MHz. The XOA and XOB pins constitute the input to the system clock PLL to which a user connects a clock source or crystal resonator Proper operation of the AD9546 requires the user to declare the input reference frequency to the system clock PLL by programming the 40-bit unsigned integer in Bits[39:0] of Register0x0206 to Register 0x0202. The programmed value constitutes the nominal frequency, in units of mHz, applied to the XOA and XOB pins. The AD9546 evaluation software frequency planning wizard calculates this value for the user. I believe that the actual circuit is: The external XOA,XOB signal is either divided by: 1, 2, 4, 8 or multiplied by 2 (available only in the external crystal resonator "path" and then this signal is applied to the System Clock phase detector. The System Clock VCO must run between 2250 MHz and 2415 MHz. The feedback divider from the System Clock VCO output to the system Clock phase detector is set to an integer between 4 and 255. It does not look like they reguire a divide by 2 right in front of the System Clock Phase Detector or maybe that is built into the System Clock Phase Detector so that they do not mention it. - Degraded phase noise performance typically occurs when the frequency at the input of the PFD of the system clock PLL is less than 50 MHz. For optimal phase noise performance, use the quartz crystal resonator path with a crystal resonator frequency ≥ 50 MHz, the frequency doubler enabled, and the device configured to use system clock Compensation Method 3 (see the System Clock Compensation section). Page 75. - Analog Devices, does not guarantee the operation of the AD9546 with these crystals, nor does Analog Devices endorse one crystal supplier over another. The AD9546 reference design uses a readily available high performance 49.152 MHz crystal with low spurious content. Page 74. - I believe that the proposed 52 MHz crystaal resonator is a bad choice - it operates the System Clock VCO near either its lower or upper frequency limit. Recall that the VCO range is 2250 MHz to 2415 MHz, i.e. a range of 165 MHz, with its center at 2332.5 MHz. 52 MHz with the doubler gives 104 MHz. 104 MHz reference to the System Clock phase detector gives a VCO frequency of 2288 MHz when used with a divider value of 22. This is close to the 2250 lower limit of the VCO. It is about 23% up from the bottom edge of the VCO range. 104 MHz reference to the System Clock phase detector gives a VCO frequency of 2392 MHz when used with a divider value of 23. This is close to the 2415 upper limit of the VCO. It is about 86% up from the bottom edge of the VCO range. A better choice is 53 MHz crystal resonator, 106 MHz after the Doubler, 2332 MHz from the VCO when used with a divider value of 22. 2332 MHz is 49.7% up from the bottom edge of the VCO range, i.e. right in the center. Their proposed 49.152 MHz crystal resonator gives 98.304 MHz after the Doubler. With a divider value of 24 this gives a VCO frequency of 2359.296 MHz which is 1.15% above the center of the VCO range. If we want to be rational and operate the VCO in the center 1/3 of its range, i.e. operate it in the range 2305 MHz to 2360 MHz then the external crystal resonator should be: Feedback Crystal Crystal Divider with Doubler Oscillator -------- ----------------- ----------------- 22 52.386 - 53.636 104.773 - 107.273 23 50.109 - 51.304 100.217 - 102.609 24 48.021 - 49.167 96.042 - 98.333 15 76.833 - 78.667 153.667 - 157.333 So either a 78 MHz crystal resonator with the Doubler or a 156 MHz crystal oscillator, operating with a feedback divider of 15 will give a VCO frequency of 2340 MHz which is 54.5% up from the bottom edge of the VCO's range. The interesting feature of using a the 78 / 156 MHz reference for the System Clock is that it can directly make a 26 MHz clock for the USB and Bluetooth. System Clock and its derivatives: - Whatever you put in on pins X0A - X0B it gets multiplied up to the range 2250 MHz - 2415 MHz and that is the System Clock. But there are 3 other forms of the System Clock that are used by various blocks in the AD9546: - DIGCLK which is just System Clock divided by 3 about 800 MHz - CORECLK which is just DIGCLK divided by 32 about 25 MHz - TDC Time Scale which is ?? DIGCLK, CORECLK, and TDC Time Scale are all 3 used by the TDCs in the Physical Clock Converters. Reference Clock Input Resources: Pg 77 ---------------------------------------- Be careful - there are a bunch of separate "reference clocks" used in this system. In general I think that they use the name "Reference Clock" to mean the reference for the Common Clock. Reference Receivers: Pg 78 ---------------------------- Reference Dividers (R Dividers) Pg 80 ---------------------------------------- The primary purpose of the Rx dividers is to reduce the input reference frequency (assuming it is greater than 200 kHz) to a value between 1 Hz and 200 kHz to satisfy the input frequency bounds of the TDC. The TDC can not generate more than 200k Time Stamps per second - so the Reference Clock must be divided by a big enough R to bring it down below 200 kHz. Reference Monitor: Pg 81 -------------------------- Reference Demodulator: Pg 87 ------------------------------ aka Embedded Clock Demodulator Page 73 and on Page 87 this block is called a Reference Demodulator. The Demodulator is part of the Physical Clock Converter. On its associated Reference Input the Demodulator looks for and detects clock cycles that have phase modulation on the falling edge of the clock signal. That is the Demodulator looks for special cycles of the Reference Clock that haave been "painted red" by phase modulation on their trailing edge and once detected it can cause the associated divid by R circuit to be reset (also called synchronized) and it can cause the associated TDC to generate a "Tagged Time Stamp". I believe that you can also get an output signal on an Mx pin when the Demodulator detects a phase modulated cycle of its reference input clock signal. The Demodulator is most sensitive / accurate when you have setup registers ahead of time to tell it what type of Balanced Modulation to look for, i.e. the duration of the first cycle of a Modulation Event is either longer or shorter than a normal cycle. The second cycle of a Modulation Event is then the opposite (shorter or longer than a normal cycle) to maintain DC Balance. Short first then Long in the second cycle is called Logic 0. Long first then Short in the second cycle is called Logic 1. Normally the Reference Clock Input will have Modulation Events at a regular interval. Thus the Demodulator will detect these Events and produce an output at a regular interval. The output from the Demodulator at a regular interval is called a Demodulator Clock signal and the period of the Demodulator Clock is called T_grid. The Demodulators can operater in two overlapping frequency ranges and the appropriate frequency range must be selected in a control register to match the actual input signal. The Demodulators expect modulation events to occur at regular periodic intervals, T_grid, with T_grid comprising an integer number of reference input clock periods. This needds to be setup in coordination with the divid R ratio. All Modulation Events should occur "On Grid" and the result is that every Kth Time Stamp will be Tagged (along with the divider R being reset aka synchronized. See page 90 of details. Distribution Clock Output Drivers: Pg 91 ------------------------------------------ Distribution Dividers (Q Dividers) Pg 94 ------------------------------------------- Distribution Phase Offset Control: Pg 97 ------------------------------------------ Distribution N Shot / PRBS Output Clocking: Pg 100 ---------------------------------------------------- Distribution Embedded Output Clock Modulation: Pg 105 ------------------------------------------------------- Distribution Output Clock Synchronization: Pg 111 --------------------------------------------------- Frequency Translation Loops: Pg 113 ------------------------------------- Source Profiles: Pg 119 ------------------------- Digital PLL (DPLL): pg 122 ----------------------------- Cascaded DPLL Configuration: Pg 141 ------------------------------------- Analog PLL (APLL): Pg 144 ---------------------------- Reference Switching: Pg 147 ----------------------------- Time to Digital Converter (TDC): Pg 154 ------------------------------------------ Time Stamps: Pg 155 --------------------- User Time Stamp Processor (UTSP): Pg 157 ------------------------------------------- Timing Skew Measurements Using Two TDCs: Pg 160 ------------------------------------------------- Auxiliary NCOs: Pg 162 ------------------------ There are 2 Auxiliary NCOs that can provide clock signals to the M1 to M4 pins. The maximum frequency of these auxiliary NCOs is 65,535 Hz with I believe a frequency resolution of 40 bits. Temperature Sensor: Pg 167 ---------------------------- The sensor reflects the temperature of the silicon die. This temperature is measured over a range of +- 256 deg C with a resolution of 0.0078 deg C at a rate of about 6 kHz. Back of the envelope what to we expect the Si Temp to be with a nominal 25 deg C ambient ? The heat discipation will be about 0.6 Watts or more, the thermal resistance will be 23 deg C per Watt or more so we expect a die temperature of about 39 deg C. The absolute dia temp is 105 deg C. System Clock Compensation: Pg 169 ----------------------------------- "The NCOs and the TDCs of the AD9546 derive their timekeeping from the System Clock. Therefore, the frequency accuracy of any of the NCOs relates directly to the accuracy of the System Clock. Likewise, an inferred frequency based on the difference between successive TDC time stamps is subject to the accuracy of the System Clock. Therefore, the stability of the System Clock is crucial to the accuracy of the NCOs and TDCs within the AD9546". "Because the NCOs and TDCs are fundamentally numeric (digital) in nature, it is possible to tune the NCOs and TDCs numerically to counteract the System Clock instability. That is, with a known frequency error associated with the system clock source, the user can apply a corresponding correction (numerically) to the NCOs and TDCs, which is the underlying concept of System Clock Compensation". They base their compensation system on Fractional Frequency Error (FFE). If the correct frequency of the System Clock is fo but right now it is operating at frequency f then f - fo f FFE = -------- which AD says = -------- fo fo - 1 AD uses: FFE == Fractional Frequency Error FPE == Fractional Period Error FTW == ??? AD talks about their Open-Loop and Closed-Loop versions of System Clock Compensation and their 3 methods of the same. Compensation Method #1 is an Open-Loop method of System Clock Compensation and involves measuring the Si temperature of the AD9546, making the ridiculous assumption that this accurately reflects the temperature of the Quartz resonator, assumes that you know the coefficients for the 4th or 5th order polynomial that relates the resonate frequency of the Quartz Resonator to its temperature, and then correcting all the Time Stamps generate by the System Clock based on what you think is the actual frequency of the System Clock. So at best this is a TCXO where the temperature measurement that is being used to do the compensation is not that of the actual Quartz Resonator. They fluf this up with a fancy Digital Filter and a variable bandwidth at which you make corrections - but this is all basically ridiculous. Compensation Method #2 Compensation Method #3 Status and Control Pins: Pg 180 --------------------------------- Interrupt Request (IRQ): Pg 183 --------------------------------- Watchdog Timer: Pg 185 ------------------------ EEPROM Usage: Pg 186 ---------------------- Application Information: Pg 191 --------------------------------- Initialization Sequence: Pg 196 --------------------------------- Serial Control Port: Pg 199 ----------------------------- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ PHYSICAL CLOCK CONVERTER: ------------------------- I think that the Reference Clock Inputs to the chip are the input signals to the Physical Clock Converters. The basic output from the Physical Clock Converters is a series of Time Stamps of the Rising Edges of the associated Reference Clock input signal. A Physical Clock Converter can also divid its input by "R" before sending it to the TDC part of the Physical Clock Converter. NOTE that the input to the TDC part of the Physical Clock Converter can not be above 200 kHz so if your input signal to a Reference Input is above 200 kHz then you must use the divide by R block to bring it down below 200 kHz. All of this must mean that the TDC can not generate Time Stamps at a rate greater than 200 kHz (or that subsequent processing can not operate above 200 kHz). If you want a 100 MHz output from the AD9546 it is basically doing a frequency multipliclation of at least 500x and holding a phase stability of 0.1 nsec - I do not believe it. I believe that the time scale for the TDC in the Physical Clock Converter is the System Clock, i.e. the clock that comes in via pins XOA XOB. NOTE that the word Reference Clock is used in many different contexts with this chip, e.g. there can be a completely separate Reference Clock that is used just for the Mothod 3 Compensation of the System Clock. In general I think that Reference Clock means the reference for the Common Clock, i.e. the Common Clock frequency that is connected to all of the AD9546s in a clock distribution system. PHYSICAL CLOCK GENERATOR: ------------------------- The Physical Clock Generators are DPLLs that use Time Stamps as their input and generate the Physical Clock ouput of this chip. The Time Stamps derive from the Common Time Scale. These blocks are really called: PLL0 and PLL1. Each of these blocks contains: a DPLL with its NCO followed by a normal PLL with is VCO. PLL0 is the basis for the 3 OUT_0 clock signals A, B, C. PLL1 is the basis for the 2 OUT_1 clock signals A, B. Each of these 5 signals, 1A, 1B, 1C, 2A, 2B has its own "output block" between the output of its PLL and the actual output signals pins. These "output blocks" can divide by "Q" (with Q being half interger) and can do a ton of other interesting stuff. This Q divider is a 32 bit value. The output pin drivers can run up to 500 MHz. The VCO in PL0 can run from: 2424 MHz to 3232 MHz. the VCO in PL1 can run from: 3232 MHz to 4040 MHz. The VCOs in Pl0 and PL1 are followed by a divid by 2 stage before their output is sent to the "output blocks". The NCO in each PL0 and PL1 operate from 162 to 350 MHz and have a 48 bit resolution. Modulation Grid: ---------------- Crystal Clock Oscillator: ------------------------- The decision has been made to use an external bare Quarts Crystal as the timebase oscillator for the AD9546 on the DK board. The current Demo board for the AD9546 uses the following bare Quarts crystal: TAITIEN XXCDDLNANF-52.000MHz This is a bare quarts crystal in the TAITIEN XX series: 3.2 mm by 2.5 mm package 10 pFd Load Capacitance +-25 ppm Tolerance +-25 ppm Stability -40 to +85 deg C Temperature Rance No Special Requirements AT Fundamental Cut Normal Apperance ROHS Compliant On a separate sheet it says that this part has an ESR of less thaan 50 Ohms in the frequency range of 27 to 60 MHz. Pins 1, 3 are the crystal and pins 2, 4 should be tied to Ground. 3.2 mm x 2.0 mm is the external size of the package itself. If the long axis of the package is the X axis then the SMD Pads should be 1.2 mm in X by 1.1 mm in Y. The C to C pad spacing should be 2.2 mm in X by 1.6 mm in Y. Page numbers in the AD9546 datasheet with information about the crystal oscillator circuit: 9, 40, 48, 49, 52, 59, 74, 75, 175, 195. Some of the most important information starts on page 74. The AD Demo board uses 6.2 pFd capacitors with this crystal and no series resistors.