DK PCB Layers and Stackup --------------------------- Initial Rev. 1-Sept-2023 Current Rev. 6-Sept-2023 The intent of this note is to first collect all of the requirements and constraints on the arrangement of Layers in the DK PCB. After that a full specification of the Stackup for the DK PCB will be developed. Because of the number of DK Boards that need to be manufactured there is some presure to control the cost of its PCB. To get started see if DK can be pressed into a balanced 10 Layer design. Layer Function ----- ------------ 1 Trace and Pads 2 Gnd Plane 3 Trace 4 Gnd Plane 5 Power Plane 6 Power Plane 7 Gnd Plane 8 Trace 9 Gnd Plane 10 Trace and Pads The required Power Planes under the FPGA/CPU are the following: Power Plane Connects to ------------- ----------------------------------------- BULK_3V3 I/O Banks: 1, 1x, 2, 2x, 3, 5, 7, 7x DIGITAL_1V8 VDD18 and I/O Bank 9 FPGA_PLL_2V5 VDD25 BULK_1V2 I/O Banks: 0, 6 DIGITAL 2V5 VDDAUX for I/O Bank 9 CORE_1V05 FPGA/CPU CORE XCVR_1V05 VDDA XCVR_PLL_2V5 VDDA25 XCVR_CLK_2V5 XCVR_CLK Initial round of constraints when trying to assign Nominally Shaped Power Fills to Physical Layers (ignore XCVR fills for now): 1. The Power Planes under the CORE section of the FPGA/CPU and under the High-Speed Transceiver section will require at least 3 Physical Layers. This implies that in some places at least one of the Trace layers needs to be used for Power Fills. 2. The BULK_3V3 and DIGITAL_1V8 should be on Physical Layers 5 and 6 because these Power Planes need to run to many places besides under the FPGA/CPU. 3. The BULK_1V2 needs to be under Banks 0 & 6 and its needs to run under the DDR4 memory chips. DIGITAL_2V5 also needs to run under the DDR4 memory chips. 4. Under the DDR4 Banks 0 & 6 all 4 Trace layers need to be available for routing - no Power Fills are allowed on Trace layers in this area. 5. The only nominally arrangement of Power Planes is: BULK_3V3 and DIGITAL_1V8 on one physical layer CORE_1V05 and DIGITAL_2V5 on another physical layer BULK_1V2 and FPGA_PLL_2V5 on a 3rd physical layer This is the only arrangement with nominal Shapes for the 6 Power Fills that does not have an overlap. But this does not work as it forces either CORE_1V05 or BULK_1V2 onto a 1/2 oz trace layer. But BULK_1V2 can not be on a Trace layer (from constraint 4) so this forces CORE_1V05 onto a Trace layer. But CORE_1V05 can not be on a 1/2 oz Trace layer because of too much current and because of constraint 4. --> So there is no 10 Layer solution to this layout with nominal rational shapes for these 6 Power Fills. The only apparant possible solutions for staying in 10 layers is to : BULK_3V3 and CORE_1V05 on one physical plane layer DIGITAL_1V8 and BULK_1V2 on another physical plane layer DIGITAL_2V5 on a physical trace layer going North FPGA_PLL_2V5 on a physical trace layer (same physical trace layer ?) going either North or going East Routing FPGA_PLL_2V5 as a fill on a Trace layer running East under the HS Transceivers may be OK because it should be a quiet low current fill and one would need to either: Route ALL of the signals in the HS Transceiver area as micro-strip either on the top or bottom of the board (both physical layers 3 and 8 are being used a power fills under the HS Transceivers) or else put this 4th fill FPGA_PLL_2V5 on the bottom of the card and route ALL of the signals in the HS Transceiver area as either micro-strip on the top or as strip-line on physical layer 8. or else some how fit: FPGA_PLL_2V5, XCVR_PLL_2V5 and XCVR_CLK_2V5 as fills onto just 2 physical layers or else make XCVR_PLL_2V5 and XCVR_CLK_2V5 into just one combined fill. Note that in NO case can DIGITAL_2V5 wrap around and make an exit to the South for a direct connection to the 2V5 plane under the DDR4 memory chips. Even if all of this power fill stuff can be done on a 10 layer board - another big question is can one escape all of the Bank 0 and 6 DDR4 signals on just 4 trace layers ? In one dimension these pins go 8 rings deep.