Setup of the Ethernet PHYs to the Adjacent Modules ---------------------------------------------------- Initial Rev. 27-APR-2023 Current Rev. 16-May-2023 The intent of this file is to describe the setup of the Ethernet Switch and PHYs in the ADIN2111 chip that provide Ethernet communication to the two adjacent modules via twisted pairs in the main cable. The focus of this description is the items in this overall setup that are controlled by the design of the DK PCB and by jumpers on the DK board. The ADIN2111 chip can support either a 1.0 V or 2.4 V transmit level. In our application we only need to communicate with adjacent modules, i.e. 50 meters, so we will use the 1.0 V transmit level which can work on links upto 500 meters. We will use the lower voltage power supply option, 1.8 Volt, and use the voltage regulators that are internal to the ADIN2111. By using the internal regulators the Reset signal to the ADIN2111 also effectively powers down the chip. We will use a 1.8 Volt SPI bus for communication between the ADIN2111 and the SPI 0 Controller in the MPFS250T FPGA/CPU on the DK board. Control and Configuration Pins: ------------------------------- See pages: 10, 11, 12, 15, 23, 24 in the Rev a datasheet. P1_TX2P4_EN_B pin 21 and P2_TX2P4_EN_B pin 48 These pins have Internal Pull-Down resistors. If wanted an External 4.7k Ohm Pull-Up to VDDIO is used. If HI allow only 1.0 Volt Transmit Level. If LOW allow either 1.0 or 2.4 Volt Transmit Level. P1_SWPD_EN_B pin 41 This pin has an Internal Pull-Down resistors. If wanted an External 4.7k Ohm Pull-Up to VDDIO is used. The default is SWPD enabled. To disable SWPD connect an external 4.7k Ohm to VDDIO. When software power-down (SWPD) is enabled, a Reset or Power Cycle puts the chip in active mode and attempts to link up and switch forward all frames. P2_SWPD_EN_B pin 47 This pin has an Internal Pull-Up resistors. If wanted an External 4.7k Ohm Pull-Down to Gnd is used. The default is SWPD disabled. To enable SWPD connect an external 4.7k Ohm to Gnd. When SWPD is enabled, a Reset or Power Cycle puts the chip in active mode and attempts to linkup and switch forward all frames. SPI_CFG0 pin 43 This pin has an Internal Pull-Down resistors. If wanted an External 4.7k Ohm Pull-Up to VDDIO is used. Voltage Low ---> 8 bit CRC Protection Used Voltage Hi ---> 8 bit CRC Protection NOT Used Default is CRC Protection is Enabled. Configure the Device to Use 8-bit CRC (generic SPI mode) or Protection Mode (OPEN Alliance Mode) on the SPI Host Interface (SPI_CFG0). Use this pin with SPI_CFG1. See Table 22for details. The default configuration for this pin is with protection/CRC enabled. This pin is provided with an internal pull-up resistor. ????? SPI_CFG1 pin 19 This pin has an Internal Pull-Up resistors. If wanted an External 4.7k Ohm Pull-Down to Gnd is used. The default is voltage High --> Generic SPI Mode. For a Open Alliance Mode i.e. voltage Low use 4.7k Ohm to Gnd. A voltage high level on this pin enables SPI Generic Mode. A voltage low level on this pin enables SPI Open Alliance Mode. SPI Protocol SPI_CFG1 SPI_CFG0 -------------------------------- -------- -------- OPEN Alliance with Protection 0 0 OPEN Alliance Without Protection 0 1 Generic SPI with 8-bit CRC 1 0 Generic SPI Without 8-bit CRC 1 1 NOTE: The AD documentation in the ADIN2111 datasheet is not consistent wrt SPI_CFG0 & SPI_CFG1 e.g. their Table 16 Hardware Configuration Default Mode Pin Function Pin Floating ---------------------- ------------ SPI Protocol OPEN Alliance SPI CRC/Protection Enabled This table does not match their other documentation. SPI_CFG0 page 10 says it has an Internal Pull-Down pin 43 page 11 says it has an Internal Pull-Up <===== page 11 says the Default is CRC Enabled page 23 table 16 says Default is CRC Enabled page 24 table 22 says LOW Enables CRC Hi Disable CRC On their Demo Brd pin 43 has an optional 4.7k to VDDIO ---> Internal must be a Pull-Down All consistent except for page 11 saying that there is an Internal Pull-Up. SPI_CFG1 page 11 says it has an Internal Pull-Up pin 19 page 11 says Low ---> Open Alliance Hi ---> Generic SPI page 11 says the Default is Generic SPI page 23 table 16 says default is Open Alliance <==== page 24 table 22 says LOW ---> Open Alliance Hi ---> Generic SPI On their Demo Brd pin 19 has an optional 4.7k to Gnd ---> Internal must be a Pull-Up All consistent except for page 23 table 16 saying that the default is Open Alliance. Setup of the "jumpers" on the DK board: --------------------------------------- - Install the 4.7k Ohm resistors R309 and R310 to lock both Phys for 1.0 Volt transmit level. - The 4.7k Ohm resistors R305 and R308 control the protocol of the SPI connection in the following way, this is my best estimate: SPI_CFG1 SPI_CFG0 SPI Protocol R305 R308 -------------------------------- -------- -------- OPEN Alliance with Protection Install Remove OPEN Alliance Without Protection Install Install Generic SPI with 8-bit CRC Remove Remove Generic SPI Without 8-bit CRC Remove Install - The 4.7k Ohm resistors R306 and R307 control the SWPD Software Power-Down for the two Phys. This is my best understanding: To Enable SWPD for Phy P1 Remove R306. To Enable SWPD for Phy P2 Install R307. When software power-down (SWPD) is enabled, a Reset or Power Cycle puts the chip in active mode and attempts to link up and switch forward all frames.