#
#            This is the  Key In  Net List  file for the
#             BVDC-24   Bias Voltage Distribution Card
#          --=========------------------------------------
#
#                                                 Original Rev.  2-JULY-2007
#                                              Most Recent Rev. 26-OCT-2007
#
#
#   Connect each TPC Wire Input to its:
#     Bias Voltage Distribution Resistor
#     and to its DC Blocking Capacitor
#
NET  'CH_01_IN'     J2-1     R1-2     C1-1     J2-13    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_02_IN'     J2-2     R2-2     C2-1     J2-14    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_03_IN'     J2-3     R3-2     C3-1     J2-15    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_04_IN'     J2-4     R4-2     C4-1     J2-16    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_05_IN'     J2-5     R5-2     C5-1     J2-17    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_06_IN'     J2-6     R6-2     C6-1     J2-18    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_07_IN'     J2-7     R7-2     C7-1     J2-19    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_08_IN'     J2-8     R8-2     C8-1     J2-20    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_09_IN'     J2-9     R9-2     C9-1     J2-21    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_10_IN'     J2-10   R10-2    C10-1     J2-22    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_11_IN'     J2-11   R11-2    C11-1     J2-23    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_12_IN'     J2-12   R12-2    C12-1     J2-24    (NET_TYPE, 'BIAS_VOLT')
#
NET  'CH_13_IN'     J3-1    R13-2    C13-1     J3-13    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_14_IN'     J3-2    R14-2    C14-1     J3-14    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_15_IN'     J3-3    R15-2    C15-1     J3-15    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_16_IN'     J3-4    R16-2    C16-1     J3-16    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_17_IN'     J3-5    R17-2    C17-1     J3-17    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_18_IN'     J3-6    R18-2    C18-1     J3-18    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_19_IN'     J3-7    R19-2    C19-1     J3-19    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_20_IN'     J3-8    R20-2    C20-1     J3-20    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_21_IN'     J3-9    R21-2    C21-1     J3-21    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_22_IN'     J3-10   R22-2    C22-1     J3-22    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_23_IN'     J3-11   R23-2    C23-1     J3-23    (NET_TYPE, 'BIAS_VOLT')
NET  'CH_24_IN'     J3-12   R24-2    C24-1     J3-24    (NET_TYPE, 'BIAS_VOLT')
#
#
#
#
#   Connect each TPC Wire Signal Output
#   to its pin on the Readout Cable Connector
#
NET  'CH_01_OUT'     C1-2    J1-46
NET  'CH_02_OUT'     C2-2    J1-42
NET  'CH_03_OUT'     C3-2    J1-38
NET  'CH_04_OUT'     C4-2    J1-34
NET  'CH_05_OUT'     C5-2    J1-30
NET  'CH_06_OUT'     C6-2    J1-26
NET  'CH_07_OUT'     C7-2    J1-22
NET  'CH_08_OUT'     C8-2    J1-18
NET  'CH_09_OUT'     C9-2    J1-14
NET  'CH_10_OUT'    C10-2    J1-10
NET  'CH_11_OUT'    C11-2    J1-6
NET  'CH_12_OUT'    C12-2    J1-2
#
NET  'CH_13_OUT'    C13-2    J1-4
NET  'CH_14_OUT'    C14-2    J1-8
NET  'CH_15_OUT'    C15-2    J1-12
NET  'CH_16_OUT'    C16-2    J1-16
NET  'CH_17_OUT'    C17-2    J1-20
NET  'CH_18_OUT'    C18-2    J1-24
NET  'CH_19_OUT'    C19-2    J1-28
NET  'CH_20_OUT'    C20-2    J1-32
NET  'CH_21_OUT'    C21-2    J1-36
NET  'CH_22_OUT'    C22-2    J1-40
NET  'CH_23_OUT'    C23-2    J1-44
NET  'CH_24_OUT'    C24-2    J1-48
#
#
#
#
#   The Raw Bias Voltage Input Net
#
NET  'RAW_BV'       J4-2     J5-2    R25-2    (NET_TYPE, 'BIAS_VOLT')
#
#
#
#
#   The Filtered Bias Voltage Nets
#
NET  'FLTRD_BV'     R1-1     R2-1     R3-1    (NET_TYPE, 'BIAS_VOLT')
NET  'FLTRD_BV'     R4-1     R5-1     R6-1    (NET_TYPE, 'BIAS_VOLT')
NET  'FLTRD_BV'     R7-1     R8-1     R9-1    (NET_TYPE, 'BIAS_VOLT')
NET  'FLTRD_BV'    R10-1    R11-1    R12-1    (NET_TYPE, 'BIAS_VOLT')
NET  'FLTRD_BV'    R13-1    R14-1    R15-1    (NET_TYPE, 'BIAS_VOLT')
NET  'FLTRD_BV'    R16-1    R17-1    R18-1    (NET_TYPE, 'BIAS_VOLT')
NET  'FLTRD_BV'    R19-1    R20-1    R21-1    (NET_TYPE, 'BIAS_VOLT')
NET  'FLTRD_BV'    R22-1    R23-1    R24-1    (NET_TYPE, 'BIAS_VOLT')
NET  'FLTRD_BV'    R25-1                      (NET_TYPE, 'BIAS_VOLT')
#
NET  'FLTRD_BV'    C25-1    C26-1    C27-1    (NET_TYPE, 'BIAS_VOLT')
NET  'FLTRD_BV'    C28-1    C29-1    C30-1    (NET_TYPE, 'BIAS_VOLT')
#
#
NET  'GROUND'      C25-2    C26-2    C27-2    C28-2    C29-2    C30-2
#
#
#
#
#   Bias Voltage Connector Grounds  and  Ground Loop Resistors
#
NET  'GND_LOOP_1'       J4-1     J4-3     R26-1
#
NET  'GND_LOOP_2'       J5-1     J5-3     R27-2
#
NET  'GROUND'           R26-2    R27-1
#
#
#
#
#   Ground the Ground Pins  (Odd Pin Numbers)  on
#   the Readout Cable Connector and Ground Pin #50.
#
NET  'GROUND'       J1-1     J1-3     J1-5     J1-7     J1-9
NET  'GROUND'       J1-11    J1-13    J1-15    J1-17    J1-19
NET  'GROUND'       J1-21    J1-23    J1-25    J1-27    J1-29
NET  'GROUND'       J1-31    J1-33    J1-35    J1-37    J1-39
NET  'GROUND'       J1-41    J1-43    J1-45    J1-47    J1-49
NET  'GROUND'       J1-50
#
#
#
#
#   Ground the "extra" connector pins that have been made
#   available if we need to take a Ground to the Wire Frame
#   card in the future.
#
NET  'GROUND'       J6-1     J6-2     J6-3     J6-4
NET  'GROUND'       J7-1     J7-2     J7-3     J7-4
#
#
