DK Board Power System Description ------------------------------------ Initial Rev. 10-Nov-2022 Current Rev. 17-Nov-2023 This initial section is an update for the 6 Converter Design. Many details in the body of this document also need to be brought up to date. Power Supply Update --------------------- Initial Rev. 10-Nov-2023 Current Rev. 17-Nov-2023 Item DCDC1 DCDC2 DCDC3 DCDC4 DCDC5 DCDC6 -------- ------- ------- ------- ------- ------- ------- Voltage: 1V00 1V05 1V2 1V8 2V5 3V3 Converter Output 3 A 6 A 6 A 3 A 3 A 3A Current Max Main PMT HS Serial Banks 0,6 Interposer FPGA/CPU Interposer Load: ADC Core DDR4 Various DDR4 Various 70 mA FPGA/CPU 2.1 A 2.5 A 150 mA 50 mA Core DDR4 PMT ADC DDR4 ? Expected PMT ADC 85 mA 250 mA TG 440 mA 75 mA ? Current 1.2 A typ "analog" Banks Int 0.5 A "analog" Int 0.5 A Draw: 1.5 A max 2.3 A typ 3.0 A typ 850 mA typ 200 mA min Scale Metering for Output Current: 2.0 A 3.0 A 4.0 A 1.0 A 500 mA 500 mA Expected Efficiency 86 % 87 % 88 % 85 % 80 % 85 % & Input Current: 465 mA 724 mA 1091 mA 424 mA 313 mA 388 mA Sense Resistor for 10 mV: 22 mOhm 14 mOhm 9.2 mOhm 24 mOhm 32 mOhm 26 mOhm Sense Resistor Std Value: 20 mOhm 15 mOhm 10 mOhm 25 mOhm 30 mOhm 25 mOhm per 1 mV Sense ---> Output Current: 215 mA 276 mA 367 mA 94.3 mA 53.2 mA 51.5 mA -------- Repeat Output Voltage: 1V00 1V05 1V2 1V8 2V5 3V3 Vout Rset Ideal: 20.828k 17.737k 12.099k 4.786k 2.382k 1.214k Vout Rset Standard: 20.5k 17.8k 12.1k 4.75k 2.37k 1.21k Rset Slope k/Volt: 71.0k/V 51.0k/V 20.0k/V 5.8k/V 2.3k/V 1.0k/V 10% of Vout is: 0.100V 0.105V 0.120V 0.180V 0.250V 0.330V --> Rset Variable Ideal: 7.10k 5.36k 2.40k 1.04k 575 Ohm 330 Ohm Vout Rset Variable Standard: 5.0k 5.0k 2.0k 1.0k 500 Ohm 500 Ohm Vout Rset Fixed Ideal: 18.33k 15.24k 11.10k 4.29k 2.13k 964 Ohm Vout Rset Fixed Standard: 18.2k 15.4k 11.0k 4.32k 2.15k 976 Ohm --------- Repeat Output Voltage: 1V00 1V05 1V2 1V8 2V5 3V3 Zener Clamp Diode Voltage: 2.2V 2.2V 2.2V 2.2V 3.0V 3.9V Part No: 4680 4680 4680 4680 4683 4686 MMSZ T1G Scale: 2.20 2.10 1.83 1.22 1.20 1.18 There are many other details in what follows that need to be brought up to date. +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ This file describes the overall power supply system on the Disco-Kraken board. Generation of the various Reset signals is also described. This file has the following sections: Input Power - Filter and Conversion to +5 Volts Step-Down DCDC Converters Power System Startup Auxiliary Supplies - DDR4 Terminator & Reference - CNST_3V3 Power Supply Monitor Connector Step-Down Converter Input Current Monitor Circuits Physical Layout and Location of the DC/DC Converters Design of the 7 Step-Down DC/DC Converters Description of and Loads on the Various Power Buses Part Types Used in the DK Board Power Supplies DCDC Converter LC Input Filter Background Information and Various Notes: List All Known Current Loads on the DK Power Supplies List All Known Requirements about the Order in which the Power Supply Rails Ramp Up and All Known Requirements about the Ramp Rates Capacitor Lifetime Calculations Table of 1% values Power Supplies on the ICICLE demo board Input Power - Filter and Conversion to +5 Volts: ------------------------------------------------ The input power to the DK board is a nominal + 100 Volts DC. This power is supplied from the "Junction Box" at the bottom of the ocean. There is a separate Return conductor for this + 100 V input power. In the cabling and on the DK board both the + 100 V power line and its Return line are isolated from the Signal Ground on the DK board. The Signal Grounds on the 20 DK boards in a string are all connected together by a separate pair of ground conductors in the cable that runs between the modules. It is understood that the power Return wire is connected to the ground in the "Junction Box" at the bottom of the string. The + 100 V input power is converted to + 5 Volt DC power by an isolated converter on the DK board. The + 5 V output from this converter is with respect to the Signal Ground on the DK board. This 100 V to 5 V converter is enabled to operate anytime it has input power. The low input voltage lock out of this converter is nominally 40 V and it can safely operate with up to 160 V of input. This is a 20 Watt isolated converter, i.e. its rated maximum output current is 4 Amps. The anticipated load on this converter is just under 2 Amps. Between the DK boards main cable connector that receives the 100 V input power and this converter there is a noise filter that includes both a normal mode section and a common mode section. This filter has a number of functions: 1. The 100 V to 5 V converter itself makes a lot of electrical noise that it sends out from its input terminals. During normal operation this converter is expected to draw about 100 mA of input power while generating about 30 mA peak to peak of noise. I assume that this 30 mA pk-pk noise will be at the nominal 330 kHz switching frequency of this converter. The input to this converter does not include any type of common mode filtering. A specific concern is that on the 50 meters of cable between modules that this 30 mA of 330 kHz noise could interfere with the Ethernet or Timing signals that run adjacent to the 100 V Power and Return wires in this long cable. The input power filter on the DK board will attenuate this 330 KHz noise before it reaches the long cable to help prevent this interference. 2. The long cable between the Junction Box and a given module will have a significant DC resistance and a considerably higher resistance at 330 kHz where the power input converter draws current in pulses. Based on the anticipated 100 mA current draw and based on the anticipated 10 Volt drop between the Junction Box and the top module I assume that the 100 V power and its Return lines will have a total DC resistance of about 100 Ohms over this 1000 meter run. This implies a DC resistance of about 15 Ohms per 1000 feet per conductor which implies about a AWG #21 or #22 conductor or a conductor diameter of about 0.7 mm. Based on Terman pg 32, at 330 kHz the approximate AC resistance of this 100 V power source will be 175 Ohms. A significant concern is the stability of the power input converter when it is working from such a high impedance power source. The impedance of this power source at the converters switching frequency the whole way down to 1 kHz can be significantly reduced by even just a 10 uFd low ESR capacitor. The normal mode section of the noise filter provides a 10 uFd capacitor that sits right next to the input terminals of the converter. Stability of the power input converter will need to be verified when it is working from this power source. The 100 V to 5 V input power converter is shown in circuit diagram # 2. This converter provides the BULK_5V0 bus that operates all of the other loads on the DK board. The loads directly on the BULK_5V0 bus consist of the inputs to 7 step-down buck converters and possibly a few other loads that operate directly from 5 Volt power. Step-Down DCDC Converters: -------------------------- The DK board uses 7 non-isolated step-down buck converters to generate the low voltage power buses that operate most of the components on the card. These 7 step-down converters are shown in circuit diagram # 1. The designs of all 7 converters are similar and this is shown in circuit diagram # 3. All of these converters operate from the BULK_5V0 power bus. The BULK_5V0 input power to these converters passes through an LC filter to prevent the noise from one converter from being transmitted to the other converters. The size of the capacitors in this filter are about twice what is required by these step-down converters and in total added up to less than the 5k uFd maximum capacitive load that the 100 V to 5 V power input converter can tolerate. The input power to these step-down converters also passes through a 4 terminal current measuring resistor. The details of this input current measuring setup is described below. The anticipated loads on the 7 power buses that come from these step-down converters are described below. In most cases, if an error has been made in estimating the load on a given bus then actual converter type use for that bus can be changed to a higher or lower power model. The number of step-down converters used on the DK board is a compromise between using a minimum number of converters to improve reliability and using many converters to keep the noise generating loads isolated from the loads that require quiet power. In circuit diagram # 1 you will see that some of the converters include output LC filters. Note that not all of these output LC filters are shown. These output LC filters are used for two separate functions: 1. In some cases the power generated by the step-down converter is too noisy for the critical load that it powers. An example of this is the XCVR_1V05 power bus for the FPGA's high-speed serial transceivers. 2. In other cases a single step-down converter is used to power both noise generating loads and quiet loads. In this case two (or more) LC filters are used to isolate these loads. An example of this is the BULK_2V5 power bus. In all cases where LC filters are used on the output of a step-down converter the voltage feedback to regulate that converter is taken before the LC filter. The voltage feedback is taken before the LC filter to prevent adding another pole to the feedback loop and thus upsetting the stability of that voltage regulation loop. The DC resistance of the L in these filters is sized so that the voltage drop across them is minimal. A plus minus few percent output voltage trim variable resistor is included in each of the 7 step-down converters. This trim is needed only for the lowest voltage power buses with their 30 mV tolerance but for now it was considered best to uniformly include this trim in all 7 of the step-down converters. This trim is useful because the output voltage drift of these converters over temperature and over time is less than the error in their initial calibration. These trims will be set during final assembly and testing and then locked. These step-down converters include remote sense on both of their output leads. During PCB layout the remote sense inputs to these converters will be routed to the area of their principal loads. This use of the remote sense inputs in indicated in circuit diagram # 3. A sample of the output from each of these step-down converters is routed to both the Power Supply Monitor Connector and to the All Power Good Supervisor. Power System Startup: --------------------- From the time that +100 V input power is applied it takes about 2 seconds for the DK board's power system to startup and for the Reset to the FPGA/CPU to be released. This may seem slow but it should not be a problem as there is no desire to frequently power cycle the DK boards. The reason for this slow startup is to minimize the transits on the long rather high impedance power feed to these cards. The steps during power up are the following: 1. Power up starts when the +100 V DC power feed to a given DK board is turned ON in the "Base Junction Box". This power feed will initially have to charge up the approximately 25 uFd capacitance of the DK boards power input filter. The charging current will be limited only by the resistance in the main cable and the few Ohm resistance of the inductors in the power input filter. ( Will the Base Junction Box need to limit this current to prevent glitching the power to other DK boards that are already operating ? ) Once the voltage coming out of the power input filter rises over about 40 Volts then the 100V to 5V input power converter will begin to start up. It's understood that this isolated converter will take about 30 msec to ramp up its output voltage to +5 Volts. Once this converter has finished ramping up and charging the approximate 5000 uFd of capacitance on its output then the current on the +100 V input bus will drop to about 5 mA and stay there for almost a full second. 2. Once the output from the 100V to 5V input power converter has been above (and constantly remained above) approximately 4.455 Volts for approximately 1 second then the 7 step-down converters will begin to startup. These 7 converters all startup at the same time and ramp up together on a volt per volt bases. This volt per volt ramp up means for example that when the output of the 1V8 converter has reached 1.5 Volts that the output of the 3V3 converter is also at 1.5 Volts and the output of the 1V0 converter has already reached 1.0 Volts. This volt per volt ramp up of all 7 power buses is understood to satisfy the power up requirements of all of the chips connected to them. It takes approximately 40 msec for the 3V3 converter to ramp up. All others step-down converters ramp up in proportionally less time. They rather lax 4.455 V requirement on the output from the 100V to 5V input power converter is designed to prevent any problems due to slightly low output voltage from this supply. The 7 step-down converters could actually operate OK with only 4.455 Volts of input. The long approximately 1 second delay between the startup of the 100V to 5V input power converter and the startup of the 7 step-down converters is designed to allow any transits on the 100V input power bus caused by the initial action to die away before the step-down converters are started up. The step just described above is controlled by the Startup Supervisor which is shown in circuit diagram # 4. 3. Once the output of all 7 step-down converters has reached approximately 85% of their nominal bus voltage then an approximate 1 second delay is started before the Reset to the FPGA/CPU is released. This step is controlled by the All Power Good Supervisor shown in circuit diagram #5 and the Reset Circuits shown in circuit diagram # 8. Releasing the Reset to other major components on the DK board (e.g. the PMT ADC and the Timing Generator) is controlled by the CPU in the FPGA/CPU. The rather lax 85% requirement on the various power buses is designed to prevent any problems due to slightly low or noisy output from any of the step-down converters. The rather long 1 second delay between all power buses reaching 85% of their nominal value and releasing of the FPGA/CPU Reset is designed to allow any transits caused by the converter startup to die away and to ensure that various oscillators have had time to startup and stabilize (e.g. the clock for the CPU) before the Reset is released. The startup sequence described above is shown graphically in circuit diagram #9. Power down is initiated when the 100V input power is removed from the DK card. Once the output from the 100V to 5V input power converter falls below about 4.455 Volts the 7 step-down converters will begin to ramp down. Once the BULK_5V0 bus falls below about 3.8 Volts these converters will turn Off completely. The rest of the power bus ramp down is uncoordinated as the decoupling capacitors on the various power buses are discharged by their loads. Auxiliary Supplies - DDR4 Terminator & Reference - CNST_3V3: ------------------------------------------------------------ The DK board requires a number of low power low drop out supplies for special functions on the card. These specialized functions include the DDR4 memory systems and the power system Supervisors. The DDR4 memory systems require a Terminator supply that can both source or sink current. The voltage of this Terminator supply needs to be exactly 1/2 of the nominal 1.2 Volt bus that powers most of the components in the memory system. The DDR4 memory also requires a low current Reference supply. The voltage of this Reference supply is also exactly 1/2 of the nominal 1.2 Volt bus. Both the DDR4 Terminator and Reference supplies are provided by a specialized linear regulator that was designed for this purpose. The DK board uses the TI TPS51200 to generate these supplies. Separate TPS51200 are used for the DDR4 that is attached to the FPGA Fabric and for the DDR4 that is attached to the CPU in the FPGA/CPU. The DDR4 Terminator and Reference supplies are shown in circuit diagram # 6. The low power to operate the regulator circuits in the TPS51200 chips comes from the BULK_3V3 bus. The actual current that is used to make the Terminator and Reference supply outputs comes from the DDR4_1V2 bus. The design of the Startup Supervisor, the All_Power_Good Supervisor, and of the Reset circuits is cleanest if there is a 3.3 Volt supply available to these functions even before the 7 Step-Down DCDC Converters have started up. Only about 1 mA of 3.3 Volt power is required to operate all of these functions. This power is provided by the "always On" CNST_3V3 supply which is just a low power low drop out linear regulator that is powered by the BULK_5V0 bus. The CNST_3V3 supply is available anytime that the BULK_5V0 supply is providing power. The overall designs of the Supervisors and the CNST_3V3 supply ensures that there is no glitch of the 7 Step-Down Converters when the DK board powers up. The CNST_3V3 supply is available and the Startup Supervisor is in control before the 7 Step-Down Converters have the possibility to startup on their own. The goal is to prevent an uncoordinated startup of the 7 Step-Down Converters with the various power buses coming up in a random order. The CNST_3V3 supply is shown in circuit diagram # 7. Power Supply Monitor Connector: ------------------------------- A connector is provided on the DK board to allow easy checking of all of the power supplies on the card All of the power supply voltages may be check and the Input current to the 7 step-down DCDC converters may also be checked. The intent of this connector is to allow easy checking of all of these voltages and currents without the need to poke around on the DK circuit board with probes from a voltmeter. The intent is that a multi-conductor cables plugs into this connector, this cable runs to a rotor switch type of switch box where one selects which voltage or current they want to measure, and from this switch box there is a connection to a known good high quality voltmeter. This power supply monitoring setup is used during the final assembly and testing of all DK boards. This setup will also be useful during firmware and software development for the DK board to measure how changes in the firmware and software effect the power consumption of the card. It's important to note that the DK board does not include any ADCs that would allow it to monitor its own power supply voltages or currents and readback these values over a network connection. Although such self monitoring capabilities are now days rather common on complex circuit boards they were excluded from the DK design because this information is not of much value in the case of the DK board for at least 3 reasons: - The failure of any of the power supplies will bring down the FPGA/CPU on the DK board, thus there will be no network connection, thus you will not have monitoring data to see which power supply failed. - Because there is no way to access the DK boards once they are placed in operation, there is no action that one can take based on power supply monitoring data. - An auxiliary supervisor / monitor type of processor could have been included but it would have increased power consumption and probably reduced the overall reliability of the DK board. All of the power supply monitor signals have a 100 Ohm series resistor in their path on the DK board. The intent is to limit any fault current should some one for example short circuit the output from the switch box. All of the power supply monitor signals have a 100 nFd capacitor to Ground on the DK board near their pin in the Power Supply Monitor Connector. The intent is to remove any high frequency noise from the monitor signal before it is sent out to the voltmeter to reduce the chance that such noise might interfere with the voltmeter reading the correct DC value of monitor signal. These capacitors also reduce the probability that any noise can come onto the DK board from this external equipment or that a power bus can glitch when the monitor cable and switch box is plugged into the Power Supply Monitor Connector. The following table shows the pinout of the Power Supply Monitor Connector Monitored Item Conn Pin -------------------------- -------- BULK_5V0 Voltage 1 BULK_3V3 Voltage 3 BULK_2V5 Voltage 5 BULK_1V8 Voltage 7 DDR4_1V2 Voltage 9 XCVR_1V05 Voltage 11 CORE_1V00 Voltage 13 ADC_1V00 Voltage 15 CNST_3V3 Voltage 17 DDR4_VTT_FPGA Voltage 19 DDR4_VTT_CPU Voltage 21 DDR4_VREF_FPGA Voltage 23 DDR4_VREF_CPU Voltage 25 BULK_3V3 Input Current 27, 28 BULK_2V5 Input Current 29, 30 BULK_1V8 Input Current 31, 32 DDR4_1V2 Input Current 33, 34 XCVR_1V05 Input Current 35, 36 CORE_1V00 Input Current 37, 38 ADC_1V00 Input Current 39, 40 Even number pins: 2, 4, 6, 8, 10, 12, 14 16, 18, 20. 22, 24, 26 are all Grounded. In the current monitoring pins the odd pin number is more positive. Step-Down Converter Input Current Monitor Circuits: --------------------------------------------------- Knowing the Output current from the 7 step-down converters is important to our overall understanding of the DK board: - We do not currently know in detail what the load will be on some of the DK's power buses. We need to confirm that the proper size converter has been used for each power bus. A converter that is too heavily loaded will have a reliability concern. A converter that is too lightly loaded will not be operating in the range of its best efficiency. - We need to be able to see how the power bus currents change as the FPGA firmware and CPU software are developed and modified over time. - During final assembly and production testing it is important to confirm that the power buses on a given card are operating with the expected load. Even though it is the Output current from these converters that we care about - the current sense resistors are located in the converter's Input circuit because: - Placing the current sense resistors in the Output of the converter has 2 potential problems: If the converter's output voltage sense is taken Before the current sense resistor then the voltage drop across the current sense resistor changes that Bus Voltage. The current sense resistor voltage drop is in the range of 10 mV and some of the Bus Voltages must be regulated within 30 mV. A 10 mV uncertainty is a lot to waste with a 30 mV error budget. If the converter's output voltage sense is taken After the current sense resistor then we have a potential stability problem with the supply because of the extra pole in its servo loop. This can be taken care of but only with the expense of more components and that does not appear to be the best option for a system that must have high reliability. - Placing the current sense resistor in the Input to the converter gives us a good enough measure of the converter's Output current because the efficiency of the converter is approximately constant over the operating range of interest. See the efficiency curves vs output current in the power supply components sub-directory. Measuring their Input current will tell us their Output current to better than 10%. The following table shows the expected efficiency of the converters when operating at 50% of their rated output current. 3 Amp 6 Amp Converter Converter Output PTH04T260WAD PTH04T230WAD Voltage at 1.5 Amp Output at 3 Amp Output --------- ----------------- --------------- 3.3 V 93% 95% 2.5 V 91% 93% 1.8 V 88% 91% 1.2 V 85% 88% 1.0 V 84% 87% The 3 Amp converter's efficiency, at all output voltages, monotonically increases as its output current is increase from 1.5 Amps (the values shown above) up to its maximum 3 Amp capacity. The converter's efficiency at its full rated 3 Amp load is typically 2% or 3% higher than with a 1.5 Amp load. The 6 Amp converter's efficiency, at all output voltages, continues to increase up to a load of about 4 Amps and then falls off slightly when going from 4 Amps up to the full 6 Amp output rating of the converter. The value of these 4 terminal current sense resistors is selected so that at normal operating load there will be about a 10 mV drop across the resistor. This 10 mV target is picked based on: - 10 mV is large enough to make a 1% measurement of the converter's Input current possible. That is, 0.1 mV is relatively easy to resolve without a great deal of care about noise or thermal EMFs. - 10 mV is small enough compared to the 5.0 Volt Input power to these converters so that a 10 mV drop makes very little change in the overall efficiency of the DK board's power supply system. The following table looks at how these current sense resistors are selected and the scale relating the voltage across the Input current sense resistor to the actual Output current from the supply: For the 3 Amp Converter Operating at 1.5 Amp Output Current per 1 mV Across mOhms Std Value ----> for Std. --------------- Output Effic- Input 10mV Value Input Output Volts iency Amps Drop mOhms Amps Amps ------ ------ ----- ----- ----- ----- ------ 3.3 0.93 1.065 9.39 10 0.100 0.141 2.5 0.91 0.824 12.13 10 0.100 0.182 1.8 0.88 0.614 16.30 15 0.0667 0.163 1.2 0.85 0.424 23.61 25 0.0400 0.142 1.0 0.84 0.357 28.00 30 0.0333 0.140 For the 6 Amp Converter Operating at 3.0 Amp Output Current per 1 mV Across mOhms Std Value ----> for Std. --------------- Output Effic- Input 10mV Value Input Output Volts iency Amps Drop mOhms Amps Amps ------ ------ ----- ----- ----- ----- ------ 3.3 0.95 2.084 4.80 5 0.200 0.288 2.5 0.93 1.613 6.20 5 0.200 0.372 1.8 0.91 1.187 8.43 10 0.100 0.253 1.2 0.88 0.818 12.22 10 0.100 0.367 1.0 0.87 0.690 14.50 15 0.0667 0.290 Physical Layout and Location of the DC/DC Converters: ----------------------------------------------------- The DK Brd has only mid-board connectors so we do not need to preserve any space around its perimeter for front panel or backplane connectors. The DK Brd does not use vertical flow forced air cooling so we do not need to to preserver any openness along it top and bottom edges. Thus we can place all of the power supply components around the perimeter of the DK Brd and try to arrange these supplies and their loads so that the various PCB Power Fills are generally in the shape of a pie slices and thus minimize the number of physical PCB layers that are required for power distribution. That is, a given PCB physical layer is used for the distribution of power bus foo in one area of the board and for the distribution of power bus bla in a different area of the board. Design of the 7 Step-Down DC/DC Converters: ------------------------------------------- There are 7 Power Trends DC/DC converters on the DK Board: Output Expected Current Power Trends Power Bus Voltage Load Capacity Model Number ------------- ------- -------- -------- ------------ VDD_ADC_1V00 1.000 V 1.4 A 3 A PTH04T260WAD VDD_CORE_1V00 1.000 V < 3.0 A 6 A PTH04T230WAD VDDA_XCVR_1V05 1.050 V < 1.5 A 3 A PTH04T260WAD VDD_DDR4_1V2 1.200 V 4.0 A 6 A PTH04T230WAD VDD_Bulk_1V8 1.800 V < 1.5 A 3 A PTH04T260WAD VDD_Bulk_2V5 2.500 V 1.4 A 3 A PTH04T260WAD VDD_Bulk_3V3 3.300 V < 1.5 A 3 A PTH04T260WAD We want to provide about a +-3% to +-5% adjustment range on all 7 of these step-down converters to take care of their initial calibration error (about +- 2%) and to take care of the 0.1% tolerance resistors in their feedback networks. The following table list the components in each type of supply: 3 Amp 6 Amp Component PTH04T260WAD PTH04T230WAD ------------------- ---------------- ---------------- MTBF @ Io Max 5.6 E+6 Hr 5.3 E+6 Hr Cin Total Min 330 uFd Min. 330 uFd Min. Cin Total Recom 680 uFd Recom 680 uFd Recom Cin Tant 4x 150 uFd 10V 4x 150 uFd 10V Cin Cerm 4x 10 uFd 16V 4x 10 uFd 16V Cin Total Installed 640 uFd 640 uFd Cout Total Min 250 uFd 250 uFd Cout Total Max 5500 uFd 5500 uFd Cout Tant 4x 330 uFd 6V3 4x 330 uFd 6V3 Cout Cerm 4x 22 uFd 6V3 4x 22 uFd 6V3 Cout @ Load ? x 330 uFd 6V3 ? x 330 uFd 6V3 ? x 22 uFd 6V3 ? x 22 uFd 6V3 Cout Total Installed > 1408 uFd > 1408 uFd Min Cout for Rtt=0 1500 uFd 1500 uFd Resistor R4 Rtt 0 Ohm 0 Ohm Vout Rset Ideal 20.828k Ohm @1V0 20.828k Ohm @1V0 ------- 12.099k Ohm @1V2 4.786k Ohm @1V8 2.382k Ohm @2V5 1.214k Ohm @3V3 Vout Rset Standard 20.50k Ohm @1V0 20.5k Ohm @1V0 ------- 12.1k Ohm @1V2 4.75k Ohm @1V8 2.37k Ohm @2V5 1.21k Ohm @3V3 Rset Slope 71.0k/Volt @1V0 71.0k/Volt @1V0 ------- 20.0k/Volt @1V2 5.8k/Volt @1V8 2.3k/Volt @2V5 1.0k/Volt @3V3 10% of Vout is 0.100V @1V0 0.100V @1V0 ------- 0.120V @1V2 0.180V @1V8 0.250V @2V5 0.330V @3V3 --> Rset Variable Ideal 7.1k Ohm @1V0 7.1k Ohm @1V0 ------- 2.4k Ohm @1V2 1.0k Ohm @1V8 575 Ohm @2V5 330 Ohm @3V3 Vout Rset Var Standard 5.0k Ohm @1V0 5.0k Ohm @1V0 ------- 2.0k Ohm @1V2 1.0k Ohm @1V8 500 Ohm @2V5 500 Ohm @3V3 Vout Rset Fix Ideal 18.33k Ohm @1V0 18.33k Ohm @1V0 ------- 11.10k Ohm @1V2 4.29k Ohm @1V8 2.13k Ohm @2V5 964 Ohm @3V3 Vout Rset Fix Standard 18.2k Ohm @1V0 18.2k Ohm @1V0 ------- 11.0k Ohm @1V2 4.32k Ohm @1V8 2.15k Ohm @2V5 976 Ohm @3V3 Vout Rset Fix Standard 15.4k Ohm @1V05 See the Final Assembly document for details about the Vout Rset resistors and the expected Vout adjustment range for each of the 7 DC/DC Converters. The Inhibit/Under_Volt_Lockout pin on all 7 converters is tied to Ground with a 37.4k Ohm resistor. This provides an Under_Volt_Lockout of about 3.8 Volts. The Synchronization pin is tied to Ground on all 7 converters. Do this with an exposed trace in case of an emergency. It is only the Track pin that is used to manage these supplies. Include an rc0603 in the layout for the connection to the "Turbo-Trans" pins on all 7 converters just in case we need something other than zero Ohms Rtt. The ground plane under each DC/DC converter and its input and output capacitor banks are slit to control and isolate the ground noise from the large circulating currents generated by these buck converters. The Remote Sense pins are routed to an area near the biggest part of a given converter's load. That is these pins are not just tied to the Ground and Power plane right under the converter. Description of and Loads on the Various Power Buses: ---------------------------------------------------- VREF_DDR4_0V6_CPU: VREF_DDR4_0V6_FAB: ( do not confuse with DDR4_VTT_0V6 ) ------------------ This rail is the low current reference for both the DDR4 chips themselves and for the DDR4 Controller. See VTT_DDR4_0V6 below. There are separate supplies for the CPU and Fabric DDR4 memory systems. On the 96 pin DDR4 chips this reference supply connects to their pin number: M1. VTT_DDR4_0V6_CPU: VTT_DDR4_0V6_FAB: ( do not confuse with DDR4_VREF_0V6 ) ----------------- This rail supplies the approximately 27 termination resistors on the Address and Control lines to the DDR4 memory chips. Each termination resistor is 39 Ohms. The maximum load on this rail is about 415 mAmp source or sink. The splash demo brd uses a TPS51200 operating with its internal circuit powered by 3V3 and the 1V2 rail provides the current to its output when it is sourcing current. The TPS51200 can also sink current from its output to ground. This part generates both: VTT_DDR4_0V6 and VREF_DDR4_0V6. A similar part for generating the DDR4 Reference and Terminating voltages is the Microchip MIC5166. There are separate supplies for the CPU and Fabric DDR4 memory systems. VDD_ADC_1V00: ------------- The AD9083 PMT ADC needs quiet 1.000 Volt power for two independent loads that it calls: AVDD at 471 mA max on pins: D6, E6, E7, F6, F7, G6 and separately on pins: F5, J4 DVDD at 971 mA max on pins: D3, E3, F3, G3 and separately on pins: B3, C3, H3 Multiple LC Filters will be needed between the VDD_ADC_1V00 switching regulator and these various separate 1.000 V loads. The DK Brd using a 3 Amp switching regulator for its VDD_ADC_1V00 rail. The AD9083 PMT ADC also uses about 150 mA of 1.8 Volt power which may also require LC Filtering to reduce the general noise in the area of this fast ADC. VDD_CORE_1V00: -------------- This is the Core supply for the FPGA and CPU. It can be either 1.000 V or 1.050 V. Selecting its value is independent from selecting the value of the VDDA supply for the High-Speed Serial Transceivers. Currently I do not know what technical details should drive this selection. For long lifetime I assume that we prefer the 1.000 V option. The Icicle Demo Brd makes this rail with a 7 Amp maximum output switching regulator. This VDD_CORE_1V00 or VDD_CORE_1V05 rail connects to the following pins on the FPGA-CPU: M15, M17, M19, M21, N16, N18, N20, N22, P15, P17, P19, P21, R14, R16, R20, R22, T15, T17, T19, T21, U14, U16, U20. I'm guessing the load on the VDD_CORE supply to be under 3 Amps. VDDA_XCVR_1V05: --------------- This is the "analog" supply for the High-Speed Serial Rx and Tx lanes. Because the DK Brd needs to operate High-Speed Serial Receivers above 10.3125 Gbps, the VDDA supply must be 1.050 V and not the optional lower 1.000 V. I guess the load on this rail be be less than 1.5 Amps. The Icicle Demo Brd makes its VDDA with a Linear LDO regulator that can make a maximum of 5 Amps and is powered by the 3V3 switching regulator that can make a maximum of 12 Amps. On the DK Brd we make this supply with a switching regulator and then use an LC filter between this switching regulator's output and the FPGA-CPU pins that receive the VDDA supply. The 1.050 V VDDA supply connects to the FPGA-CPU on its pins: H27, K27, L25, M27, N25, P27, R25, T27, V27, Y27 VDD_DDR4_1V2: ------------- This rail powers the DDR4 memory chips for both the CPU memory system and for the Fabric memory system. This rail also powers both the CPU Bank 6 HSIO pins that connect to its DDR4 memory chips and it powers the Fabric's Bank 0 and/or Bank 8 HSIO pins that connect to its DDR4 memory chips. And finally this rail also powers the two special regulators that make the VREF_DDR4_0V6 and VTT_DDR4_0V6 supplies for the CPU and Fabric memory systems. I'm guessing the average total load on this rail from the 4 DDR4 memory chips to be 2.5 Amps (3 Watts per 8 GBytes). I'm guessing the load from the HSIO Banks to be 0.5 Amp. The total load from the two special regulators that make the VREF_DDR4_0V6 and VTT_DDR4_0V6 supplies is just under 1 Amp maximum. Thus the total expected load on the VDD_DDR4_1V2 rail is 4 Amps. The Splash demo brd uses a LX7165-01CSP converter which has a 5 Amp maximum output to make its 1V2 rail for its DDR4 memory system. On the 96 pin DDR4 memory chips the 1V2 rail is connected to their pins: A1, A9, B3, B9, C1, D1, D9, F2, F8, G1, G7, G9, J1, J2, J8, J9, L1, L9, R1, T9 To power CPU HSIO Bank 6 the 1V2 rail is connected to FPGA-CPU pins: AA1, AA11, AB8, AC5, AD2, AG3, T6, U3, V10, W7, Y4 To power Fabric HSIO Bank 0 the 1V2 rail is connected to FPGA-CPU pins: AA21, AB18, AC25, AD22, AE19, AF16, AF26, AG23, AH20, W18 To power Fabric HSIO Bank 8 the 1V2 rail is connected to FPGA-CPU pins: AA16, AC15, AD12, AE9, AF6, AG13, AH10, W14 VDD_Bulk_1V8: ------------- The VDD_Bulk_1V8 supply is used by the FPGA-CPU for its Programming and HSIO Receiver Supply on its VDD18 pins and by some of its I/O Banks. The VDD_Bulk_1V8 supply is also used by various other small loads on the DK Brd. I'm guessing that the total load on the VDD_Bulk_1V8 rail is less than 2 Amps and for now will specify a 3 Amp switching converter for this supply (which can be switched to a 6 Amp converter with no pcb change). The pins on the FPGA-CPU that receive the VDD_Bulk_1V8 supply are the following: U18, U22, V13, V15, V17, V19, V21, W12, W13, W16 VDD_Bulk_2V5: ------------- The VDD_Bulk_2V5 rail supplies the "Vpp" power to the DDR4 memory chips. This is currently thought to be under 100 mA for all four DDR4 memory chips. On the 96 pin DDR4 memory chips the 2V5 rail connects to their pins: B1 and R9. The VDD_Bulk_2V5 rail supplies a number of independent loads in the FPGA-CPU: VDD25 is called the "Device Core and Device PLL High Voltage Supply". The VDD25 pins are: K22, L12, R18, U12, W23. I'm guessing this load to be under 250 mA. VDDA25 is called the "Transceiver PLL High Voltage Supply". The VDDA25 pins are: J25, M23, T23, U25 I'm guessing this load to be under 200 mA. VDD_XCVR_CLK is called the "Transceiver Reference Clock Supply". The VDD_XCVR_CLK pins are: G25, K23, P23, W25 I'm guessing this load to be under 200 mA. VDDAUXx is called the "GPIO Auxiliary Supply" and is needed by any GPIO Bank that operates at 2.5 V or less. The GPIO Banks (both CPU and Fabric) are Bank Numbers: Bank 1 VDDAUX pins: K13, L14, L16 Bank 2 VDDAUX pins: N12, P13 Bank 4 VDDAUX pins: R12, T13 Bank 7 VDDAUX pins: M13, N14 Bank 9 VDDAUX pins: K19, L18, L20, L22 If all 5 of these banks are in use and operating at 2.5 V or less I'm guessing the total load to be under 650 mA. Thus I'm guessing the total known load on the 2.5 Volt supply to be under 1.4 Amps. Note that some of these loads will require LC Filtering between the output of the 2.5 V switching regulator and the load. Specifically the loads: VDD25 "Device Core and Device PLL High Voltage Supply" VDDA25 "Transceiver PLL High Voltage Supply" VDD_XCVR_CLK "Transceiver Reference Clock Supply" will all require LC Filtering which is practical because these are all relatively low current loads. VDD_Bulk_3V3: ------------- The VDD_Bulk_3V3 supply is used by the FPGA-CPU for some of its I/O Banks and this rail is used by various other small loads on the DK Brd. I'm guessing that the total load on the VDD_Bulk_3V3 rail is less than 2 Amps and for now will specify a 3 Amp switching converter for this supply (which can be switched to a 6 Amp converter with no pcb change). VDD_Bulk_5V0 aka the 100 Volt to 5 Volt converter: ------------------------------------------------------ The 100 V DC to 5 V DC converter is a Traco Power model TEN 20-7211WIR. This converter is isolated (1.6 kVolts) and works with a DC input between 43 V and 160 V (110 V is its nominal input) and provides a 5 V DC output at up to 20 Watts (4 Amps) with a typical efficiency of 87%. This converter makes the VDD_Bulk_5V0 rail. This converter produces a typical "reflected ripple current" of 30 mAmp and has only an internal input Pi type filter (but no common mode filter). The input under-volt lockout should typically be 40 V DC. Output regulation (over Vin and Load) is 0.2%. The output noise is 75 mVpp typical and that's with an external 1 uFd ceramic capacitor with an unspecified load. The output can have a maximum of 5000 uFd load. There is no minimum output load. The input to output capacitance is 3 nFd - so quite a lot of input to output AC coupling. The output has a typical startup time of 30 msec. Its operating temperature range is -40 C to +86 C. Its typical switching frequency is 330 kHz. Its mean time to failure is 1.5 E+6 hours. It is hermetic enough that washing is allowed. Part Types Used in the DK Board Power Supplies: ----------------------------------------------- To help eliminate assembly errors there is a strong desire to control the number of types of components that are used on the DK Brd. This design technique is followed in the power supply section of the DK Brd. Limiting the number of component types will also control the number of component risk factors that we are exposed to. The main components that are used in the power supply section of the DK Brd are the following: Power Trends Part Number V In V Out I Out Foot Print ------------ -------- ---------- ---------- --------------- PTH04T240W 2.2-5.5V 0.69-3.6 V 10 Amp Max EAY R-PDSS-T11 PTH04T230W 2.2-5.5V 0.69-3.6 V 6 Amp Max ECL R-PDSS-T10 PTH04T260W 2.2-5.5V 0.70-3.6 V 3 Amp Max ECL R-PDSS-T10 The DK Brd uses the through hole version of these supplies so that we have the possibility to replace them in house if necessary. DDR4 Reference and Terminator Supply: TI TPS51200 Filter Inductor: 10 uH 15.0 Amp 6.9 mOhm 14 Mhz Wurth 74435561100 10 uH 9.0 Amp 16.7 mOhm 29 MHz Wurth 7443321000 Common Mode Choke: 27 mH 600 mA 1.2 Ohm Wurth 7446630027 Current Measurement Resistor 4 Wire: 5 to 30 mOhm 4 terminal 2 Watt Ohmite Part No. FC4L64 5 to 30 mOhm 4 terminal 2 Watt Susumu Part No. KRL64 Start-Up Supervisor: TI TPS 3808 TPS3808G50DBVR SOT-23-6 Octal Voltage Monitor: LT LTC2910 Trim Pots: Bourns Trimpot 3214W Sealed e.g. 1 k Ohm 3214W-1-102E Tantalum Capacitors: 330 uFd 6.3 Volt 25 mOhm ESR V x 1.90 mm Kemet T520V337M006ATE025 150 uFd 10 Volt 25 mOhm ESR V x 1.90 mm Kemet T520V157M010ATE025 Ceramic Capacitors: 10 uFd 16 Volt X7R 1206 x 1.80 mm Kemet C1206C106K4RAC7800 22 uFd 6.3 Volt X7R 1206 x 1.80 mm Kemet C1206C226K9RAC7800 47 uFd 6.3 Volt X5R 1206 x 1.80 mm Kemet C1206C476M9PAC7800 0.47 uFd 250 Volt X7R 1812 x 2.70 mm Tiayo Yuden QMK432B7474KM-T 0.47 uFd 250 Volt X7R 1812 x 1.85 mm Kemet C1812C474KARAC7800 Polypropylene Film 10 uFd 250 Volt: Cornell Dubillier 730, 930, phb, phc Kemet PHE426, C4G, R75, C4AT Aluminum Electrolytic: (Note currently in the design) 18 uFd 250 Volt 20 k Hr Nichicon ULD ULD2E180MPD1TD or ULD2E180MPD 18 uFd 250 Volt 20 k Hr Rubycon LLE 250LLE18MEFC10X16 18 uFd 250 Volt 20 k Hr Chemi-Con KXF EKXF251ELL180MJ16S Polymer Aluminum Electrolytic: (Not currently in the design) 330 uFd 6.3 Volt 20 mOhm 10 mm Dia 12.2 mm Height APXA6R3ARA331MJ80G 330 uFd 16 Volt 14 mOhm 10 mm Dia 7.7 mm Height APXA160ARA331MJC0G DCDC Converter LC Input Filter: ------------------------------- At what frequency do the LC input filters to the DCDC converters become series resonant and thus loose effectiveness ? The inductor is about 10 uH. The capacitor is about 640 uFd. This gives a series resonant at about 1989 Hz. This is more than 2 orders of magnitude below the 300 kHz switching frequency of the DC/DC converters. The inductor in these filters is a Wurth 7443321000 10 uH that can handle a current of 9 Amps without saturating and has a DC resistance of 15 mOhm. The estimated AC reactance at 2 kHz is about 100 mOhm. =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Background Information and Various Notes: ------------------------------------------- Some or all of the following information may not be up to date. List All of the Known Current Loads on the DK Power Supplies: ------------------------------------------------------------- FPGA/CPU Power Requirements: ----------------------------- VDD Core Supply 1.00 / 1.05 V 23 pins VDD18 Programming and HSIO Banks AUX 1.8 V 10 pins VDD25 PLL and PNVM Supply 2.5 V 5 pins VDD_XCVR_CLK XCVR Ref Clk Supply 2.5 / 3.3 V 4 pins XCVR_VREF XCVR Reference Supply 0.9 / 1.25 V 2 pins VDDA25 XCVR PLL Supply 2.5 V 4 pins VDDA XCVR Tx/Rx Lanes Supply 1.0 / 1.05 V 10 pins VDDI0 FPGA HSIO Bank 0 1.2 / 1.35 / 1.5 / 1.8 V 10 pins VDDI1 FPGA GPIO Bank 1 1.2/1.5/1.8/2.5/3.3 V 11 pins VDDI2 MSS I/O Bank 2 1.2/1.5/1.8/2.5/3.3 V 3 pins VDDI3 JTAG Bank 1.8 / 2.5 / 3.3 V 2 pins VDDI4 MSS I/O Bank 4 1.2/1.5/1.8/2.5/3.3 V 2 pins VDDI5 MSS SGMII Bank 5 2.5 / 3.3 V 2 pins VDDI6 MSS DDR Bank 6 1.2 / 1.5 / 1.6 V 11 pins VDDI7 FPGA GPIO Bank 7 1.2/1.5/1.8/2.5/3.3 V 3 pins VDDI8 FPGA HSIO Bank 8 1.2 / 1.35 / 1.5 / 1.8 V 8 pins VDDI9 FPGA GPIO Bank 9 1.2/1.5/1.8/2.5/3.3 V 10 pins VDDAUX1 FPGA GPIO Bank 1 2.5 / 3.3 V 3 pins VDDAUX2 MSS Bank 2 2.5 / 3.3 V 2 pins VDDAUX4 MSS Bank 4 2.5 / 3.3 V 2 pins VDDAUX7 FPGA GPIO Bank 7 2.5 / 3.3 V 2 pins VDDAUX9 FPGA GPIO Bank 9 2.5 / 3.3 V 4 pins VSS Ground 134 pins Notes: that Microchip Tech uses some pin names that can be very confusing, e.g. VDDI8 and VDD18 e.g. VDDI0 and VDDI0 VDD — This supply can be powered to 1.0V or 1.05V. VDDA — This supply can be powered to 1.0V or 1.05V. This is a quiet supply for the device. One method would be to use a Linear regulator to ensure the supply is quiet. I believe that the XCVR_VREF supply is needed only if you send a single-ended reference clock signal to the FPGA-CPU. All power rails to the MPFS250T-1FCVG784E have a ramp time requirement of: 0.2 ms min 50 ms max The on-chip Power-on Reset circuitry requires the VDD, VDD18, and VDD25 supplies to ramp monotonically from 0V to the minimum recommended operating voltage. When a GPIO bank requires the VDDI to be less than 2.5V (1.2V, 1.5V, or 1.8V), the VDDAUX for that bank must be tied to 2.5V supply irrespective of the VDDI supply. The VDDI requires a separate supply for the specific I/O type (1.5V or 1.8V). VREFx is the reference voltage for DDR3 and DDR4 signals. VREF voltages can be generated internally and externally. – Internal VREF is not subjected to PCB, package inductance, and capacitance loss. These changes provide the highest performance and can be programmed as required by DDR controller. – External VREF is fixed and cannot be programmed as required. The PCB, package inductance, and capacitance impact the VREF performance. If VDDI and VDDAUX need to be configured to the same voltage (2.5V or 3.3V), ensure both VDDI and VDDAUX are supplied from the same regulator. Do not use different regulators to source these rails. This prevents any voltage variations between VDDI and VDDAUX. In this case, the board must not supply the VDDI and VDDAUX from individual voltage supplies. Starting on page 5 of the "PolarFire_SoC_FPGA_Board_Design_ Guidelines_User_Guide_VB.pdf" they have specifications for the required decoupling capacitors - but not for our chip or for out 784 pin package. AD9083 ADC Power Requirements: -------------------------------- AVDD 1.0 V +- 50 mV 208:397 mA typ 1:2 GSPS 471 mA max AVDD1P8V 1.8 V +- 100 mv 65:95 mA typ 1:2 GSPS 102 mA max DVDD 1.0 V +- 50 mV 592:797 mA typ 1:2 GSPS 971 mA max DVDD1P8V 1.8 V +- 100 mv 40:41 mA typ 1:2 GSPS 48 mA max The AVDD supply goes to 3 separate loads in this ADC: Analog Power Supply pins: D6, E6, E7, F6, F7, G6 Analog Supply for Clock pin: F5 Analog Supply for PLL pin: J4 The DVDD supply goes to 2 separate loads in this ADC: Digital Power Supply pins: D3, E3, F3, G3 Digital Driver Supply pins: B3, C3, H3 Notes: Worst case at 2 GSPS this part dissipates 1.712 Watts. The schematics for the demo brd for the AD9083 give lots of details about its power supply setup and bypass capacitors. The AD9083 includes a temperature diode to monitor its Si temp. AD9546 Clock Generator Power Requirements: -------------------------------------------- VDD 1.8 V +- 90 mV 325 mA typ 440 mA max VDDIOA 1.8 V up to 3.3 V 5 mA typ 8 mA max VDDIOB - 90 mv + 165 mV for 1.8V 2.5V or 3.3V IO Notes: Worst case this part dissipates 0.806 Watts with everything running from 1.8 V supplies. ADIN2111 Ethernet Switch & Phy Power Requirements: ---------------------------------------------------- AVDD_H 1.8 V to 3.3 V for analog circuits if 1.8 V then only 1.0 Vpp TX if 3.3 V then both 1.0 and 2.4 Vpp TX AVDD_L 1.8 V to 3.3 V input power for LDO circuits VDDIO 1.8 V or 2.5 V or 3.3 V for SPI interface DVDD1_1P1 1.1 V rail 1 power for digital PHY 1 DVDD2_1P1 1.1 V rail 2 power for digital PHY 2 DLDO1_1P1 1.1 V output from LDO regulator 1 DLDO2_1P1 1.1 V output from LDO regulator 2 Because the Enet links are only 50 meters I believe that everything could be operated from 1.8 V and use 1.8 V SPI and 1.0 Vpp Enet TX. Total power about 91 mW or 51 mA. DS91M125 1:4 M-LVDS Repeater Power Requirements: -------------------------------------------------- VCC 3.3 V about 70 mA at 10 MHz with all 4 output On TLV320ADC6140 BB Audio ADC: ---------------------------- AVDD 1.8 V AREG about 11 to 23 mA IOVDD 1.8 V or 3.3 V about 2 mA Details about the TLV320ADC6140 power are not understood. TDC7200 Time to Digital Converter: ----------------------------------- VDD 3.3 V about 2 mA CC2564 Bluetooth Transceiver: ------------------------------ VDD_IO 1.8 V about 1 mA when doing I/O only MLDO_IN 2.2 V to 4.8 V about 110 mA everything running full output about 20 mA typical everything running Details about the CC2564 power are not understood - see pg 37. DDR4 Memory Chips: ------------------ 3 Watts per 8 GBytes List All Known Requirements about the Order in which the Power Supply Rails Ramp Up and All Known Requirements about the Ramp Rates: ------------------------------------------------ The current plan is that the VDD_Bulk_5V0 rail will come up first. Only after it has reached its full voltage and been given about 1.0 seconds to stabilize will the other 7 converters start to ramp. These 7 converters that make the 1.000 V though 3.300 V rails will all ramp up at the same time, on a volt per volt basis, with the longest ramp, which is required for the VDD_Bulk_3V3 rail taking about 30 msec. The shortest ramp, which is required by the 1.000 V output converters will take about 8 msec. The VREF and VTT supplies for the DDR4 memory systems will come up as the 1.200 V and 3.300 V switching converters come up. Capacitor Lifetime Calculations: -------------------------------- This is my current but still developing understanding of the capacitor lifetimes that we should expect. - Ceramic capacitors and classical Tantalum capacitors, i.e. hermetically sealed wet tantalum capacitors and tantalum capacitors with manganese dioxide electrolyte, if properly constructed and used well within their ratings do not have a wear out mechanism. - Classical Aluminum electrolytic capacitors have a wear out mechanism caused by evaporation of their electrolyte. Quality examples of these capacitors typically have a lifetime specification something like: 2000 Hrs at 105 degrees C. If properly constructed then the lifetime scaling law for this type of capacitor is a doubling of the lifetime for every 10 deg C lower operating temperature than that given in the specification. Thus for example an Aluminum electrolytic capacitor specified for a lifetime of 2000 Hrs at 105 deg C should have a lifetime of 8000 Hrs if operated at 85 deg C. - Polymer capacitors, I believe both Aluminum Polymer and Tantalum Polymer capacitors, have a slow wear out mechanism caused by thermal degradation of the conductive polymer- the wear out is due to shrinking of the conductive polymer grains. If properly constructed then the lifetime scaling law for Polymer capacitors is a 10x increase in lifetime for every 20 deg C lower operating temperature than the temperature used in the capacitor's lifetime specification. Thus for example a Polymer capacitor specified for a lifetime of 2000 Hrs at 105 deg C should have a lifetime of 20000 Hrs if operated at 85 deg C. - Capacitors with the following lifetime specifications are used in the DK Board: Ceramic and Classical Tantalum no wear out mechanism Classical Aluminum 20k Hrs at 105 deg C Aluminum Polymer 15k Hrs at 105 deg C Tantalum Polymer 2k Hrs at 105 deg C Scaled to 45 deg C all of these capacitor types should have a lifetime of over 10E6 Hrs. 1% Standard Values (EIA E96): ----------------------------- 10.0 10.2 10.5 10.7 11.0 11.3 11.5 11.8 12.1 12.4 12.7 13.0 13.3 13.7 14.0 14.3 14.7 15.0 15.4 15.8 16.2 16.5 16.9 17.4 17.8 18.2 18.7 19.1 19.6 20.0 20.5 21.0 21.5 22.1 22.6 23.2 23.7 24.3 24.9 25.5 26.1 26.7 27.4 28.0 28.7 29.4 30.1 30.9 31.6 32.4 33.2 34.0 34.8 35.7 36.5 37.4 38.3 39.2 40.2 41.2 42.2 43.2 44.2 45.3 46.4 47.5 48.7 49.9 51.1 52.3 53.6 54.9 56.2 57.6 59.0 60.4 61.9 63.4 64.9 66.5 68.1 69.8 71.5 73.2 75.0 76.8 78.7 80.6 82.5 84.5 86.6 88.7 90.9 93.1 95.3 97.6 Power Supplies on the ICICLE demo board: ---------------------------------------- The +12V input power is used to make: 5V0 with a MIC26950YJL 3V3 with a MIC26950YJL The 5V0 power is used to make: 1V0 or 1V05 with a MIC22705YML 1V2 with a MIC23303YML 1V1 with a MIC23303YML 1V8 with a MIC23303YML 2V5 with a MIC69502WR The 3V3 power is used to make: 1V05 VDDA with a MIC69502WR 1V5 DDR3 with a MIC23303YML 0V75 VTT/VREF with a MIC5166YML the 1V8 output enables the 1V1 the 1V5 DDR3 output enables the 0V75 VTT/VREF MIC26950YJL Switch Buck Regulator <26 V in 12 Amp max Out MIC22705YML Switch Buck Regulator <5.5V in 7 Amp max Out MIC23303YML Switch Buck Regulator <5.5V in 3 Amp max Out MIC69502WR Linear LDO <5.5V In 5 Amp max Out MIC5166YML Linear DDR VTT and VREF the 5V0 at 12 Amps is made from the +12V input power with a MIC26950YJL-TR the 3V3 at 12 Amps is made from the +12V input power with a MIC26950YJL-TR the 1V0 or 1V05 7 Amp supply for the VDD Code is powered from the +5V bus and made with a MIC22705YML-TR the 1V8 at 3 Amps for the VDD18 bus and a bunch of stuff is made from +5V with a MIC23303YML-T5 the 2V5 at 5 Amps for the VDD25, VDD_XCVR_CLK and a bunch of stuff is made from +5V power with a MIC69502WR the 1V05 at 5 Amps for the high-speed link VDDA is made from 3V3 power with a MIC69502WR the 1V2 at 3 Amps supply for a bunch of stuff is made from +5V with a MIC23303YML-T5 the 1V5 at 3 Amps for DDR3 is made from +3V3 with a MIC23303YML-T5 the 1V1 at 3 Amps for LPDDR4 is made from +5 V with a MIC23303YML-T5 The DDR3 Term and Ref are made from +3V3 with a MIC5166YML-TR