#
#        Didsco-Kraken   Relatively Placed   Components  File
#       -----------------=================---==========-------
#
#
#         FPGA  BOOT Memory   BANK #3   MT25QL01GBBBESF-0SIT
#       -===================------------------------------------
#        ======
#
#                                                 Original Rev. 27-Nov-2023
#                                              Most Recent Rev.  1-Dec-2023
#
#
#  This file holds the Components for the   FPGA BOOT MEMORY
#  that runs from FPGA Bank #3.            ------
#
#  This comps file includes the Multiplexer that allows the
#  Emergency Rescue uProcessor to take over control of this
#  Boot Memory.
#
#  This is a  relatively placed  key in  comps file.
#
#  Additional  FPGA/CPU  Bank #3  components and nets
#  are included in separate comp and net files.  These
#  additional items include some pull-up resistors to
#  set default logic levels  and  the RESET input to
#  the FPGA/CPU.
#


UNITS MM


#
#                                                       Board_Location
# Ref    Part_Number   Symbol     Geometry                 X       Y     Properties
#-----   -----------   ------   ------------------      --------------   ----------
#

U1251    MT25QL01GBBB    SY_JUNK   so16w                0.0      0.00      1  270

U1252    74LVC241A       SY_JUNK   soic_20              0.0     -0.30      2    0




#
#                      Series Terminator Resistors
#
#    FPGA Boot Memory  &  Mux  to/from  DK FPGA Bank #3  &  ER uProcessor:
#   -====------------------------------------------------------------------
#

R1251    Res_22_Ohm_0603     SY_JUNK    Res_0603       -3.0    -10.0       1   90
R1252    Res_22_Ohm_0603     SY_JUNK    Res_0603       -7.5    -10.0       2   90
R1253    Res_22_Ohm_0603     SY_JUNK    Res_0603       -5.0    -10.0       2   90

R1254    Res_22_Ohm_0603     SY_JUNK    Res_0603       -2.5    -10.0       2   90
R1255    Res_22_Ohm_0603     SY_JUNK    Res_0603        0.0    -10.0       2   90
R1256    Res_22_Ohm_0603     SY_JUNK    Res_0603        2.5    -10.0       2   90

#
#   NOTE:  R2 and R3 are actually located near the ER uProcessor.
#   NOTE:  R5 and R6 are actually located near the FPGA/CPU.
#




#
#     Pull-Up  and  Default Level Setting Resistors
#
#            for the  FPGA Boot Memory:
#   ------------------====---------------------------
#

R1257    Res_4.7k_Ohm_0603    SY_JUNK    Res_0603      -9.5      5.7       1    0
R1258    Res_4.7k_Ohm_0603    SY_JUNK    Res_0603      -9.5      0.7       1    0
R1259    Res_4.7k_Ohm_0603    SY_JUNK    Res_0603       9.5     -4.5       1    0

R1260    Res_4.7k_Ohm_0603    SY_JUNK    Res_0603       9.5      3.5       2    0

R1261    Res_10.0k_Ohm_0603    SY_JUNK   Res_0603       5.0    -10.0       2   90
R1262    Res_10.0k_Ohm_0603    SY_JUNK   Res_0603       7.5    -10.0       2   90

#
#   NOTE:  Install either only R1261 or R1262.
#   NOTE:  Install R1261 if the default state of SCK is Hi
#   NOTE:  Install R1262 if the default state of SCK is Low
#




#
#    3V3  Bypass Capacitors for the   FPGA Boot Memory:
#   ----------------------------------====--------------
#

C1251   Cap_22_uFd_10_V_1206    SY_JUNK   cap_1206        -9.5     7.0     2    0

C1252   Cap_100_nFd_25_V_0603   SY_JUNK   Cap_0603        -9.5     3.2     1    0

C1253   Cap_100_nFd_25_V_0603   SY_JUNK   Cap_0603         0.0     7.0     1    0

C1254   Cap_100_nFd_25_V_0603   SY_JUNK   Cap_0603         9.5    -0.5     2   90