// file: ddr4_96_pin_basic_structure.txt // // date: 24-Dec-2022 Original bga pad only draft // date: 2-Mar-2023 Moved to a common set of 0mm8 BGA Pin-Pad Stacks // and move to hand entry of all 96 pins. // date: 3-Mar-2023 Expand the component outline to just outside Via Pads. // date: 9-Sept-2024 Adjust the Silkscreen outline to fit // the part's 13.0 mm x 7.5 mm size // date: 22-Sept-2024 Add on Sheet_Dielectric_9 lines that separate // the CA, Data L, and Data H buses so it is easier to see // // // // Geometry of the DDR4 96 Pin package for the Micron MT40A1G16. // // // This is the geometry for the Micron MT40A1G16 DDR4 SDRAM // which is a 16 Gbit part, i.e. 1 Gig addresses by 16 bits wide. // This package has 96 SMD pads, i.e. 6 Rows of 16 Pins // // This geometry has the long axis of this component on the X axis. // // The overall orientation of this geometry is pin A1 in the // North East corner. // // // T1 R1 ..... B1 A1 <--- pin #1 corner // T2 R2 ..... B2 A2 // T3 R3 ..... B3 A3 // . . . . Top-View // . . . . -------- // T7 R7 ..... B7 A7 // T8 R8 ..... B8 A8 // T9 R9 ..... B9 A9 // // // NOTE: the drawings of this package from Micron are // Bottom-View - everything here is Top-View // and rotated 90 deg CW compared to the drawings // in the Micron data sheet. This rotation is to // make it easier to hand enter the 96 pins. // // NOTE: the ball pitch of this package is 0.80 mm - not 1.0 mm. // // As written in this geometry: // // The pin Rows are numbered: 1, 2, 3, 7, 8, 9 // // Pin Rows 4, 5, 6 do not exist. // // The pin Columns are designated: A, B, C, D, E, F, G, H, // J, K, L, M, N, P, R, T // // // The Pin Pad Stacks for this Geometry come from the file: // // bga_0mm8_stack_definitions.txt // // //---------------------------------------------------------------------------- // Introduction $abort_enable = @false; $$lock_windows(@on) ; $$snap_diagonal(@off) ; $$snap_orthogonal(@off) ; //---------------------------------------------------------------------------- // Now start the actual description of the DDR4_96_Pin Rev 1 $$create_component("DDR4_96_Pin", @replace); $$page(0.0,0.0,0.0, @mm, 0.0, 0.0, [0.0, 0.0, 'CO$DDR4_96_Pin']); $$point_mode(@vertex); $$attribute( "COMPONENT_HEIGHT", "3.00", , @scale , , [0.0, 0.0] ); // // Component Outline // // The actual DDR4_96_Pin package is 13 mm in X // by 10 mm in Y. I will make the Placement Outline // only about 0.5 mm bigger than the actual array of pads. // $$initial([ 6.8, 4.0 ], , @nosnap ); $$terminal([ -6.8, 4.0 ]); $$terminal([ -6.8, -4.0 ]); $$terminal([ 6.8, -4.0 ]); $$terminal([ 6.8, 4.0 ]); $$attribute( "COMPONENT_PLACEMENT_OUTLINE", "", @mark, @scale ); // // Silkscreen Content // // Horizontal Lines $$path( "SILKSCREEN_1", 0.20 , , [ -7.00, 4.20, 6.50, 4.20 ]); $$path( "SILKSCREEN_1", 0.20 , , [ -7.00, -4.20, 7.00, -4.20 ]); // Vertical Lines $$path( "SILKSCREEN_1", 0.20 , , [ -7.00, 4.20, -7.00, -4.20 ]); $$path( "SILKSCREEN_1", 0.20 , , [ 7.00, 3.70, 7.00, -4.20 ]); // Diagonal Line $$path( "SILKSCREEN_1", 0.20 , , [ 6.50, 4.20, 7.00, 3.70 ]); $$circle( "SILKSCREEN_1", 7.40, 4.60, 1.0, 0.0); $$text( "SILKSCREEN_1", "^$ref", 0.0, 5.5, 2.5, @BC, 0, 0.7, 0.20, "std", "None", 0.0, 0.0 ); // Setup the Local Fiducial Marks // // Place Local Fiducial Marks at: // +- 10 mm at the center line of the chip $$circle( "PAD_1", 10.00, 0.00, 1.0, 0.0); $$circle( "SOLDER_MASK_1", 10.00, 0.00, 1.3, 0.0); $$circle( "PAD_1", -10.00, 0.00, 1.0, 0.0); $$circle( "SOLDER_MASK_1", -10.00, 0.00, 1.3, 0.0); // // Add lines on the Sheet_Dielectric_9 layer so that // it is easy to see the boundaries between the: // CA, Data L, and Data_H buses. // $$path( "SHEET_DIELECTRIC_9", 0.10 , , [ -0.80, 4.10, -0.80, -4.10 ]); $$path( "SHEET_DIELECTRIC_9", 0.10 , , [ 2.80, 4.10, 2.80, 0.40 ]); $$path( "SHEET_DIELECTRIC_9", 0.10 , , [ 2.80, 0.40, 3.60, -0.40 ]); $$path( "SHEET_DIELECTRIC_9", 0.10 , , [ 3.60, -0.40, 3.60, -4.10 ]); // // Define the 96 Pin-Pad Stack locations aka the pin list: //