// // file: /home2/designs/boards/Disco/Work/Geometries/Design_Disco_PCB/disco_pcb_basic_structure.txt // // date: Original Rev. 15-Nov-2022 // Rev. 20-Oct-2023 change to a rectangle with a slot // Rev. 19-Feb-2024 change to a rectangle with a bump-out // and move the 340 mm limit to Sheet_Dielectric_9 // Current Rev. 21-Feb-2024 slight change in bump-out shape keep 3.8 mm radial clearance. // // // // Disco-Kraken // // PCB Geometry Basic Structure // // // All dimensions are wrt the lower left-hand corner of the pcb. // // $$lock_windows(@on); $$create_board("disco_0_pcb"); $$page(0.0, 0.0, 0.75, @mm, 0.0, 0.0, [0.0,0.0,'BO$disco_0_pcb'] ); $$point_mode(@vertex); $$attribute( "MILLING_ORIGIN", "MILLING 0 0.0 0 ", , @scale , , [0.0, 0.0]); $$attribute( "DRILL_ORIGIN", "0.0", , @scale , , [0.0, 0.0]); $$template_line_style( @Solid ); // // For the outlines given in the "Initial - Terminal" // format we will begin at 0,0 and proceed CCW. // // // Board Outline // $$initial([ 0.00, 0.00 ], , @nosnap ); $$terminal([ 138.00, 0.00 ]); $$terminal([ 138.00, -34.00 ]); $$terminal([ 186.00, -34.00 ]); $$terminal([ 235.00, 0.00 ]); $$terminal([ 235.00, 235.00 ]); $$terminal([ 0.00, 235.00 ]); $$terminal([ 0.00, 0.00 ]); $$path( "BOARD_OUTLINE", 0.20 ); // // // // Old Slot Version of the Board // // // // $$terminal([ 137.80, 0.00 ]); // // $$terminal([ 137.80, 24.50 ]); // // $$terminal([ 166.70, 24.50 ]); // // $$terminal([ 166.70, 0.00 ]); // // // // Board Routing Outline // $$initial([ 0.00, 0.00 ], , @nosnap ); $$terminal([ 138.00, 0.00 ]); $$terminal([ 138.00, -34.00 ]); $$terminal([ 186.00, -34.00 ]); $$terminal([ 235.00, 0.00 ]); $$terminal([ 235.00, 235.00 ]); $$terminal([ 0.00, 235.00 ]); $$terminal([ 0.00, 0.00 ]); $$attribute( "BOARD_ROUTING_OUTLINE", "", @mark, @scale ); // // Board Placement Ooutline // $$initial([ 0.00, 0.00 ], , @nosnap ); $$terminal([ 138.00, 0.00 ]); $$terminal([ 138.00, -34.00 ]); $$terminal([ 186.00, -34.00 ]); $$terminal([ 235.00, 0.00 ]); $$terminal([ 235.00, 235.00 ]); $$terminal([ 0.00, 235.00 ]); $$terminal([ 0.00, 0.00 ]); $$attribute( "BOARD_PLACEMENT_OUTLINE", "", @mark, @scale ); $$attribute( "BOARD_DEFINITION_IDENTIFIER", ""); $$attribute( "BOARD_ROUTING_LAYERS", "", , , , [12, 0]); $$attribute( "POWER_NET_NAMES", "GROUND"); $$attribute( "DIAGONAL_ROUTING_ALLOWED", "yes"); $$attribute( "TJUNCTIONS_ALLOWED", "yes"); $$attribute( "BOARD_DEFAULT_PADSTACK", "TERM_60"); $$attribute( "BOARD_DEFAULT_VIA", "via_0mm65"); $$attribute( "DEFAULT_PAD_SIZE", "", , @scale , , [ 1.50, 0.0 ]); $$attribute( "BOARD_PLACEMENT_GRID", "", , @scale , , [ 0.10, 0.0 ]); $$attribute( "BOARD_PLACEMENT_CLEARANCE", "", , @scale , , [ 0.10, 0.0 ]); $$attribute( "BOARD_MATERIAL", ""); $$attribute( "BOARD_THICKNESS", "", , @scale , , [ 0.0, 0.0 ]); $$attribute( "BOARD_INTERNAL_COPPER", "", , @scale , , [ 0.0, 0.0 ]); $$attribute( "BOARD_EXTERNAL_COPPER", "", , @scale , , [ 0.0, 0.0 ]); // // For now add a 340 mm diameter circle on // GLUE_MASK_1 this is to shown the limits // of the space available to the DK board. // This circle is centered on the center of DK. // $$circle( "SHEET_DIELECTRIC_9", 117.50, 117.50, 340.00, 0.20 ); // // file: disco_pcb_drill_holes.txt // // // date: Original Rev. 15-Nov-2022 // Rev. 20-Oct-2022 // Rev. 19-Feb-2024 Remove the 9th Mounting Screw Hole. // Rev. 19-Feb-2024 Change the Plane Relief to 5.2 mm i.e. a 1 mm gap // Current Rev. 23-Jan-2025 Remove the North-East and Center-East Mounting Holes // as they are now 1 pin components in the design and // Increase the Plane Relief to 7.2 mm i.e. a 2 mm gap // The Aperture Table already includes a 7.2 mm Flash // and Stop relieving the Solder Mask around these holes // // // // Disco-Kraken // // PCB Geometry Drill Holes // // // // // // Recall some Standard Size Screw Holes // -------------------------------------- // // - M2.5 Screw Dimensions: // // Diameter of Threaded Section: 2.45 mm // Diameter of the Screw Head: 4.5 mm // Thickness of the Screw Head: 1.5 mm // // - In the DK PCB implement this as: // // Drill Hole Diameter: 2.7 mm // Pad Diameter: 4.9 mm // Solder Mask Opening Diameter: 5.1 mm // Plane Relief Diameter: 3.7 mm // Silkscreen circle Diameter: 5.1 mm // // // // - M3 Screw Dimensions: // // Diameter of Threaded Section: 3.0 mm // Diameter of the Screw Head: 5.5 mm // M3 Washer Outside Diameter: 7.0 mm // // - In the DK PCB implement this as: // // Drill Hole Diameter: 3.2 mm // Pad Diameter: 7.4 mm // Solder Mask Opening Diameter: 7.6 mm // Plane Relief Diameter: 4.5 mm // Silkscreen circle Diameter: 7.6 mm // // // // - 4-40 Button Head Screw Dimensions: // // Diameter of Threaded Section: 2.8 mm // Diameter of the Screw Head: 5.3 mm // Thickness of the Screw Head: 1.5 mm // // - In the DK PCB implement this as: // // Drill Hole Diameter: 3.0 mm // Pad Diameter: 6.0 mm // Solder Mask Opening Diameter: 6.2 mm // Plane Relief Diameter: 4.0 mm // Silkscreen circle Diameter: 9.0 mm // // // Add 8 PCB Mounting Holes // // one mounting hole in each corner set back 6.0 mm from both edges // one mounting hole in the middle of each edge set back 6.0 mm from the edge // // These mounting holes are for M3 screws with a washer. $$attribute( "DRILL_DEFINITION_UNPLATED", "3.20", , @scale , , [ 6.00, 6.00 ]); //$$circle( "PAD_1", 6.00, 6.00, 7.40, 0.0 ); //$$circle( "PAD_2", 6.00, 6.00, 7.40, 0.0 ); //$$circle( "SOLDER_MASK_1", 6.00, 6.00, 7.60, 0.0 ); //$$circle( "SOLDER_MASK_2", 6.00, 6.00, 7.60, 0.0 ); $$circle( "POWER", 6.00, 6.00, 7.20, 0.0 ); $$circle( "SILKSCREEN_1", 6.00, 6.00, 7.60, 0.20 ); $$circle( "SILKSCREEN_2", 6.00, 6.00, 7.60, 0.20 ); $$attribute( "DRILL_DEFINITION_UNPLATED", "3.20", , @scale , , [ 117.50, 6.00 ]); //$$circle( "PAD_1", 117.50, 6.00, 7.40, 0.0 ); //$$circle( "PAD_2", 117.50, 6.00, 7.40, 0.0 ); //$$circle( "SOLDER_MASK_1", 117.50, 6.00, 7.60, 0.0 ); //$$circle( "SOLDER_MASK_2", 117.50, 6.00, 7.60, 0.0 ); $$circle( "POWER", 117.50, 6.00, 7.20, 0.0 ); $$circle( "SILKSCREEN_1", 117.50, 6.00, 7.60, 0.20 ); $$circle( "SILKSCREEN_2", 117.50, 6.00, 7.60, 0.20 ); $$attribute( "DRILL_DEFINITION_UNPLATED", "3.20", , @scale , , [ 229.00, 6.00 ]); //$$circle( "PAD_1", 229.00, 6.00, 7.40, 0.0 ); //$$circle( "PAD_2", 229.00, 6.00, 7.40, 0.0 ); //$$circle( "SOLDER_MASK_1", 229.00, 6.00, 7.60, 0.0 ); //$$circle( "SOLDER_MASK_2", 229.00, 6.00, 7.60, 0.0 ); $$circle( "POWER", 229.00, 6.00, 7.20, 0.0 ); $$circle( "SILKSCREEN_1", 229.00, 6.00, 7.60, 0.20 ); $$circle( "SILKSCREEN_2", 229.00, 6.00, 7.60, 0.20 ); $$attribute( "DRILL_DEFINITION_UNPLATED", "3.20", , @scale , , [ 6.00, 117.50 ]); //$$circle( "PAD_1", 6.00, 117.50, 7.40, 0.0 ); //$$circle( "PAD_2", 6.00, 117.50, 7.40, 0.0 ); //$$circle( "SOLDER_MASK_1", 6.00, 117.50, 7.60, 0.0 ); //$$circle( "SOLDER_MASK_2", 6.00, 117.50, 7.60, 0.0 ); $$circle( "POWER", 6.00, 117.50, 7.20, 0.0 ); $$circle( "SILKSCREEN_1", 6.00, 117.50, 7.60, 0.20 ); $$circle( "SILKSCREEN_2", 6.00, 117.50, 7.60, 0.20 ); // //$$attribute( "DRILL_DEFINITION_UNPLATED", "3.20", , @scale , , [ 229.00, 117.50 ]); // ////$$circle( "PAD_1", 229.00, 117.50, 7.40, 0.0 ); // ////$$circle( "PAD_2", 229.00, 117.50, 7.40, 0.0 ); // //$$circle( "SOLDER_MASK_1", 229.00, 117.50, 7.60, 0.0 ); // //$$circle( "SOLDER_MASK_2", 229.00, 117.50, 7.60, 0.0 ); // //$$circle( "POWER", 229.00, 117.50, 7.20, 0.0 ); // //$$circle( "SILKSCREEN_1", 229.00, 117.50, 7.60, 0.20 ); // //$$circle( "SILKSCREEN_2", 229.00, 117.50, 7.60, 0.20 ); $$attribute( "DRILL_DEFINITION_UNPLATED", "3.20", , @scale , , [ 6.00, 229.00 ]); //$$circle( "PAD_1", 6.00, 229.00, 7.40, 0.0 ); //$$circle( "PAD_2", 6.00, 229.00, 7.40, 0.0 ); //$$circle( "SOLDER_MASK_1", 6.00, 229.00, 7.60, 0.0 ); //$$circle( "SOLDER_MASK_2", 6.00, 229.00, 7.60, 0.0 ); $$circle( "POWER", 6.00, 229.00, 7.20, 0.0 ); $$circle( "SILKSCREEN_1", 6.00, 229.00, 7.60, 0.20 ); $$circle( "SILKSCREEN_2", 6.00, 229.00, 7.60, 0.20 ); $$attribute( "DRILL_DEFINITION_UNPLATED", "3.20", , @scale , , [ 117.50, 229.00 ]); //$$circle( "PAD_1", 117.50, 229.00, 7.40, 0.0 ); //$$circle( "PAD_2", 117.50, 229.00, 7.40, 0.0 ); //$$circle( "SOLDER_MASK_1", 117.50, 229.00, 7.60, 0.0 ); //$$circle( "SOLDER_MASK_2", 117.50, 229.00, 7.60, 0.0 ); $$circle( "POWER", 117.50, 229.00, 7.20, 0.0 ); $$circle( "SILKSCREEN_1", 117.50, 229.00, 7.60, 0.20 ); $$circle( "SILKSCREEN_2", 117.50, 229.00, 7.60, 0.20 ); // //$$attribute( "DRILL_DEFINITION_UNPLATED", "3.20", , @scale , , [ 229.00, 229.00 ]); // ////$$circle( "PAD_1", 229.00, 229.00, 7.40, 0.0 ); // ////$$circle( "PAD_2", 229.00, 229.00, 7.40, 0.0 ); // //$$circle( "SOLDER_MASK_1", 229.00, 229.00, 7.60, 0.0 ); // //$$circle( "SOLDER_MASK_2", 229.00, 229.00, 7.60, 0.0 ); // //$$circle( "POWER", 229.00, 229.00, 7.20, 0.0 ); // //$$circle( "SILKSCREEN_1", 229.00, 229.00, 7.60, 0.20 ); // //$$circle( "SILKSCREEN_2", 229.00, 229.00, 7.60, 0.20 ); // // Add a 9th PCB Mounting Hole // // set back 6.0 mm from the edge // to support the board by the cut out for the SFP Modules // // These mounting holes are for M3 screws with a washer. // //$$attribute( "DRILL_DEFINITION_UNPLATED", "3.20", , @scale , , [ 176.50, 6.00 ]); // //$$circle( "PAD_1", 6.00, 6.00, 7.40, 0.0 ); // //$$circle( "PAD_2", 6.00, 6.00, 7.40, 0.0 ); // //$$circle( "SOLDER_MASK_1", 176.50, 6.00, 7.60, 0.0 ); // //$$circle( "SOLDER_MASK_2", 176.50, 6.00, 7.60, 0.0 ); // //$$circle( "POWER", 176.50, 6.00, 7.20, 0.0 ); // //$$circle( "SILKSCREEN_1", 176.50, 6.00, 7.60, 0.20 ); // //$$circle( "SILKSCREEN_2", 176.50, 6.00, 7.60, 0.20 ); // // file: disco_pcb_silkscreen.txt // // date: Original Rev. 15-Nov-2022 // Current Rev. 12-Mar-2025 // // // // Disco-Kraken // // PCB Geometry Silkscreen // // // Label the Board // $$text( "SILKSCREEN_1", "Disco-Kraken", 113.0, 164.5, 3.50, @BC, 0, 0.90, 0.25, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "MSU Physics", 113.0, 169.5, 2.00, @BC, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "March 2025", 64.0, 158.7, 2.00, @BC, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); // // Label the Layers // $$text( "SIGNAL_1", "Disco-Kraken Brd Art 1", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_1", "L1 Top Traces & Pads ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "PREPREG_1", "Disco-Kraken Brd Art 2 & 5", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "PREPREG_1", "L2 & L5 Upper Ground Planes", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_2", "Disco-Kraken Brd Art 3", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_2", "L3 Traces ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_3", "Disco-Kraken Brd Art 4", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_3", "L4 Traces & One Fill ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "PREPREG_1", "Disco-Kraken Brd Art 2 & 5", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "PREPREG_1", "L2 & L5 Upper Ground Planes", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_11", "Disco-Kraken Brd Art 6 ", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_11", "L6 13x Power Fills ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_12", "Disco-Kraken Brd Art 7 ", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_12", "L7 12x Power Fills ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "PREPREG_2", "Disco-Kraken Brd Art 8 & 11", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "PREPREG_2", "L8 & L11 LowerGround Planes", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_8", "Disco-Kraken Brd Art 9", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_8", "L9 Traces ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_9", "Disco-Kraken Brd Art 10", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_9", "L10 Traces ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "PREPREG_2", "Disco-Kraken Brd Art 8 & 11", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "PREPREG_2", "L8 & L11 LowerGround Planes", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_10", "Disco-Kraken Brd Art 12 ", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SIGNAL_10", "L12 Bottom Traces & Pads ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "DRAWING_1", "Disco-Kraken Board Art 13", 50.0, -12.0, 3.0, @BC, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "DRAWING_1", "MSU Physics March 2025", 50.0, -19.0, 3.0, @BC, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "Disco-Kraken Brd Art 14", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "Silk Screen Top ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_2", "Disco-Kraken Brd Art 15", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0, , @nomirror ); $$text( "SILKSCREEN_2", "Silk Screen Bottom ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0, , @nomirror ); $$text( "SOLDER_MASK_1", "Disco-Kraken Brd Art 16", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SOLDER_MASK_1", "Solder Mask Top ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SOLDER_MASK_2", "Disco-Kraken Brd Art 17", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0, , @nomirror ); $$text( "SOLDER_MASK_2", "Solder Mask Bottom ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0, , @nomirror ); $$text( "PASTE_MASK_1", "Disco-Kraken Brd Art 18", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "PASTE_MASK_1", "Paste Stencil Top ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "PASTE_MASK_2", "Disco-Kraken Brd Art 19", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0, , @nomirror ); $$text( "PASTE_MASK_2", "Paste Stencil Bottom ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0, , @nomirror ); $$text( "PREPREG_5", "Disco-Kraken Brd Art 20", 2.0, -12.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); $$text( "PREPREG_5", "Via Plugs Top ", 2.0, -24.0, 5.0, @BL, 0, 0.90, 0.20, "std", "None", 0.0, 0.0 ); // // End of the Layer Labels // // // Label the 6 Power Supply Trim Pots: // $$text( "SILKSCREEN_1", "1V00", 185.2, 27.0, 2.0, @BC, 0, 0.70, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "1V05", 101.5, 50.5, 2.0, @BC, 0, 0.70, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "1V2", 70.0, 50.5, 2.0, @BC, 0, 0.70, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "1V8", 193.0, 206.1, 2.0, @BC, 0, 0.70, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "2V5", 142.0, 210.0, 2.0, @BC, 0, 0.70, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "3V3", 73.0, 207.0, 2.0, @BC, 0, 0.70, 0.20, "std", "None", 0.0, 0.0 ); // // Label the PMT Channel Inputs: // $$text( "SILKSCREEN_1", "PMT 1", 225.9, 164.5, 2.5, @BC, 90, 0.70, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "PMT 8", 225.9, 141.9, 2.5, @BC, 90, 0.70, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "PMT 9", 225.9, 93.1, 2.5, @BC, 90, 0.70, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "PMT 16", 225.9, 71.8, 2.5, @BC, 90, 0.70, 0.20, "std", "None", 0.0, 0.0 ); // // Label the two USB Camera Connectors: // $$text( "SILKSCREEN_1", "Camara", 14.5, 10.5, 2.5, @BC, 270, 0.70, 0.20, "std", "None", 0.0, 0.0, , , @noright_reading ); $$text( "SILKSCREEN_1", "A", 10.0, 11.0, 2.5, @BC, 270, 0.70, 0.20, "std", "None", 0.0, 0.0, , , @noright_reading ); $$text( "SILKSCREEN_1", "Camara", 15.5, 224.0, 2.5, @BC, 270, 0.70, 0.20, "std", "None", 0.0, 0.0, , , @noright_reading ); $$text( "SILKSCREEN_1", "B", 11.0, 224.0, 2.5, @BC, 270, 0.70, 0.20, "std", "None", 0.0, 0.0, , , @noright_reading ); // // Label the ACCESS and Power Supply Monitor Connectors: // $$text( "SILKSCREEN_1", "ACCESS", 24.0, 207.0, 2.5, @BC, 0, 0.70, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "POWER", 214.0, 228.0, 2.5, @BC, 0, 0.70, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "Monitor", 214.0, 224.0, 2.5, @BC, 0, 0.70, 0.20, "std", "None", 0.0, 0.0 ); // // White Area next to the "SN" text for the Serial Number // // Two vertical lines then a bunch of horizontal lines all 1 mm wide. // // Vertical $$path( "SILKSCREEN_1", 1.00, , [ 206.50, 58.00, 206.50, 50.50 ]); $$path( "SILKSCREEN_1", 1.00, , [ 234.50, 58.00, 234.50, 50.50 ]); // Horizontal $$path( "SILKSCREEN_1", 1.00, , [ 206.50, 58.00, 234.50, 58.00 ]); $$path( "SILKSCREEN_1", 1.00, , [ 206.50, 57.10, 234.50, 57.10 ]); $$path( "SILKSCREEN_1", 1.00, , [ 206.50, 56.20, 234.50, 56.20 ]); $$path( "SILKSCREEN_1", 1.00, , [ 206.50, 55.30, 234.50, 55.30 ]); $$path( "SILKSCREEN_1", 1.00, , [ 206.50, 54.40, 234.50, 54.40 ]); $$path( "SILKSCREEN_1", 1.00, , [ 206.50, 53.50, 234.50, 53.50 ]); $$path( "SILKSCREEN_1", 1.00, , [ 206.50, 52.60, 234.50, 52.60 ]); $$path( "SILKSCREEN_1", 1.00, , [ 206.50, 51.70, 234.50, 51.70 ]); $$path( "SILKSCREEN_1", 1.00, , [ 206.50, 51.10, 234.50, 51.10 ]); $$path( "SILKSCREEN_1", 1.00, , [ 206.50, 50.50, 234.50, 50.50 ]); // // SilkScreen 1 Lines to Guide Reference Designators // // XCVR AC Coupling Caps // $$path( "SILKSCREEN_1", 0.20, , [ 153.7, 144.3, 154.8, 126.8 ]); $$path( "SILKSCREEN_1", 0.20, , [ 154.8, 126.8, 155.9, 125.0 ]); // Interposer A Resistors // $$path( "SILKSCREEN_1", 0.20, , [ 150.4, 217.8, 161.2, 217.8 ]); $$path( "SILKSCREEN_1", 0.20, , [ 152.4, 216.6, 164.2, 216.6 ]); $$path( "SILKSCREEN_1", 0.20, , [ 155.8, 217.8, 158.3, 216.6 ]); // ER uProcessor Resistors // $$path( "SILKSCREEN_1", 0.20, , [ 55.7, 138.7, 59.0, 134.8 ]); $$path( "SILKSCREEN_1", 0.20, , [ 59.0, 134.8, 68.3, 134.8 ]); // // SilkScreen 1 Kapton Tape over DCDC20 Top Traces // $$circle( "SILKSCREEN_1", 5.10, 95.40, 6.00, 0.00 ); $$circle( "SILKSCREEN_1", 23.80, 95.40, 6.00, 0.00 ); $$circle( "SILKSCREEN_1", 15.00, 44.60, 4.10, 0.00 ); $$circle( "SILKSCREEN_1", 22.00, 44.60, 4.10, 0.00 ); $$circle( "SILKSCREEN_1", 27.20, 66.10, 6.00, 0.00 ); $$text( "SILKSCREEN_1", "Kapton", 14.5, 92.0, 2.0, @BC, 0, 0.70, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "Kapton", 18.5, 47.0, 2.0, @BC, 0, 0.70, 0.20, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_1", "Kapton", 21.5, 69.0, 2.0, @BC, 0, 0.70, 0.20, "std", "None", 0.0, 0.0 ); // // Additional Text on SilkScreen 2 // $$text( "SILKSCREEN_2", "Disco-Kraken", 136.0, 13.0, 3.0, @BC, 0, 0.70, 0.25, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_2", "MSU Physics", 136.0, 8.5, 2.5, @BC, 0, 0.70, 0.25, "std", "None", 0.0, 0.0 ); $$text( "SILKSCREEN_2", "March 2025", 136.0, 4.0, 2.5, @BC, 0, 0.70, 0.25, "std", "None", 0.0, 0.0 ); // // file: disco_pcb_drawing_and_dimension.txt // // date: Original Rev. 11-Oct-2023 // Current Rev. 21-Aug-2024 // // // // Notes: // // The pcb geometry source file holds the manufacturing // drawing and dimensions information. // // $$template_line_style( @Solid ); // Show 0,0 at bottom left corner. $$path( "DRAWING_1", 0.20, , [ -5.0, -5.0, -23.0, -23.0 ] ); // comment line $$path( "DRAWING_1", 0.20, , [ -5.0, -5.0, -10.0, -7.5 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ -5.0, -5.0, -7.5, -10.0 ] ); // arrow $$text( "DRAWING_1", "X = 0", -40.0, -18.0, 4.0, @BC, 0, 1.00, 0.20, "std", "None", 0.0, 0.0 ); $$text( "DRAWING_1", "Y = 0", -40.0, -25.0, 4.0, @BC, 0, 1.00, 0.20, "std", "None", 0.0, 0.0 ); $$text( "DRAWING_1", "Corner", -40.0, -32.0, 4.0, @BC, 0, 1.00, 0.20, "std", "None", 0.0, 0.0 ); $$path( "DRAWING_1", 0.20, , [ -23.0, -13.5, -23.0, -32.5 ] ); // Brace Line Vert $$path( "DRAWING_1", 0.20, , [ -23.0, -13.5, -25.0, -12.5 ] ); // Brace Line Top $$path( "DRAWING_1", 0.20, , [ -25.0, -33.5, -23.0, -32.5 ] ); // Brace Line Bot // Main Board Overall Horizontal Dimension. $$path( "DRAWING_1", 0.20, , [ 0.0, -6.0, 0.0, -70.0 ] ); // Left witness line $$path( "DRAWING_1", 0.20, , [ 0.0, -65.0, 48.0, -65.0 ] ); // Left dimension line $$path( "DRAWING_1", 0.20, , [ 0.0, -65.0, 7.5, -62.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 0.0, -65.0, 7.5, -68.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 235.0, -6.0, 235.0, -70.0 ] ); // Right witnes line $$path( "DRAWING_1", 0.20, , [ 92.0, -65.0, 235.0, -65.0 ] ); // Right dimension line $$path( "DRAWING_1", 0.20, , [ 227.5, -62.0, 235.0, -65.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 227.5, -68.0, 235.0, -65.0 ] ); // arrow $$text( "DRAWING_1", "235.00 mm", 70.0, -65.0, 4.0, @CC, 0, 1.00, 0.20, "std", "None", 0.0, 0.0 ); $$text( "DRAWING_1", "X Dimension", 70.0, -74.0, 4.0, @CC, 0, 1.00, 0.20, "std", "None", 0.0, 0.0 ); // Bump West Edge Horizontal Dimension $$path( "DRAWING_1", 0.20, , [ 0.0, -45.0, 48.0, -45.0 ] ); // Left dimension line $$path( "DRAWING_1", 0.20, , [ 0.0, -45.0, 7.5, -42.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 0.0, -45.0, 7.5, -48.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 138.0, -40.0, 138.0, -50.0 ] ); // Right witnes line $$path( "DRAWING_1", 0.20, , [ 92.0, -45.0, 138.0, -45.0 ] ); // Right dimension line $$path( "DRAWING_1", 0.20, , [ 130.5, -42.0, 138.0, -45.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 130.5, -48.0, 138.0, -45.0 ] ); // arrow $$text( "DRAWING_1", "138.00 mm", 70.0, -45.0, 4.0, @CC, 0, 1.00, 0.20, "std", "None", 0.0, 0.0 ); // Bump East Edge Horizontal Dimension $$path( "DRAWING_1", 0.20, , [ 0.0, -55.0, 48.0, -55.0 ] ); // Left dimension line $$path( "DRAWING_1", 0.20, , [ 0.0, -55.0, 7.5, -52.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 0.0, -55.0, 7.5, -58.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 186.0, -40.0, 186.0, -60.0 ] ); // Right witnes line $$path( "DRAWING_1", 0.20, , [ 92.0, -55.0, 186.0, -55.0 ] ); // Right dimension line $$path( "DRAWING_1", 0.20, , [ 178.5, -52.0, 186.0, -55.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 178.5, -58.0, 186.0, -55.0 ] ); // arrow $$text( "DRAWING_1", "186.00 mm", 70.0, -55.0, 4.0, @CC, 0, 1.00, 0.20, "std", "None", 0.0, 0.0 ); // // Overall Vertical Dimension // $$path( "DRAWING_1", 0.20, , [ 241.0, 235.00, 280.0, 235.0 ] ); // Upper witness line $$path( "DRAWING_1", 0.20, , [ 275.0, 132.50, 275.0, 235.0 ] ); // dimension line $$path( "DRAWING_1", 0.20, , [ 272.0, 227.50, 275.0, 235.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 278.0, 227.50, 275.0, 235.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 241.0, 0.0, 280.0, 0.0 ] ); // Lower witness line $$path( "DRAWING_1", 0.20, , [ 275.0, 102.5, 275.0, 0.0 ] ); // dimension line $$path( "DRAWING_1", 0.20, , [ 272.0, 7.5, 275.0, 0.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 278.0, 7.5, 275.0, 0.0 ] ); // arrow $$text( "DRAWING_1", "235.00 mm", 275.0, 122.5, 4.0, @CC, 0, 1.00, 0.20, "std", "None", 0.0, 0.0 ); $$text( "DRAWING_1", "Y Dimension", 275.0, 112.5, 4.0, @CC, 0, 1.00, 0.20, "std", "None", 0.0, 0.0 ); // Bump Bottom Edge Vertical Dimension $$path( "DRAWING_1", 0.20, , [ 275.0, -10.50, 275.0, 0.0 ] ); // dimension line $$path( "DRAWING_1", 0.20, , [ 272.0, -7.50, 275.0, 0.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 278.0, -7.50, 275.0, 0.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 245.0, -34.0, 280.0, -34.0 ] ); // Lower witness line $$path( "DRAWING_1", 0.20, , [ 240.0, -29.0, 245.0, -34.0 ] ); // Lower witness line $$path( "DRAWING_1", 0.20, , [ 230.0, -29.0, 240.0, -29.0 ] ); // Lower witness line $$path( "DRAWING_1", 0.20, , [ 225.0, -34.0, 230.0, -29.0 ] ); // Lower witness line $$path( "DRAWING_1", 0.20, , [ 194.0, -34.0, 225.0, -34.0 ] ); // Lower witness line $$path( "DRAWING_1", 0.20, , [ 275.0, -23.5, 275.0, -34.0 ] ); // dimension line $$path( "DRAWING_1", 0.20, , [ 272.0, -26.5, 275.0, -34.0 ] ); // arrow $$path( "DRAWING_1", 0.20, , [ 278.0, -26.5, 275.0, -34.0 ] ); // arrow $$text( "DRAWING_1", "34.00 mm", 275.0, -17.0, 4.0, @CC, 0, 1.00, 0.20, "std", "None", 0.0, 0.0 ); // // End of the Drawing_1 overall board dimensions. // // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // Area Fills on Signal Layer 11 <--- // ---------------------------==== // // // // Original Rev. 4-July-2024 // Current Rev. 19-Feb-2025 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_11 are: // // ADC_DIGITAL_1V0 to the PMT ADC AD9083 about 971 mA // ADC_ANALOG_1V8 to the PMT ADC AD9083 about 102 mA // ADC_ANALOG_1V0 1/2 length run up to bypass under PMT ADC // BULK_1V0 under DCDC-1 and L601 and L603 // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_11 fill file is repeated // on both the layers: DIELECTRIC_1 and SHAPE_EDIT. // See the bottom section of this file. // // - As of 25-Nov-2024 there are 6 shapes defined in this file. // // // Net: ADC_DIGITAL_1V0 about 971 mA // // Fill Layer: Signal_11 12 mm wide // // Location: West and South of U601 the PMT ADC down to L603 // // Resolution: Medium // $$initial([ 167.5, 138.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 167.0, 139.0 ] ); $$terminal([ 154.9, 139.0 ] ); // Go most of the way West across the Top $$terminal([ 154.4, 138.5 ] ); $$terminal([ 154.4, 77.7 ] ); // Go Down the West Edge. $$terminal([ 154.9, 77.2 ] ); $$terminal([ 165.9, 77.2 ] ); // Go back East across the bottom most of the way. $$terminal([ 166.4, 77.7 ] ); $$terminal([ 166.4, 103.1 ] ); // Go North up the East edge - to where bypass starts # 102.5 $$terminal([ 167.5, 104.2 ] ); // Jog 45 deg NE to get the rest of the way East. // // Start the notch for the Verfy High Res Fill $$terminal([ 167.5, 114.5 ] ); // Go North up to where the PMT_ADC Very_High Res Fill starts $$terminal([ 167.0, 115.0 ] ); $$terminal([ 161.5, 115.0 ] ); // Go West around but over lapping the Very_High Res Fill $$terminal([ 161.0, 115.5 ] ); $$terminal([ 161.0, 124.5 ] ); // Go North up to the top of the Very_High Res Fill $$terminal([ 161.5, 125.0 ] ); $$terminal([ 167.0, 125.0 ] ); // Go East back to our normal boarder $$terminal([ 167.5, 125.5 ] ); // // Finish the notch for the Verfy High Res Fill $$terminal([ 167.5, 138.5 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: ADC_DIGITAL_1V0 about 971 mA // // Fill Layer: Signal_11 7.5 mm wide // // Location: Only under the West part of U601 the PMT ADC // // Resolution: Very High // $$initial([ 167.5, 125.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 167.0, 126.2 ] ); $$terminal([ 160.3, 126.2 ] ); // Go West across the Top $$terminal([ 159.8, 125.7 ] ); $$terminal([ 159.8, 114.3 ] ); // Go Down the West Edge. $$terminal([ 160.3, 113.8 ] ); $$terminal([ 167.0, 113.8 ] ); // Go back East across the bottom $$terminal([ 167.5, 114.3 ] ); $$terminal([ 167.5, 125.7 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: ADC_ANALOG_1V8 about 102 mA // // Fill Layer: Signal_11 12.3 mm wide // // Location: East and North of U601 the PMT ADC up to L602 // // Resolution: Medium // $$initial([ 180.3, 167.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 179.8, 167.8 ] ); $$terminal([ 168.2, 167.8 ] ); // Go most of the way West across the Top $$terminal([ 167.7, 167.3 ] ); // // Start the notch for the Verfy High Res Fill $$terminal([ 167.7, 125.5 ] ); // Go South down to where the PMT_ADC Very_High Res Fill starts $$terminal([ 168.2, 125.0 ] ); $$terminal([ 172.7, 125.0 ] ); // Go East around but over lapping the Very_High Res Fill $$terminal([ 173.2, 124.5 ] ); $$terminal([ 173.2, 115.5 ] ); // Go South down to the base of the Very_High Res Fill $$terminal([ 172.7, 115.0 ] ); $$terminal([ 168.2, 115.0 ] ); // Go West back to our normal boarder $$terminal([ 167.7, 114.5 ] ); // // Finish the notch for the Verfy High Res Fill $$terminal([ 167.7, 104.1 ] ); // Go Down the West Edge. $$terminal([ 168.2, 103.6 ] ); $$terminal([ 179.8, 103.6 ] ); // Go East across the bottom. $$terminal([ 180.3, 104.1 ] ); $$terminal([ 180.3, 167.3 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: ADC_ANALOG_1V8 about 102 mA // // Fill Layer: Signal_11 6.2 mm wide // // Location: Only Under the East part of U601 the PMT ADC // // Resolution: Very High // $$initial([ 174.4, 125.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 173.9, 126.2 ] ); $$terminal([ 168.2, 126.2 ] ); // Go West across the Top $$terminal([ 167.7, 125.7 ] ); $$terminal([ 167.7, 114.3 ] ); // Go Down the West Edge. $$terminal([ 168.2, 113.8 ] ); $$terminal([ 173.9, 113.8 ] ); // Go East across the bottom. $$terminal([ 174.4, 114.3 ] ); $$terminal([ 174.4, 125.7 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: ADC_Analog_1V0 about 471 mA half for half length // -------------------- // Fill Layer: Signal_11 14.3 mm wide // // Location: 1/2 length East side only Under the U601 bypass caps // ---------- // // Resolution: Medium // $$initial([ 180.3, 102.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 179.8, 103.0 ] ); $$terminal([ 167.2, 103.0 ] ); // Go most of the way West across the Top $$terminal([ 166.7, 102.5 ] ); $$terminal([ 166.7, 77.7 ] ); // Go Down the West Edge. $$terminal([ 167.2, 77.2 ] ); $$terminal([ 179.8, 77.2 ] ); // Go East across the bottom. $$terminal([ 180.3, 77.7 ] ); $$terminal([ 180.3, 102.5 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: BULK_1V0 about 1442 mA // // Fill Layer: Signal_11 // // Location: Under DCDC-1 Output and L601 and L603 // // Resolution: Medium // $$initial([ 199.5, 61.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 199.0, 62.0 ] ); $$terminal([ 187.7, 62.0 ] ); // Go West until we can break further North # 186.9 $$terminal([ 178.8, 70.9 ] ); // Run NW at 45 deg $$terminal([ 178.8, 74.5 ] ); // Run North as far as we can go $$terminal([ 178.3, 75.0 ] ); $$terminal([ 155.2, 75.0 ] ); // Run West as far as we can go $$terminal([ 154.7, 74.5 ] ); $$terminal([ 154.7, 61.6 ] ); // Run South until bump into Timing Gen $$terminal([ 155.2, 61.1 ] ); $$terminal([ 165.6, 61.1 ] ); // Run East to clear the Timing Gen # 165.6 $$terminal([ 190.3, 36.4 ] ); // Run 45 deg SE to get back down to DCDC-1 $$terminal([ 199.0, 36.4 ] ); // Run East under part of DCDC-1 $$terminal([ 199.5, 36.9 ] ); $$terminal([ 199.5, 61.5 ] ); // Go North up through DCDC-1 back home $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_1", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: ADC_DIGITAL_1V0 about 971 mA // // Fill Layer: Signal_11 12 mm wide // // Location: West and South of U601 the PMT ADC down to L603 // // Resolution: Medium // $$initial([ 167.5, 138.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 167.0, 139.0 ] ); $$terminal([ 154.9, 139.0 ] ); // Go most of the way West across the Top $$terminal([ 154.4, 138.5 ] ); $$terminal([ 154.4, 77.7 ] ); // Go Down the West Edge. $$terminal([ 154.9, 77.2 ] ); $$terminal([ 165.9, 77.2 ] ); // Go back East across the bottom most of the way. $$terminal([ 166.4, 77.7 ] ); $$terminal([ 166.4, 103.1 ] ); // Go North up the East edge - to where bypass starts # 102.5 $$terminal([ 167.5, 104.2 ] ); // Jog 45 deg NE to get the rest of the way East. // // Start the notch for the Verfy High Res Fill $$terminal([ 167.5, 114.5 ] ); // Go North up to where the PMT_ADC Very_High Res Fill starts $$terminal([ 167.0, 115.0 ] ); $$terminal([ 161.5, 115.0 ] ); // Go West around but over lapping the Very_High Res Fill $$terminal([ 161.0, 115.5 ] ); $$terminal([ 161.0, 124.5 ] ); // Go North up to the top of the Very_High Res Fill $$terminal([ 161.5, 125.0 ] ); $$terminal([ 167.0, 125.0 ] ); // Go East back to our normal boarder $$terminal([ 167.5, 125.5 ] ); // // Finish the notch for the Verfy High Res Fill $$terminal([ 167.5, 138.5 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // Net: ADC_DIGITAL_1V0 about 971 mA // // Fill Layer: Signal_11 7.5 mm wide // // Location: Only under the West part of U601 the PMT ADC // // Resolution: Very High // $$initial([ 167.5, 125.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 167.0, 126.2 ] ); $$terminal([ 160.3, 126.2 ] ); // Go West across the Top $$terminal([ 159.8, 125.7 ] ); $$terminal([ 159.8, 114.3 ] ); // Go Down the West Edge. $$terminal([ 160.3, 113.8 ] ); $$terminal([ 167.0, 113.8 ] ); // Go back East across the bottom $$terminal([ 167.5, 114.3 ] ); $$terminal([ 167.5, 125.7 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // Net: ADC_ANALOG_1V8 about 102 mA // // Fill Layer: Signal_11 12.3 mm wide // // Location: East and North of U601 the PMT ADC up to L602 // // Resolution: Medium // $$initial([ 180.3, 167.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 179.8, 167.8 ] ); $$terminal([ 168.2, 167.8 ] ); // Go most of the way West across the Top $$terminal([ 167.7, 167.3 ] ); // // Start the notch for the Verfy High Res Fill $$terminal([ 167.7, 125.5 ] ); // Go South down to where the PMT_ADC Very_High Res Fill starts $$terminal([ 168.2, 125.0 ] ); $$terminal([ 172.7, 125.0 ] ); // Go East around but over lapping the Very_High Res Fill $$terminal([ 173.2, 124.5 ] ); $$terminal([ 173.2, 115.5 ] ); // Go South down to the base of the Very_High Res Fill $$terminal([ 172.7, 115.0 ] ); $$terminal([ 168.2, 115.0 ] ); // Go West back to our normal boarder $$terminal([ 167.7, 114.5 ] ); // // Finish the notch for the Verfy High Res Fill $$terminal([ 167.7, 104.1 ] ); // Go Down the West Edge. $$terminal([ 168.2, 103.6 ] ); $$terminal([ 179.8, 103.6 ] ); // Go East across the bottom. $$terminal([ 180.3, 104.1 ] ); $$terminal([ 180.3, 167.3 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // Net: ADC_ANALOG_1V8 about 102 mA // // Fill Layer: Signal_11 6.2 mm wide // // Location: Only Under the East part of U601 the PMT ADC // // Resolution: Very High // $$initial([ 174.4, 125.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 173.9, 126.2 ] ); $$terminal([ 168.2, 126.2 ] ); // Go West across the Top $$terminal([ 167.7, 125.7 ] ); $$terminal([ 167.7, 114.3 ] ); // Go Down the West Edge. $$terminal([ 168.2, 113.8 ] ); $$terminal([ 173.9, 113.8 ] ); // Go East across the bottom. $$terminal([ 174.4, 114.3 ] ); $$terminal([ 174.4, 125.7 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // Net: ADC_Analog_1V0 about 471 mA half for half length // -------------------- // Fill Layer: Signal_11 14.3 mm wide // // Location: 1/2 length East side only Under the U601 bypass caps // ---------- // // Resolution: Medium // $$initial([ 180.3, 102.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 179.8, 103.0 ] ); $$terminal([ 167.2, 103.0 ] ); // Go most of the way West across the Top $$terminal([ 166.7, 102.5 ] ); $$terminal([ 166.7, 77.7 ] ); // Go Down the West Edge. $$terminal([ 167.2, 77.2 ] ); $$terminal([ 179.8, 77.2 ] ); // Go East across the bottom. $$terminal([ 180.3, 77.7 ] ); $$terminal([ 180.3, 102.5 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // Net: BULK_1V0 about 1442 mA // // Fill Layer: Signal_11 // // Location: Under DCDC-1 Output and L601 and L603 // // Resolution: Medium // $$initial([ 199.5, 61.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 199.0, 62.0 ] ); $$terminal([ 187.7, 62.0 ] ); // Go West until we can break further North # 186.9 $$terminal([ 178.8, 70.9 ] ); // Run NW at 45 deg $$terminal([ 178.8, 74.5 ] ); // Run North as far as we can go $$terminal([ 178.3, 75.0 ] ); $$terminal([ 155.2, 75.0 ] ); // Run West as far as we can go $$terminal([ 154.7, 74.5 ] ); $$terminal([ 154.7, 61.6 ] ); // Run South until bump into Timing Gen $$terminal([ 155.2, 61.1 ] ); $$terminal([ 165.6, 61.1 ] ); // Run East to clear the Timing Gen # 165.6 $$terminal([ 190.3, 36.4 ] ); // Run 45 deg SE to get back down to DCDC-1 $$terminal([ 199.0, 36.4 ] ); // Run East under part of DCDC-1 $$terminal([ 199.5, 36.9 ] ); $$terminal([ 199.5, 61.5 ] ); // Go North up through DCDC-1 back home $$path( "DIELECTRIC_1", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // Area Fills on Signal Layer 12 <--- // ---------------------------==== // // // // Original Rev. 4-July-2024 // Current Rev. 19-Feb-2025 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_12 are: // // ADC_Analog_1V0 to the PMT ADC AD9083 about 471 mA // ADC_Digital_1V8 to the PMT ADC AD9083 about 48 mA // ADC_Digital_1V0 1/2 length run up to bypass under PMT ADC // ADC_Analog_1V8 1/2 length run down to bypass above PMT ADC // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_12 fill file is repeated // on both the layers: DIELECTRIC_2 and SHAPE_EDIT. // See the bottom section of this file. // // - As of 26-Nov-2024 there are 6 shapes defined in this file. // // // Net: ADC_Digital_1V8 about 48 mA // // Fill Layer: Signal_12 13.0 mm wide // // Location: West of U601 the PMT ADC and North up to L604 // // Resolution: Medium // $$initial([ 167.4, 167.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 166.9, 167.8 ] ); $$terminal([ 157.0, 167.8 ] ); // Go most of the way West across the Top $$terminal([ 156.5, 167.3 ] ); $$terminal([ 156.5, 159.0 ] ); // Go South Down past the Clk Gen fill to the West $$terminal([ 156.0, 158.5 ] ); $$terminal([ 154.9, 158.5 ] ); // Go West the rest of the way to our full width $$terminal([ 154.4, 158.0 ] ); $$terminal([ 154.4, 104.1 ] ); // Go Down the West Edge. $$terminal([ 154.9, 103.6 ] ); $$terminal([ 165.0, 103.6 ] ); // Go East across the bottom. $$terminal([ 165.5, 104.1 ] ); // // Start the notch for the Verfy High Res Fill $$terminal([ 165.5, 114.5 ] ); // Go North up to where the PMT_ADC Very_High Res Fill starts $$terminal([ 165.0, 115.0 ] ); $$terminal([ 161.3, 115.0 ] ); // Go West around but over lapping the Very_High Res Fill $$terminal([ 160.8, 115.5 ] ); $$terminal([ 160.8, 124.5 ] ); // Go North up to the top of the Very_High Res Fill $$terminal([ 161.3, 125.0 ] ); $$terminal([ 165.0, 125.0 ] ); // Go East back to our normal boarder $$terminal([ 165.5, 125.5 ] ); // // Finish the notch for the Verfy High Res Fill $$terminal([ 165.5, 136.1 ] ); // Go North up past the bypass caps on East edge # 135.7 $$terminal([ 167.4, 138.0 ] ); // Jog NE at 45 deg to get full width $$terminal([ 167.4, 167.3 ] ); // Go North and back home $$path( "SHAPE_EDIT", 0.0 ); // // Net: ADC_Digital_1V8 about 48 mA // // Fill Layer: Signal_12 5.5 mm wide // // Location: Only under the West side of U601 the PMT ADC // // Resolution: Very High // $$initial([ 165.5, 125.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 165.0, 126.2 ] ); $$terminal([ 160.5, 126.2 ] ); // Go West across the Top $$terminal([ 160.0, 125.7 ] ); $$terminal([ 160.0, 114.3 ] ); // Go Down the West Edge. $$terminal([ 160.5, 113.8 ] ); $$terminal([ 165.0, 113.8 ] ); // Go back East across the bottom $$terminal([ 165.5, 114.3 ] ); $$terminal([ 165.5, 125.7 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: ADC_Analog_1V0 about 471 mA // // Fill Layer: Signal_12 13.4 mm wide // // Location: East of U601 the PMT ADC and South down to L601 // // Resolution: Medium // $$initial([ 180.3, 135.9], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 179.8, 136.4 ] ); $$terminal([ 166.2, 136.4 ] ); // Go the full way West across the Top $$terminal([ 165.7, 135.9 ] ); // // Start the notch for the Verfy High Res Fill $$terminal([ 165.7, 125.5 ] ); // Go South down to where the PMT_ADC Very_High Res Fill starts $$terminal([ 166.2, 125.0 ] ); $$terminal([ 172.9, 125.0 ] ); // Go East around but over lapping the Very_High Res Fill $$terminal([ 173.4, 124.5 ] ); $$terminal([ 173.4, 115.5 ] ); // Go South down to the base of the Very_High Res Fill $$terminal([ 172.9, 115.0 ] ); $$terminal([ 166.2, 115.0 ] ); // Go West back to our normal boarder $$terminal([ 165.7, 114.5 ] ); // // Finish the notch for the Verfy High Res Fill $$terminal([ 165.7, 104.0 ] ); // Go Down the West Edge past the bypass caps # 103.6 $$terminal([ 166.6, 103.1 ] ); // Jog 45 deg SE $$terminal([ 166.6, 77.7 ] ); // Run South the rest of the way down to L601 $$terminal([ 167.1, 77.2 ] ); $$terminal([ 179.8, 77.2 ] ); // Go East across the bottom. $$terminal([ 180.3, 77.7 ] ); $$terminal([ 180.3, 135.9 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: ADC_Analog_1V0 about 471 mA // // Fill Layer: Signal_11 8.7 mm wide // // Location: Only Under the East part of U601 the PMT ADC // // Resolution: Very High // $$initial([ 174.2, 125.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 173.7, 126.2 ] ); $$terminal([ 166.2, 126.2 ] ); // Go West across the Top $$terminal([ 165.7, 125.7 ] ); $$terminal([ 165.7, 114.3 ] ); // Go Down the West Edge. $$terminal([ 166.2, 113.8 ] ); $$terminal([ 173.7, 113.8 ] ); // Go East across the bottom. $$terminal([ 174.2, 114.3 ] ); $$terminal([ 174.2, 125.7 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: ADC_Digital_1V0 about 971 mA half for half length // -------------------- // Fill Layer: Signal_12 12 mm wide // // Location: 1/2 length West side only Under the U601 bypass caps // ---------- // // Resolution: Medium // $$initial([ 166.3, 102.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 165.8, 103.0 ] ); $$terminal([ 154.9, 103.0 ] ); // Go most of the way West across the Top $$terminal([ 154.4, 102.5 ] ); $$terminal([ 154.4, 77.7 ] ); // Go Down the West Edge. $$terminal([ 154.9, 77.2 ] ); $$terminal([ 165.8, 77.2 ] ); // Go East across the bottom. $$terminal([ 166.3, 77.7 ] ); $$terminal([ 166.3, 102.5 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: ADC_Analog_1V8 about 102 mA half for half length // -------------------- // Fill Layer: Signal_12 12.3 mm wide // // Location: 1/2 length West side only Under the U601 bypass caps // ---------- // // Resolution: Medium // $$initial([ 180.3, 167.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 179.8, 167.8 ] ); $$terminal([ 168.2, 167.8 ] ); // Go most of the way West across the Top $$terminal([ 167.7, 167.3 ] ); $$terminal([ 167.7, 137.5 ] ); // Go Down the West Edge. $$terminal([ 168.2, 137.0 ] ); $$terminal([ 179.8, 137.0 ] ); // Go East across the bottom. $$terminal([ 180.3, 137.5 ] ); $$terminal([ 180.3, 167.3 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_2", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: ADC_Digital_1V8 about 48 mA // // Fill Layer: Signal_12 13.0 mm wide // // Location: West of U601 the PMT ADC and North up to L604 // // Resolution: Medium // $$initial([ 167.4, 167.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 166.9, 167.8 ] ); $$terminal([ 157.0, 167.8 ] ); // Go most of the way West across the Top $$terminal([ 156.5, 167.3 ] ); $$terminal([ 156.5, 159.0 ] ); // Go South Down past the Clk Gen fill to the West $$terminal([ 156.0, 158.5 ] ); $$terminal([ 154.9, 158.5 ] ); // Go West the rest of the way to our full width $$terminal([ 154.4, 158.0 ] ); $$terminal([ 154.4, 104.1 ] ); // Go Down the West Edge. $$terminal([ 154.9, 103.6 ] ); $$terminal([ 165.0, 103.6 ] ); // Go East across the bottom. $$terminal([ 165.5, 104.1 ] ); // // Start the notch for the Verfy High Res Fill $$terminal([ 165.5, 114.5 ] ); // Go North up to where the PMT_ADC Very_High Res Fill starts $$terminal([ 165.0, 115.0 ] ); $$terminal([ 161.3, 115.0 ] ); // Go West around but over lapping the Very_High Res Fill $$terminal([ 160.8, 115.5 ] ); $$terminal([ 160.8, 124.5 ] ); // Go North up to the top of the Very_High Res Fill $$terminal([ 161.3, 125.0 ] ); $$terminal([ 165.0, 125.0 ] ); // Go East back to our normal boarder $$terminal([ 165.5, 125.5 ] ); // // Finish the notch for the Verfy High Res Fill $$terminal([ 165.5, 136.1 ] ); // Go North up past the bypass caps on East edge # 135.7 $$terminal([ 167.4, 138.0 ] ); // Jog NE at 45 deg to get full width $$terminal([ 167.4, 167.3 ] ); // Go North and back home $$path( "DIELECTRIC_2", 0.0 ); // // Net: ADC_Digital_1V8 about 48 mA // // Fill Layer: Signal_12 5.5 mm wide // // Location: Only under the West side of U601 the PMT ADC // // Resolution: Very High // $$initial([ 165.5, 125.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 165.0, 126.2 ] ); $$terminal([ 160.5, 126.2 ] ); // Go West across the Top $$terminal([ 160.0, 125.7 ] ); $$terminal([ 160.0, 114.3 ] ); // Go Down the West Edge. $$terminal([ 160.5, 113.8 ] ); $$terminal([ 165.0, 113.8 ] ); // Go back East across the bottom $$terminal([ 165.5, 114.3 ] ); $$terminal([ 165.5, 125.7 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // Net: ADC_Analog_1V0 about 471 mA // // Fill Layer: Signal_12 13.4 mm wide // // Location: East of U601 the PMT ADC and South down to L601 // // Resolution: Medium // $$initial([ 180.3, 135.9], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 179.8, 136.4 ] ); $$terminal([ 166.2, 136.4 ] ); // Go the full way West across the Top $$terminal([ 165.7, 135.9 ] ); // // Start the notch for the Verfy High Res Fill $$terminal([ 165.7, 125.5 ] ); // Go South down to where the PMT_ADC Very_High Res Fill starts $$terminal([ 166.2, 125.0 ] ); $$terminal([ 172.9, 125.0 ] ); // Go East around but over lapping the Very_High Res Fill $$terminal([ 173.4, 124.5 ] ); $$terminal([ 173.4, 115.5 ] ); // Go South down to the base of the Very_High Res Fill $$terminal([ 172.9, 115.0 ] ); $$terminal([ 166.2, 115.0 ] ); // Go West back to our normal boarder $$terminal([ 165.7, 114.5 ] ); // // Finish the notch for the Verfy High Res Fill $$terminal([ 165.7, 104.0 ] ); // Go Down the West Edge past the bypass caps # 103.6 $$terminal([ 166.6, 103.1 ] ); // Jog 45 deg SE $$terminal([ 166.6, 77.7 ] ); // Run South the rest of the way down to L601 $$terminal([ 167.1, 77.2 ] ); $$terminal([ 179.8, 77.2 ] ); // Go East across the bottom. $$terminal([ 180.3, 77.7 ] ); $$terminal([ 180.3, 135.9 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // Net: ADC_Analog_1V0 about 471 mA // // Fill Layer: Signal_11 8.7 mm wide // // Location: Only Under the East part of U601 the PMT ADC // // Resolution: Very High // $$initial([ 174.2, 125.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 173.7, 126.2 ] ); $$terminal([ 166.2, 126.2 ] ); // Go West across the Top $$terminal([ 165.7, 125.7 ] ); $$terminal([ 165.7, 114.3 ] ); // Go Down the West Edge. $$terminal([ 166.2, 113.8 ] ); $$terminal([ 173.7, 113.8 ] ); // Go East across the bottom. $$terminal([ 174.2, 114.3 ] ); $$terminal([ 174.2, 125.7 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // Net: ADC_Digital_1V0 about 971 mA half for half length // -------------------- // Fill Layer: Signal_12 12 mm wide // // Location: 1/2 length West side only Under the U601 bypass caps // ---------- // // Resolution: Medium // $$initial([ 166.3, 102.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 165.8, 103.0 ] ); $$terminal([ 154.9, 103.0 ] ); // Go most of the way West across the Top $$terminal([ 154.4, 102.5 ] ); $$terminal([ 154.4, 77.7 ] ); // Go Down the West Edge. $$terminal([ 154.9, 77.2 ] ); $$terminal([ 165.8, 77.2 ] ); // Go East across the bottom. $$terminal([ 166.3, 77.7 ] ); $$terminal([ 166.3, 102.5 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // Net: ADC_Analog_1V8 about 102 mA half for half length // -------------------- // Fill Layer: Signal_12 12.3 mm wide // // Location: 1/2 length West side only Under the U601 bypass caps // ---------- // // Resolution: Medium // $$initial([ 180.3, 167.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 179.8, 167.8 ] ); $$terminal([ 168.2, 167.8 ] ); // Go most of the way West across the Top $$terminal([ 167.7, 167.3 ] ); $$terminal([ 167.7, 137.5 ] ); // Go Down the West Edge. $$terminal([ 168.2, 137.0 ] ); $$terminal([ 179.8, 137.0 ] ); // Go East across the bottom. $$terminal([ 180.3, 137.5 ] ); $$terminal([ 180.3, 167.3 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // CNST_3V3 and RESCUE_3V3 Area Fills on Signal Layer 12 <--- // ==========---============----------------------------==== // // // // Original Rev. 4-July-2024 // Current Rev. 18-Nov-2024 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_12 in this file are: // // CNST_3V3 area under the discrete logic about 10 mA // RESCUE_3V3 area under the Emergency Rescue uProcessor about 10 mA // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_12 fill file is repeated // on both the layers: DIELECTRIC_2 and SHAPE_EDIT. // See the bottom section of this file. // // - As of 22-July-2024 there are 2 shapes defined in this file. // // // Net: CNST_3V3 about 10 mA // // Fill Layer: Signal_12 // // Location: under the section of discrete logic for Startup and Resets // // Resolution: Medium // $$initial([ 61.8, 114.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 61.3, 115.0 ] ); $$terminal([ 49.5, 115.0 ] ); // Go West part way across the top $$terminal([ 49.0, 114.5 ] ); $$terminal([ 49.0, 95.5 ] ); // Go South down the West edge $$terminal([ 48.5, 95.0 ] ); $$terminal([ 44.5, 95.0 ] ); // Go West some more $$terminal([ 44.0, 94.5 ] ); $$terminal([ 44.0, 93.0 ] ); // Go South to get more width for another fill $$terminal([ 43.5, 92.5 ] ); $$terminal([ 35.3, 92.5 ] ); // Go West the rest of the way $$terminal([ 34.8, 92.0 ] ); $$terminal([ 34.8, 44.7 ] ); // Go South down the West edge $$terminal([ 35.3, 44.2 ] ); $$terminal([ 63.5, 44.2 ] ); // Go East across the bottom. $$terminal([ 64.0, 44.7 ] ); $$terminal([ 64.0, 52.0 ] ); // Go North up to just below C1656 $$terminal([ 63.5, 52.5 ] ); $$terminal([ 62.3, 52.5 ] ); // Go West to clear the C1656 pin $$terminal([ 61.8, 53.0 ] ); $$terminal([ 61.8, 64.0 ] ); // Go North to clear the C1656 pin $$terminal([ 62.3, 64.5 ] ); $$terminal([ 63.5, 64.5 ] ); // Go East back to the normal boarder $$terminal([ 64.0, 65.0 ] ); $$terminal([ 64.0, 97.5 ] ); // Go North up to just below C1653 $$terminal([ 63.5, 98.0 ] ); $$terminal([ 62.3, 98.0 ] ); // Go West to clear the C1653 pin $$terminal([ 61.8, 98.5 ] ); $$terminal([ 61.8, 114.5 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: RESCUE_3V3 about 10 mA // // Fill Layer: Signal_12 // // Location: under the Emergency Rescue uProcessor section // // Resolution: Medium // $$initial([ 62.2, 140.0], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 61.7, 140.5 ] ); $$terminal([ 42.7, 140.5 ] ); // Go West across the top $$terminal([ 42.2, 140.0 ] ); $$terminal([ 42.2, 119.7 ] ); // Go South down the West edge $$terminal([ 42.7, 119.2 ] ); $$terminal([ 61.7, 119.2 ] ); // Go East across the bottom. $$terminal([ 62.2, 119.7 ] ); $$terminal([ 62.2, 140.0 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_2", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: CNST_3V3 about 10 mA // // Fill Layer: Signal_12 // // Location: under the section of discrete logic for Startup and Resets // // Resolution: Medium // $$initial([ 61.8, 114.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 61.3, 115.0 ] ); $$terminal([ 49.5, 115.0 ] ); // Go West part way across the top $$terminal([ 49.0, 114.5 ] ); $$terminal([ 49.0, 95.5 ] ); // Go South down the West edge $$terminal([ 48.5, 95.0 ] ); $$terminal([ 44.5, 95.0 ] ); // Go West some more $$terminal([ 44.0, 94.5 ] ); $$terminal([ 44.0, 93.0 ] ); // Go South to get more width for another fill $$terminal([ 43.5, 92.5 ] ); $$terminal([ 35.3, 92.5 ] ); // Go West the rest of the way $$terminal([ 34.8, 92.0 ] ); $$terminal([ 34.8, 44.7 ] ); // Go South down the West edge $$terminal([ 35.3, 44.2 ] ); $$terminal([ 63.5, 44.2 ] ); // Go East across the bottom. $$terminal([ 64.0, 44.7 ] ); $$terminal([ 64.0, 52.0 ] ); // Go North up to just below C1656 $$terminal([ 63.5, 52.5 ] ); $$terminal([ 62.3, 52.5 ] ); // Go West to clear the C1656 pin $$terminal([ 61.8, 53.0 ] ); $$terminal([ 61.8, 64.0 ] ); // Go North to clear the C1656 pin $$terminal([ 62.3, 64.5 ] ); $$terminal([ 63.5, 64.5 ] ); // Go East back to the normal boarder $$terminal([ 64.0, 65.0 ] ); $$terminal([ 64.0, 97.5 ] ); // Go North up to just below C1653 $$terminal([ 63.5, 98.0 ] ); $$terminal([ 62.3, 98.0 ] ); // Go West to clear the C1653 pin $$terminal([ 61.8, 98.5 ] ); $$terminal([ 61.8, 114.5 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // Net: RESCUE_3V3 about 10 mA // // Fill Layer: Signal_12 // // Location: under the Emergency Rescue uProcessor section // // Resolution: Medium // $$initial([ 62.2, 140.0], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 61.7, 140.5 ] ); $$terminal([ 42.7, 140.5 ] ); // Go West across the top $$terminal([ 42.2, 140.0 ] ); $$terminal([ 42.2, 119.7 ] ); // Go South down the West edge $$terminal([ 42.7, 119.2 ] ); $$terminal([ 61.7, 119.2 ] ); // Go East across the bottom. $$terminal([ 62.2, 119.7 ] ); $$terminal([ 62.2, 140.0 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // BULK_1V8 Area Fills on Signal Layer 12 <--- // ==========----------------------------==== // // // // Original Rev. 4-July-2024 // Current Rev. 7-Jan-2025 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_12 in this file are: // // BULK_1V8 to 3x filter inductors and many other areas // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_12 fill file is repeated // on both the layers: DIELECTRIC_2 and SHAPE_EDIT. // See the bottom section of this file. // // - As of 22-July-2024 there is 1 shapes defined in this file. // // // Net: BULK_1V8 about 850 mA // // Fill Layer: Signal_12 // // Location: North-East Corner and around the perimeter // // Resolution: Medium // $$initial([ 221.0, 231.0], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 220.0, 232.0 ] ); $$terminal([ 184.0, 232.0 ] ); // Go most of the way West across the Top $$terminal([ 183.0, 231.0 ] ); $$terminal([ 183.0, 226.5 ] ); // Go South to get below the cable screw block $$terminal([ 182.0, 225.5 ] ); $$terminal([ 131.0, 225.5 ] ); // Go West under the J4 connector $$terminal([ 130.0, 226.5 ] ); $$terminal([ 130.0, 227.5 ] ); // Go North for a good feed to both J4 and J5 $$terminal([ 129.0, 228.5 ] ); $$terminal([ 122.5, 228.5 ] ); // Go West to where we need to start around the Mounting Screw $$terminal([ 121.5, 227.5 ] ); $$terminal([ 121.5, 226.0 ] ); // Go South to get under the Mounting Screw $$terminal([ 120.5, 225.0 ] ); $$terminal([ 114.5, 225.0 ] ); // Go West under the Mounting Screw to its West Side $$terminal([ 113.5, 226.0 ] ); $$terminal([ 113.5, 227.5 ] ); // Go North back up to our normal run line - now past the Screw $$terminal([ 112.5, 228.5 ] ); $$terminal([ 106.0, 228.5 ] ); // Go West between J4 and J5 $$terminal([ 105.0, 227.5 ] ); $$terminal([ 105.0, 226.5 ] ); // Go South to get positioned for the run under J5 $$terminal([ 104.0, 225.5 ] ); $$terminal([ 45.0, 225.5 ] ); // Go West under J5 all the way to just East of U1401 $$terminal([ 44.0, 224.5 ] ); $$terminal([ 44.0, 220.0 ] ); // Go South to get under U1401 and U1402 $$terminal([ 43.0, 219.0 ] ); $$terminal([ 18.5, 219.0 ] ); // Go West to where we can start the 45 deg cut past the USB connector $$terminal([ 3.0, 203.5 ] ); // Go SW in a 45 deg cut past USB conn J16 $$terminal([ 3.0, 168.0 ] ); // Go South down to just above the Main Cable Ground Slit $$terminal([ 4.0, 167.0 ] ); $$terminal([ 17.0, 167.0 ] ); // Go East to the jog in the Main Cable Ground Slit $$terminal([ 18.0, 166.0 ] ); $$terminal([ 18.0, 161.0 ] ); // Go South along the jog in the Main Cable Ground Slit $$terminal([ 19.0, 160.0 ] ); $$terminal([ 50.0, 160.0 ] ); // Go East to just short of the BULK_5V0 Fill $$terminal([ 51.0, 161.0 ] ); $$terminal([ 51.0, 169.0 ] ); // Go North up to just under the USB Phy chip U1051 $$terminal([ 50.0, 170.0 ] ); $$terminal([ 25.0, 170.0 ] ); // Go West to where we can run North in the middle of J12 Access conn $$terminal([ 24.0, 171.0 ] ); $$terminal([ 24.0, 206.5 ] ); // Go North up the middle of J12 to just above the BULK_5V0 Fill $$terminal([ 25.0, 207.5 ] ); $$terminal([ 93.0, 207.5 ] ); // Go East start of run back to area of DCDC4 $$terminal([ 94.0, 208.5 ] ); $$terminal([ 94.0, 209.5 ] ); // Go North to get above the feed to DCDC5 via R1821 $$terminal([ 95.0, 210.5 ] ); $$terminal([ 103.0, 210.5 ] ); // Go East across the top of R1821 $$terminal([ 104.0, 209.5 ] ); $$terminal([ 104.0, 208.0 ] ); // Go South to complete the run back to the area of DCDC4 $$terminal([ 105.0, 207.0 ] ); $$terminal([ 171.0, 207.0 ] ); // Go East back to the area of DCDC4 $$terminal([ 172.0, 206.0 ] ); $$terminal([ 172.0, 191.0 ] ); // Go South down to just below DCDC-4 $$terminal([ 171.0, 190.0 ] ); $$terminal([ 153.0, 190.0 ] ); // Go West to pick up the Filter Inductors $$terminal([ 152.0, 189.0 ] ); $$terminal([ 152.0, 171.0 ] ); // Go South to pick up the PMT ADC Filter Inductors $$terminal([ 153.0, 170.0 ] ); $$terminal([ 178.8, 170.0 ] ); // Go East to run over to the PMT Analog Input Section $$terminal([ 179.8, 171.0 ] ); $$terminal([ 179.8, 175.0 ] ); // Go North to get above the PMT Analog Input Section $$terminal([ 180.8, 176.0 ] ); $$terminal([ 231.0, 176.0 ] ); // Go East over to the East edge of the board $$terminal([ 232.0, 177.0 ] ); $$terminal([ 232.0, 220.0 ] ); // Go North up the East edge of the board $$terminal([ 231.0, 221.0 ] ); $$terminal([ 222.0, 221.0 ] ); // Go West to clear the mounting screw hole $$terminal([ 221.0, 222.0 ] ); $$terminal([ 221.0, 231.0 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_2" 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: BULK_1V8 about 850 mA // // Fill Layer: Signal_12 // // Location: North-East Corner and around the perimeter // // Resolution: Medium // $$initial([ 221.0, 231.0], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 220.0, 232.0 ] ); $$terminal([ 184.0, 232.0 ] ); // Go most of the way West across the Top $$terminal([ 183.0, 231.0 ] ); $$terminal([ 183.0, 226.5 ] ); // Go South to get below the cable screw block $$terminal([ 182.0, 225.5 ] ); $$terminal([ 131.0, 225.5 ] ); // Go West under the J4 connector $$terminal([ 130.0, 226.5 ] ); $$terminal([ 130.0, 227.5 ] ); // Go North for a good feed to both J4 and J5 $$terminal([ 129.0, 228.5 ] ); $$terminal([ 122.5, 228.5 ] ); // Go West to where we need to start around the Mounting Screw $$terminal([ 121.5, 227.5 ] ); $$terminal([ 121.5, 226.0 ] ); // Go South to get under the Mounting Screw $$terminal([ 120.5, 225.0 ] ); $$terminal([ 114.5, 225.0 ] ); // Go West under the Mounting Screw to its West Side $$terminal([ 113.5, 226.0 ] ); $$terminal([ 113.5, 227.5 ] ); // Go North back up to our normal run line - now past the Screw $$terminal([ 112.5, 228.5 ] ); $$terminal([ 106.0, 228.5 ] ); // Go West between J4 and J5 $$terminal([ 105.0, 227.5 ] ); $$terminal([ 105.0, 226.5 ] ); // Go South to get positioned for the run under J5 $$terminal([ 104.0, 225.5 ] ); $$terminal([ 45.0, 225.5 ] ); // Go West under J5 all the way to just East of U1401 $$terminal([ 44.0, 224.5 ] ); $$terminal([ 44.0, 220.0 ] ); // Go South to get under U1401 and U1402 $$terminal([ 43.0, 219.0 ] ); $$terminal([ 18.5, 219.0 ] ); // Go West to where we can start the 45 deg cut past the USB connector $$terminal([ 3.0, 203.5 ] ); // Go SW in a 45 deg cut past USB conn J16 $$terminal([ 3.0, 168.0 ] ); // Go South down to just above the Main Cable Ground Slit $$terminal([ 4.0, 167.0 ] ); $$terminal([ 17.0, 167.0 ] ); // Go East to the jog in the Main Cable Ground Slit $$terminal([ 18.0, 166.0 ] ); $$terminal([ 18.0, 161.0 ] ); // Go South along the jog in the Main Cable Ground Slit $$terminal([ 19.0, 160.0 ] ); $$terminal([ 50.0, 160.0 ] ); // Go East to just short of the BULK_5V0 Fill $$terminal([ 51.0, 161.0 ] ); $$terminal([ 51.0, 169.0 ] ); // Go North up to just under the USB Phy chip U1051 $$terminal([ 50.0, 170.0 ] ); $$terminal([ 25.0, 170.0 ] ); // Go West to where we can run North in the middle of J12 Access conn $$terminal([ 24.0, 171.0 ] ); $$terminal([ 24.0, 206.5 ] ); // Go North up the middle of J12 to just above the BULK_5V0 Fill $$terminal([ 25.0, 207.5 ] ); $$terminal([ 93.0, 207.5 ] ); // Go East start of run back to area of DCDC4 $$terminal([ 94.0, 208.5 ] ); $$terminal([ 94.0, 209.5 ] ); // Go North to get above the feed to DCDC5 via R1821 $$terminal([ 95.0, 210.5 ] ); $$terminal([ 103.0, 210.5 ] ); // Go East across the top of R1821 $$terminal([ 104.0, 209.5 ] ); $$terminal([ 104.0, 208.0 ] ); // Go South to complete the run back to the area of DCDC4 $$terminal([ 105.0, 207.0 ] ); $$terminal([ 171.0, 207.0 ] ); // Go East back to the area of DCDC4 $$terminal([ 172.0, 206.0 ] ); $$terminal([ 172.0, 191.0 ] ); // Go South down to just below DCDC-4 $$terminal([ 171.0, 190.0 ] ); $$terminal([ 153.0, 190.0 ] ); // Go West to pick up the Filter Inductors $$terminal([ 152.0, 189.0 ] ); $$terminal([ 152.0, 171.0 ] ); // Go South to pick up the PMT ADC Filter Inductors $$terminal([ 153.0, 170.0 ] ); $$terminal([ 178.8, 170.0 ] ); // Go East to run over to the PMT Analog Input Section $$terminal([ 179.8, 171.0 ] ); $$terminal([ 179.8, 175.0 ] ); // Go North to get above the PMT Analog Input Section $$terminal([ 180.8, 176.0 ] ); $$terminal([ 231.0, 176.0 ] ); // Go East over to the East edge of the board $$terminal([ 232.0, 177.0 ] ); $$terminal([ 232.0, 220.0 ] ); // Go North up the East edge of the board $$terminal([ 231.0, 221.0 ] ); $$terminal([ 222.0, 221.0 ] ); // Go West to clear the mounting screw hole $$terminal([ 221.0, 222.0 ] ); $$terminal([ 221.0, 231.0 ] ); // Go North - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // BULK_5V0 Area Fills on Signal Layer 12 <--- // ==========----------------------------==== // // // // Original Rev. 4-Oct-2024 // Current Rev. 7-Jan-2025 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_12 in this file are: // // BULK_5V0 from the +-50V to 5V converter output // to the 6x DCDC Converter inputs and // to other loads on the BULK_5V0 // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_12 fill file is repeated // on both the layers: DIELECTRIC_2 and SHAPE_EDIT. // See the bottom section of this file. // // - As of 4-Oct-2024 there is 1 shape defined in this file. // // // Net: BULK_5V up to 4 Amps // // Fill Layer: Signal_12 // // Location: West side and perimeter of North and South sides // // Resolution: Medium // $$initial([ 154.0, 205.0], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 153.5, 205.5 ] ); $$terminal([ 103.5, 205.5 ] ); // Go West across the top over to DCDC5 $$terminal([ 103.0, 206.0 ] ); $$terminal([ 103.0, 209.0 ] ); // Go North to feed DCDC5 via R1821 $$terminal([ 102.5, 209.5 ] ); $$terminal([ 95.5, 209.5 ] ); // Go West across the top of R1821 $$terminal([ 95.0, 209.0 ] ); $$terminal([ 95.0, 206.0 ] ); // Go South after the bump up to feed DCDC5 $$terminal([ 94.5, 205.5 ] ); $$terminal([ 34.5, 205.5 ] ); // Go West across the top over to DCDC6 $$terminal([ 34.0, 206.0 ] ); $$terminal([ 34.0, 206.0 ] ); // Go North to feed DCDC6 via R1851 $$terminal([ 33.5, 206.5 ] ); $$terminal([ 26.7, 206.5 ] ); // Go West across the top of R1851 $$terminal([ 26.2, 206.0 ] ); $$terminal([ 26.2, 171.5 ] ); // Go South down to just under the USB Phy chip U1051 $$terminal([ 26.7, 171.0 ] ); $$terminal([ 51.5, 171.0 ] ); // Go East to avoid the Main Cable HV $$terminal([ 52.0, 170.5 ] ); $$terminal([ 52.0, 145.5 ] ); // Go South down to under the RS-485 XCVR $$terminal([ 51.5, 145.0 ] ); $$terminal([ 40.5, 145.0 ] ); // Go West but keep out of the Main Cable stuff $$terminal([ 40.0, 144.5 ] ); $$terminal([ 40.0, 99.5 ] ); // Go South below the C1653 terminals $$terminal([ 39.5, 99.0 ] ); $$terminal([ 33.0, 99.0 ] ); // Go West but stay East of DCDC20 $$terminal([ 28.0, 94.0 ] ); // Go SW at an angle down to were we can start the run South $$terminal([ 28.0, 76.5 ] ); // Go South to below DCDC20 input section $$terminal([ 24.0, 72.5 ] ); // Go 45 deg SW to start run below DCDC20 input section $$terminal([ 2.0, 72.5 ] ); // Go West to pickup the DCDC20 Output Terms $$terminal([ 1.5, 72.0 ] ); $$terminal([ 1.5, 33.0 ] ); // Go South (sub 0.5 mm for miter) $$terminal([ 19.5, 15.0 ] ); // Go South-East at 45 deg to above Barnacle Connector $$terminal([ 67.5, 15.0 ] ); // Go East across the top of the Barnacle Connector $$terminal([ 68.0, 14.5 ] ); $$terminal([ 68.0, 3.5 ] ); // Go South down the East edge of the Barnacle Connector $$terminal([ 68.5, 3.0 ] ); $$terminal([ 112.0, 3.0 ] ); // Go East to where we need to start around the Mounting Screw $$terminal([ 112.5, 3.5 ] ); $$terminal([ 112.5, 10.5 ] ); // Go North to get above the Mounting Screw $$terminal([ 113.0, 11.0 ] ); $$terminal([ 122.0, 11.0 ] ); // Go East above the Mounting Screw to its East Side $$terminal([ 122.5, 10.5 ] ); $$terminal([ 122.5, 3.5 ] ); // Go South back up to our normal run line - now past the Screw $$terminal([ 123.0, 3.0 ] ); $$terminal([ 221.5, 3.0 ] ); // Go East past the SFPs and the BlackCat power feed $$terminal([ 222.0, 3.5 ] ); $$terminal([ 222.0, 12.5 ] ); // Go North to avoid the mounting screw hole $$terminal([ 222.5, 13.0 ] ); $$terminal([ 231.5, 13.0 ] ); // Go East to Brd edge to pick up DCDC1 $$terminal([ 232.0, 13.5 ] ); $$terminal([ 232.0, 36.5 ] ); // Go North to get above the DCDC1 $$terminal([ 231.5, 37.0 ] ); $$terminal([ 201.0, 37.0 ] ); // Go West to the start of the DCDC1 Output Fill $$terminal([ 200.5, 36.5 ] ); $$terminal([ 200.5, 35.5 ] ); // Go South to get below the DCDC1 Output Fill $$terminal([ 200.0, 35.0 ] ); $$terminal([ 189.2, 35.0 ] ); // Go West below the DCDC1 Output Fill $$terminal([ 188.7, 35.5 ] ); $$terminal([ 188.7, 36.5 ] ); // Go North to get back to our full vertical width $$terminal([ 188.2, 37.0 ] ); $$terminal([ 79.5, 37.0 ] ); // Go West to where we can start North $$terminal([ 79.0, 37.5 ] ); $$terminal([ 79.0, 142.5 ] ); // Go North up to were we can get some more width $$terminal([ 79.5, 143.0 ] ); $$terminal([ 85.5, 143.0 ] ); // Go East to pick up more width but do not crowed the FPGA $$terminal([ 86.0, 143.5 ] ); $$terminal([ 86.0, 177.5 ] ); // Go North to get above the FPGA, i.e. above the Bank #9 1V8 Fill $$terminal([ 86.5, 178.0 ] ); $$terminal([ 148.5, 178.0 ] ); // Go East to pick up a lot of width $$terminal([ 149.0, 178.5 ] ); $$terminal([ 149.0, 190.0 ] ); // Go North just under the feed to DCDC4 $$terminal([ 149.5, 190.5 ] ); $$terminal([ 153.5, 190.5 ] ); // Go East $$terminal([ 154.0, 191.0 ] ); $$terminal([ 154.0, 205.0 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_2" 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: BULK_5V up to 4 Amps // // Fill Layer: Signal_12 // // Location: West side and perimeter of North and South sides // // Resolution: Medium // $$initial([ 154.0, 205.0], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 153.5, 205.5 ] ); $$terminal([ 103.5, 205.5 ] ); // Go West across the top over to DCDC5 $$terminal([ 103.0, 206.0 ] ); $$terminal([ 103.0, 209.0 ] ); // Go North to feed DCDC5 via R1821 $$terminal([ 102.5, 209.5 ] ); $$terminal([ 95.5, 209.5 ] ); // Go West across the top of R1821 $$terminal([ 95.0, 209.0 ] ); $$terminal([ 95.0, 206.0 ] ); // Go South after the bump up to feed DCDC5 $$terminal([ 94.5, 205.5 ] ); $$terminal([ 34.5, 205.5 ] ); // Go West across the top over to DCDC6 $$terminal([ 34.0, 206.0 ] ); $$terminal([ 34.0, 206.0 ] ); // Go North to feed DCDC6 via R1851 $$terminal([ 33.5, 206.5 ] ); $$terminal([ 26.7, 206.5 ] ); // Go West across the top of R1851 $$terminal([ 26.2, 206.0 ] ); $$terminal([ 26.2, 171.5 ] ); // Go South down to just under the USB Phy chip U1051 $$terminal([ 26.7, 171.0 ] ); $$terminal([ 51.5, 171.0 ] ); // Go East to avoid the Main Cable HV $$terminal([ 52.0, 170.5 ] ); $$terminal([ 52.0, 145.5 ] ); // Go South down to under the RS-485 XCVR $$terminal([ 51.5, 145.0 ] ); $$terminal([ 40.5, 145.0 ] ); // Go West but keep out of the Main Cable stuff $$terminal([ 40.0, 144.5 ] ); $$terminal([ 40.0, 99.5 ] ); // Go South below the C1653 terminals $$terminal([ 39.5, 99.0 ] ); $$terminal([ 33.0, 99.0 ] ); // Go West but stay East of DCDC20 $$terminal([ 28.0, 94.0 ] ); // Go SW at an angle down to were we can start the run South $$terminal([ 28.0, 76.5 ] ); // Go South to below DCDC20 input section $$terminal([ 24.0, 72.5 ] ); // Go 45 deg SW to start run below DCDC20 input section $$terminal([ 2.0, 72.5 ] ); // Go West to pickup the DCDC20 Output Terms $$terminal([ 1.5, 72.0 ] ); $$terminal([ 1.5, 33.0 ] ); // Go South (sub 0.5 mm for miter) $$terminal([ 19.5, 15.0 ] ); // Go South-East at 45 deg to above Barnacle Connector $$terminal([ 67.5, 15.0 ] ); // Go East across the top of the Barnacle Connector $$terminal([ 68.0, 14.5 ] ); $$terminal([ 68.0, 3.5 ] ); // Go South down the East edge of the Barnacle Connector $$terminal([ 68.5, 3.0 ] ); $$terminal([ 112.0, 3.0 ] ); // Go East to where we need to start around the Mounting Screw $$terminal([ 112.5, 3.5 ] ); $$terminal([ 112.5, 10.5 ] ); // Go North to get above the Mounting Screw $$terminal([ 113.0, 11.0 ] ); $$terminal([ 122.0, 11.0 ] ); // Go East above the Mounting Screw to its East Side $$terminal([ 122.5, 10.5 ] ); $$terminal([ 122.5, 3.5 ] ); // Go South back up to our normal run line - now past the Screw $$terminal([ 123.0, 3.0 ] ); $$terminal([ 221.5, 3.0 ] ); // Go East past the SFPs and the BlackCat power feed $$terminal([ 222.0, 3.5 ] ); $$terminal([ 222.0, 12.5 ] ); // Go North to avoid the mounting screw hole $$terminal([ 222.5, 13.0 ] ); $$terminal([ 231.5, 13.0 ] ); // Go East to Brd edge to pick up DCDC1 $$terminal([ 232.0, 13.5 ] ); $$terminal([ 232.0, 36.5 ] ); // Go North to get above the DCDC1 $$terminal([ 231.5, 37.0 ] ); $$terminal([ 201.0, 37.0 ] ); // Go West to the start of the DCDC1 Output Fill $$terminal([ 200.5, 36.5 ] ); $$terminal([ 200.5, 35.5 ] ); // Go South to get below the DCDC1 Output Fill $$terminal([ 200.0, 35.0 ] ); $$terminal([ 189.2, 35.0 ] ); // Go West below the DCDC1 Output Fill $$terminal([ 188.7, 35.5 ] ); $$terminal([ 188.7, 36.5 ] ); // Go North to get back to our full vertical width $$terminal([ 188.2, 37.0 ] ); $$terminal([ 79.5, 37.0 ] ); // Go West to where we can start North $$terminal([ 79.0, 37.5 ] ); $$terminal([ 79.0, 142.5 ] ); // Go North up to were we can get some more width $$terminal([ 79.5, 143.0 ] ); $$terminal([ 85.5, 143.0 ] ); // Go East to pick up more width but do not crowed the FPGA $$terminal([ 86.0, 143.5 ] ); $$terminal([ 86.0, 177.5 ] ); // Go North to get above the FPGA, i.e. above the Bank #9 1V8 Fill $$terminal([ 86.5, 178.0 ] ); $$terminal([ 148.5, 178.0 ] ); // Go East to pick up a lot of width $$terminal([ 149.0, 178.5 ] ); $$terminal([ 149.0, 190.0 ] ); // Go North just under the feed to DCDC4 $$terminal([ 149.5, 190.5 ] ); $$terminal([ 153.5, 190.5 ] ); // Go East $$terminal([ 154.0, 191.0 ] ); $$terminal([ 154.0, 205.0 ] ); // Go North - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // FPGA Area Fills on Signal Layer 3 <--- // ======-----------------------------=== // // // // Original Rev. 29-July-2024 // Current Rev. 25-Nov-2024 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_12 in this file are: // // Analog_2V5 to FPGA PLLs and PNVM and // to XCVR Plls and Clock Buffers // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_3 fill file is repeated // on both the layers: DIELECTRIC_3 and SHAPE_EDIT. // See the bottom section of this file. // // - As of 31-July-2024 there is 1 shape defined in this file. // // // Net: Analog_2V5 about ?? mA // // Fill Layer: Signal_3 // // Location: Center of FPGA and up to L104 // // Resolution: High // $$initial([ 120.5, 183.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 120.3, 183.5 ] ); $$terminal([ 112.7, 183.5 ] ); // Go West across the top of L104 $$terminal([ 112.5, 183.3 ] ); $$terminal([ 112.5, 177.0 ] ); // Go South to the bottom of L104 (Y minus 0.2 for miter) $$terminal([ 109.4, 163.0 ] ); // Go South-West to the top of the BGA // // Now start Down into the BGA $$terminal([ 109.4, 149.6 ] ); // Go part way South $$terminal([ 109.6, 149.4 ] ); $$terminal([ 110.2, 149.4 ] ); // Jog a little East $$terminal([ 110.4, 149.2 ] ); $$terminal([ 110.4, 138.6 ] ); // Go South the rest of the way $$terminal([ 110.6, 138.4 ] ); $$terminal([ 122.4, 138.4 ] ); // Go East across the bottom $$terminal([ 122.6, 138.6 ] ); $$terminal([ 122.6, 158.4 ] ); // Go North up to where we need to jog back West $$terminal([ 122.4, 158.6 ] ); $$terminal([ 119.8, 158.6 ] ); // Go West to clean some Diff signals that I may want on this layer $$terminal([ 119.6, 158.8 ] ); $$terminal([ 119.6, 167.0 ] ); // Go North to the top of the FPGA (Y plus 0.2 for miter) // // Now we are back out of the BGA $$terminal([ 120.5, 177.0 ] ); // Go North-West back up to L104 $$terminal([ 120.5, 183.3 ] ); // Go North and back Home $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_3" 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: Analog_2V5 about ?? mA // // Fill Layer: Signal_3 // // Location: Center of FPGA and up to L104 // // Resolution: High // $$initial([ 120.5, 183.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 120.3, 183.5 ] ); $$terminal([ 112.7, 183.5 ] ); // Go West across the top of L104 $$terminal([ 112.5, 183.3 ] ); $$terminal([ 112.5, 177.0 ] ); // Go South to the bottom of L104 (Y minus 0.2 for miter) $$terminal([ 109.4, 163.0 ] ); // Go South-West to the top of the BGA // // Now start Down into the BGA $$terminal([ 109.4, 149.6 ] ); // Go part way South $$terminal([ 109.6, 149.4 ] ); $$terminal([ 110.2, 149.4 ] ); // Jog a little East $$terminal([ 110.4, 149.2 ] ); $$terminal([ 110.4, 138.6 ] ); // Go South the rest of the way $$terminal([ 110.6, 138.4 ] ); $$terminal([ 122.4, 138.4 ] ); // Go East across the bottom $$terminal([ 122.6, 138.6 ] ); $$terminal([ 122.6, 158.4 ] ); // Go North up to where we need to jog back West $$terminal([ 122.4, 158.6 ] ); $$terminal([ 119.8, 158.6 ] ); // Go West to clean some Diff signals that I may want on this layer $$terminal([ 119.6, 158.8 ] ); $$terminal([ 119.6, 167.0 ] ); // Go North to the top of the FPGA (Y plus 0.2 for miter) // // Now we are back out of the BGA $$terminal([ 120.5, 177.0 ] ); // Go North-West back up to L104 $$terminal([ 120.5, 183.3 ] ); // Go North and back Home $$path( "DIELECTRIC_3", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // FPGA Area Fills on Signal Layer 11 <--- // ======---------------------------==== // // // // Original Rev. 28-July-2024 // Current Rev. 26-Dec-2024 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_11 are: // // BULK_1V05 DCDC2 to L101 and L102 about 2200+ mA // XCVR_1V05 XCVR Lanes main supply about ?? mA // BULK_3V3 FPGA I/O Bank Supply about ?? mA // Digital_2V5 FPGA Bank #9 AUX Supply about ?? mA // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_11 fill file is repeated // on both the layers: DIELECTRIC_1 and SHAPE_EDIT. // See the bottom section of this file. // // - In the tight section under the FPGA I'm using a 0.20 mm // air gap between Fills. // // - As of 26-Nov-2024 there are 4 shapes defined in this file // that make 4 Fills on the PCB. // // // Net: BULK_1V05 about 2200+ mA // // Fill Layer: Signal_11 20 mm wide // // Location: DCDC2 Output, L101 Feed, L102 Feed // // Resolution: Medium // $$initial([ 143.0, 119.1], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 142.8, 119.3 ] ); $$terminal([ 132.2, 119.3 ] ); // Go West under L102 $$terminal([ 132.0, 119.1 ] ); $$terminal([ 132.0, 73.2 ] ); // Go South to where the fill gets wider $$terminal([ 131.8, 73.0 ] ); $$terminal([ 125.2, 73.0 ] ); // Go West as far as there is space available $$terminal([ 125.0, 72.8 ] ); $$terminal([ 125.0, 63.2 ] ); // Go South to where fill goes under L101 $$terminal([ 124.8, 63.0 ] ); $$terminal([ 102.2, 63.0 ] ); // Go West under filter L101 $$terminal([ 102.0, 62.8 ] ); $$terminal([ 102.0, 39.2 ] ); // Go South down to pick up the DCDC2 output $$terminal([ 102.2, 39.0 ] ); $$terminal([ 142.8, 39.0 ] ); // Go East through DCDC2 to where can run North $$terminal([ 143.0, 39.2 ] ); $$terminal([ 143.0, 119.1 ] ); // Go North back up to the starting point $$path( "SHAPE_EDIT", 0.0 ); // // Net: XCVR_1V05 about ?? mA // // Fill Layer: Signal_11 16 mm wide // // Location: East edge under FPGA and East from there // // Resolution: High // $$initial([ 143.0, 160.4], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 142.8, 160.6 ] ); $$terminal([ 123.6, 160.6 ] ); // Go West part way across the Top $$terminal([ 123.4, 160.4 ] ); $$terminal([ 123.4, 152.7 ] ); // Go Down the West Edge until the bump out $$terminal([ 123.2, 152.5 ] ); $$terminal([ 122.3, 152.5 ] ); // Jog out West $$terminal([ 122.1, 152.3 ] ); $$terminal([ 122.1, 139.3 ] ); // Go Down past the bump out $$terminal([ 122.3, 139.1 ] ); $$terminal([ 123.0, 139.1 ] ); // Jog back East $$terminal([ 123.2, 138.9 ] ); $$terminal([ 123.2, 131.6 ] ); // Go Down to near the South end $$terminal([ 123.4, 131.4 ] ); $$terminal([ 126.2, 131.4 ] ); // Jog back East $$terminal([ 126.4, 131.2 ] ); $$terminal([ 126.4, 128.6 ] ); // Go Down to clear the bottom pin $$terminal([ 126.6, 128.4 ] ); $$terminal([ 130.3, 128.4 ] ); // Jog back East out of the BGA pins $$terminal([ 130.5, 128.2 ] ); $$terminal([ 130.5, 121.9 ] ); // Go Down to pick up the L102 Power Feed $$terminal([ 130.7, 121.7 ] ); $$terminal([ 142.8, 121.7 ] ); // Go the rest of the way back East $$terminal([ 143.0, 121.9 ] ); $$terminal([ 143.0, 160.4 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: Bulk_3V3 about ?? mA FPGA Banks: 1, 2, 3, 5, 7 // // Fill Layer: Signal_11 ?? mm wide // // Location: Under the North-West part of FPGA and North from there // // Resolution: High // $$initial([ 106.6, 164.8], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 106.4, 165.0 ] ); $$terminal([ 94.2, 165.0 ] ); // Go West across the Top $$terminal([ 94.0, 164.8 ] ); $$terminal([ 94.0, 140.3 ] ); // Go Down the West Edge. $$terminal([ 94.2, 140.1 ] ); $$terminal([ 101.7, 140.1 ] ); // Go East across the bottom. $$terminal([ 101.9, 140.3 ] ); $$terminal([ 101.9, 141.9 ] ); // Go North part way up past the Core Sypply $$terminal([ 102.1, 142.1 ] ); $$terminal([ 111.7, 142.1 ] ); // Go East across the bottom. $$terminal([ 111.9, 142.3 ] ); $$terminal([ 111.9, 148.9 ] ); // Go North part way up past the Core supply $$terminal([ 112.1, 149.1 ] ); $$terminal([ 114.7, 149.1 ] ); // Go East to pick up a few pins $$terminal([ 114.9, 149.3 ] ); $$terminal([ 114.9, 152.3 ] ); // Go North $$terminal([ 114.7, 152.5 ] ); $$terminal([ 113.1, 152.5 ] ); // Jog back West to clear some 1V8 pins $$terminal([ 112.9, 152.7 ] ); $$terminal([ 112.9, 154.4 ] ); // Go North $$terminal([ 112.7, 154.6 ] ); $$terminal([ 111.6, 154.6 ] ); // Jog back West to clear some more 1V8 pins $$terminal([ 111.4, 154.8 ] ); $$terminal([ 111.4, 156.4 ] ); // Go North $$terminal([ 111.2, 156.6 ] ); $$terminal([ 107.8, 156.6 ] ); // Jog back West to clear some more 1V8 pins $$terminal([ 107.6, 156.8 ] ); $$terminal([ 107.6, 159.4 ] ); // Go North $$terminal([ 107.4, 159.6 ] ); $$terminal([ 106.8, 159.6 ] ); // Final Jog back West $$terminal([ 106.6, 159.8 ] ); $$terminal([ 106.6, 164.8 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: Digital_2V5 about ?? mA // // Fill Layer: Signal_11 10 mm wide // // Location: Under the upper central part of FPGA and North to L105 // // Resolution: High // $$initial([ 111.5, 183.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 111.3, 183.5 ] ); $$terminal([ 103.7, 183.5 ] ); // Go West across the Top of L105 $$terminal([ 103.5, 183.3 ] ); $$terminal([ 103.5, 175.1 ] ); // Go South down the side of L105 ( Y minus 0.2 for miter) $$terminal([ 114.4, 163.7 ] ); // Go South-East to start of BGA // // Start down into the BGA $$terminal([ 114.4, 154.2 ] ); // Go Down the West Edge. $$terminal([ 114.6, 154.0 ] ); $$terminal([ 114.9, 154.0 ] ); // Go East just a little to clear the 3V3 Fill $$terminal([ 115.1, 153.8 ] ); $$terminal([ 115.1, 149.3 ] ); // Go Down the West Edge the rest of the way $$terminal([ 115.3, 149.1 ] ); $$terminal([ 121.7, 149.1 ] ); // Go back East across the bottom. $$terminal([ 121.9, 149.3 ] ); $$terminal([ 121.9, 165.9 ] ); // Go North up the East edge of the BGA (Y plus 0.2 for miter) // // Now back out of the BGA $$terminal([ 111.5, 176.9 ] ); // Go North-West over to L105 $$terminal([ 111.5, 183.3 ] ); // Go North up the East edge of L105 - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_1", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: BULK_1V05 about 2200+ mA // // Fill Layer: Signal_11 20 mm wide // // Location: DCDC2 Output, L101 Feed, L102 Feed // // Resolution: Medium // $$initial([ 143.0, 119.1], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 142.8, 119.3 ] ); $$terminal([ 132.2, 119.3 ] ); // Go West under L102 $$terminal([ 132.0, 119.1 ] ); $$terminal([ 132.0, 73.2 ] ); // Go South to where the fill gets wider $$terminal([ 131.8, 73.0 ] ); $$terminal([ 125.2, 73.0 ] ); // Go West as far as there is space available $$terminal([ 125.0, 72.8 ] ); $$terminal([ 125.0, 63.2 ] ); // Go South to where fill goes under L101 $$terminal([ 124.8, 63.0 ] ); $$terminal([ 102.2, 63.0 ] ); // Go West under filter L101 $$terminal([ 102.0, 62.8 ] ); $$terminal([ 102.0, 39.2 ] ); // Go South down to pick up the DCDC2 output $$terminal([ 102.2, 39.0 ] ); $$terminal([ 142.8, 39.0 ] ); // Go East through DCDC2 to where can run North $$terminal([ 143.0, 39.2 ] ); $$terminal([ 143.0, 119.1 ] ); // Go North back up to the starting point $$path( "DIELECTRIC_1", 0.0 ); // // Net: XCVR_1V05 about ?? mA // // Fill Layer: Signal_11 16 mm wide // // Location: East edge under FPGA and East from there // // Resolution: High // $$initial([ 143.0, 160.4], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 142.8, 160.6 ] ); $$terminal([ 123.6, 160.6 ] ); // Go West part way across the Top $$terminal([ 123.4, 160.4 ] ); $$terminal([ 123.4, 152.7 ] ); // Go Down the West Edge until the bump out $$terminal([ 123.2, 152.5 ] ); $$terminal([ 122.3, 152.5 ] ); // Jog out West $$terminal([ 122.1, 152.3 ] ); $$terminal([ 122.1, 139.3 ] ); // Go Down past the bump out $$terminal([ 122.3, 139.1 ] ); $$terminal([ 123.0, 139.1 ] ); // Jog back East $$terminal([ 123.2, 138.9 ] ); $$terminal([ 123.2, 131.6 ] ); // Go Down to near the South end $$terminal([ 123.4, 131.4 ] ); $$terminal([ 126.2, 131.4 ] ); // Jog back East $$terminal([ 126.4, 131.2 ] ); $$terminal([ 126.4, 128.6 ] ); // Go Down to clear the bottom pin $$terminal([ 126.6, 128.4 ] ); $$terminal([ 130.3, 128.4 ] ); // Jog back East out of the BGA pins $$terminal([ 130.5, 128.2 ] ); $$terminal([ 130.5, 121.9 ] ); // Go Down to pick up the L102 Power Feed $$terminal([ 130.7, 121.7 ] ); $$terminal([ 142.8, 121.7 ] ); // Go the rest of the way back East $$terminal([ 143.0, 121.9 ] ); $$terminal([ 143.0, 160.4 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // Net: Bulk_3V3 about ?? mA FPGA Banks: 1, 2, 3, 5, 7 // // Fill Layer: Signal_11 ?? mm wide // // Location: Under the North-West part of FPGA and North from there // // Resolution: High // $$initial([ 106.6, 164.8], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 106.4, 165.0 ] ); $$terminal([ 94.2, 165.0 ] ); // Go West across the Top $$terminal([ 94.0, 164.8 ] ); $$terminal([ 94.0, 140.3 ] ); // Go Down the West Edge. $$terminal([ 94.2, 140.1 ] ); $$terminal([ 101.7, 140.1 ] ); // Go East across the bottom. $$terminal([ 101.9, 140.3 ] ); $$terminal([ 101.9, 141.9 ] ); // Go North part way up past the Core Sypply $$terminal([ 102.1, 142.1 ] ); $$terminal([ 111.7, 142.1 ] ); // Go East across the bottom. $$terminal([ 111.9, 142.3 ] ); $$terminal([ 111.9, 148.9 ] ); // Go North part way up past the Core supply $$terminal([ 112.1, 149.1 ] ); $$terminal([ 114.7, 149.1 ] ); // Go East to pick up a few pins $$terminal([ 114.9, 149.3 ] ); $$terminal([ 114.9, 152.3 ] ); // Go North $$terminal([ 114.7, 152.5 ] ); $$terminal([ 113.1, 152.5 ] ); // Jog back West to clear some 1V8 pins $$terminal([ 112.9, 152.7 ] ); $$terminal([ 112.9, 154.4 ] ); // Go North $$terminal([ 112.7, 154.6 ] ); $$terminal([ 111.6, 154.6 ] ); // Jog back West to clear some more 1V8 pins $$terminal([ 111.4, 154.8 ] ); $$terminal([ 111.4, 156.4 ] ); // Go North $$terminal([ 111.2, 156.6 ] ); $$terminal([ 107.8, 156.6 ] ); // Jog back West to clear some more 1V8 pins $$terminal([ 107.6, 156.8 ] ); $$terminal([ 107.6, 159.4 ] ); // Go North $$terminal([ 107.4, 159.6 ] ); $$terminal([ 106.8, 159.6 ] ); // Final Jog back West $$terminal([ 106.6, 159.8 ] ); $$terminal([ 106.6, 164.8 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // Net: Digital_2V5 about ?? mA // // Fill Layer: Signal_11 10 mm wide // // Location: Under the upper central part of FPGA and North to L105 // // Resolution: High // $$initial([ 111.5, 183.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 111.3, 183.5 ] ); $$terminal([ 103.7, 183.5 ] ); // Go West across the Top of L105 $$terminal([ 103.5, 183.3 ] ); $$terminal([ 103.5, 175.1 ] ); // Go South down the side of L105 ( Y minus 0.2 for miter) $$terminal([ 114.4, 163.7 ] ); // Go South-East to start of BGA // // Start down into the BGA $$terminal([ 114.4, 154.2 ] ); // Go Down the West Edge. $$terminal([ 114.6, 154.0 ] ); $$terminal([ 114.9, 154.0 ] ); // Go East just a little to clear the 3V3 Fill $$terminal([ 115.1, 153.8 ] ); $$terminal([ 115.1, 149.3 ] ); // Go Down the West Edge the rest of the way $$terminal([ 115.3, 149.1 ] ); $$terminal([ 121.7, 149.1 ] ); // Go back East across the bottom. $$terminal([ 121.9, 149.3 ] ); $$terminal([ 121.9, 165.9 ] ); // Go North up the East edge of the BGA (Y plus 0.2 for miter) // // Now back out of the BGA $$terminal([ 111.5, 176.9 ] ); // Go North-West over to L105 $$terminal([ 111.5, 183.3 ] ); // Go North up the East edge of L105 - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // FPGA CORE Supply Area Fills on Signal Layer 11 <--- // ============-----------------------------------==== // // // // Original Rev. 28-July-2024 // Current Rev. 27-Nov-2024 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_11 are: // // CORE_1V05 FPGA Core Supply about 2200 mA // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_11 fill file is repeated // on both the layers: DIELECTRIC_1 and SHAPE_EDIT. // See the bottom section of this file. // // - In the tight section under the FPGA I'm using a 0.20 mm // air gap between Fills. // // - As of 26-Nov-2024 there are 3 shapes defined in this file. // // // Net: CORE_1V05 about 2200 mA // // Fill Layer: Signal_11 mm wide // // Location: Just under the central part of the FPGA // // Resolution: High // $$initial([ 121.9, 148.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 121.7, 148.9 ] ); $$terminal([ 112.3, 148.9 ] ); // Go West across the Top $$terminal([ 112.1, 148.7 ] ); $$terminal([ 112.1, 142.1 ] ); // Go part way Down the West Edge. $$terminal([ 111.9, 141.9 ] ); $$terminal([ 102.6, 141.9 ] ); // Jog to the West now just under the 3V3 Fill $$terminal([ 102.4, 141.7 ] ); $$terminal([ 102.4, 127.2 ] ); // Go South the rest of the way out of the BGA $$terminal([ 102.2, 127.0 ] ); $$terminal([ 95.7, 127.0 ] ); // Go West to a rational point to travel South $$terminal([ 95.5, 126.8 ] ); $$terminal([ 95.5, 114.7 ] ); // Go South down to just above the DDR4 chips $$terminal([ 95.7, 114.5 ] ); $$terminal([ 124.3, 114.5 ] ); // Go East just above the DDR4 chips $$terminal([ 124.5, 114.7 ] ); $$terminal([ 124.5, 126.8 ] ); // Go North up to just under the FPGA BGA $$terminal([ 124.3, 127.0 ] ); $$terminal([ 123.0, 127.0 ] ); // Go West a little to the point to run North $$terminal([ 122.8, 127.2 ] ); $$terminal([ 122.8, 138.7 ] ); // Go North part way up the East side $$terminal([ 122.6, 138.9 ] ); $$terminal([ 122.1, 138.9 ] ); // Go back East across the bottom. $$terminal([ 121.9, 139.1 ] ); $$terminal([ 121.9, 148.7 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: CORE_1V05 about 2200 mA // // Fill Layer: Signal_11 mm wide // // Location: Just under the DDR4 chips // // Resolution: Very_High // $$initial([ 124.5, 114.8], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 124.3, 115.0 ] ); $$terminal([ 95.7, 115.0 ] ); // Go West just above the DDR4 chips $$terminal([ 95.5, 114.8 ] ); $$terminal([ 95.5, 89.2 ] ); // Go South down past the DDR4 chips $$terminal([ 95.7, 89.0 ] ); $$terminal([ 124.3, 89.0 ] ); // Go East just under the DDR4 chips $$terminal([ 124.5, 89.2 ] ); $$terminal([ 124.5, 114.8 ] ); // Go North up the East edge of DDR4 - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: CORE_1V05 about 2200 mA // // Fill Layer: Signal_11 mm wide // // Location: From just below the DDR4 Array down South to L101 // // Resolution: High // $$initial([ 124.5, 89.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 124.3, 89.5 ] ); $$terminal([ 95.7, 89.5 ] ); // Go West just below the DDR4 array $$terminal([ 95.5, 89.3 ] ); $$terminal([ 95.5, 73.2 ] ); // Go South to below the CA Bus Terminators $$terminal([ 95.7, 73.0 ] ); $$terminal([ 102.0, 73.0 ] ); // Jog East to get closer to L101 $$terminal([ 102.2, 72.8 ] ); $$terminal([ 102.2, 65.2 ] ); // Go South to below L101 $$terminal([ 102.4, 65.0 ] ); $$terminal([ 117.6, 65.0 ] ); // Go East under L101 $$terminal([ 117.8, 65.2 ] ); $$terminal([ 117.8, 72.8 ] ); // Go North up the East edge of L101 $$terminal([ 118.0, 73.0 ] ); $$terminal([ 124.3, 73.0 ] ); // Jog East to get back to full width $$terminal([ 124.5, 73.2 ] ); $$terminal([ 124.5, 89.3 ] ); // Go North up the East edge - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_1", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: CORE_1V05 about 2200 mA // // Fill Layer: Signal_11 mm wide // // Location: Just under the central part of the FPGA // // Resolution: High // $$initial([ 121.9, 148.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 121.7, 148.9 ] ); $$terminal([ 112.3, 148.9 ] ); // Go West across the Top $$terminal([ 112.1, 148.7 ] ); $$terminal([ 112.1, 142.1 ] ); // Go part way Down the West Edge. $$terminal([ 111.9, 141.9 ] ); $$terminal([ 102.6, 141.9 ] ); // Jog to the West now just under the 3V3 Fill $$terminal([ 102.4, 141.7 ] ); $$terminal([ 102.4, 127.2 ] ); // Go South the rest of the way out of the BGA $$terminal([ 102.2, 127.0 ] ); $$terminal([ 95.7, 127.0 ] ); // Go West to a rational point to travel South $$terminal([ 95.5, 126.8 ] ); $$terminal([ 95.5, 114.7 ] ); // Go South down to just above the DDR4 chips $$terminal([ 95.7, 114.5 ] ); $$terminal([ 124.3, 114.5 ] ); // Go East just above the DDR4 chips $$terminal([ 124.5, 114.7 ] ); $$terminal([ 124.5, 126.8 ] ); // Go North up to just under the FPGA BGA $$terminal([ 124.3, 127.0 ] ); $$terminal([ 123.0, 127.0 ] ); // Go West a little to the point to run North $$terminal([ 122.8, 127.2 ] ); $$terminal([ 122.8, 138.7 ] ); // Go North part way up the East side $$terminal([ 122.6, 138.9 ] ); $$terminal([ 122.1, 138.9 ] ); // Go back East across the bottom. $$terminal([ 121.9, 139.1 ] ); $$terminal([ 121.9, 148.7 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // Net: CORE_1V05 about 2200 mA // // Fill Layer: Signal_11 mm wide // // Location: Just under the DDR4 chips // // Resolution: Very_High // $$initial([ 124.5, 114.8], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 124.3, 115.0 ] ); $$terminal([ 95.7, 115.0 ] ); // Go West just above the DDR4 chips $$terminal([ 95.5, 114.8 ] ); $$terminal([ 95.5, 89.2 ] ); // Go South down past the DDR4 chips $$terminal([ 95.7, 89.0 ] ); $$terminal([ 124.3, 89.0 ] ); // Go East just under the DDR4 chips $$terminal([ 124.5, 89.2 ] ); $$terminal([ 124.5, 114.8 ] ); // Go North up the East edge of DDR4 - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // Net: CORE_1V05 about 2200 mA // // Fill Layer: Signal_11 mm wide // // Location: From just below the DDR4 Array down South to L101 // // Resolution: High // $$initial([ 124.5, 89.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 124.3, 89.5 ] ); $$terminal([ 95.7, 89.5 ] ); // Go West just below the DDR4 array $$terminal([ 95.5, 89.3 ] ); $$terminal([ 95.5, 73.2 ] ); // Go South to below the CA Bus Terminators $$terminal([ 95.7, 73.0 ] ); $$terminal([ 102.0, 73.0 ] ); // Jog East to get closer to L101 $$terminal([ 102.2, 72.8 ] ); $$terminal([ 102.2, 65.2 ] ); // Go South to below L101 $$terminal([ 102.4, 65.0 ] ); $$terminal([ 117.6, 65.0 ] ); // Go East under L101 $$terminal([ 117.8, 65.2 ] ); $$terminal([ 117.8, 72.8 ] ); // Go North up the East edge of L101 $$terminal([ 118.0, 73.0 ] ); $$terminal([ 124.3, 73.0 ] ); // Jog East to get back to full width $$terminal([ 124.5, 73.2 ] ); $$terminal([ 124.5, 89.3 ] ); // Go North up the East edge - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // FPGA Area Fills on Signal Layer 12 <--- // ======----------------------------==== // // // // Original Rev. 29-July-2024 // Current Rev. 28-Nov-2024 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_12 in this file are: // // FPGA_1V8 to FPGA I/O Bank 9 and FPGA Prog & HSIO Aux // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_12 fill file is repeated // on both the layers: DIELECTRIC_2 and SHAPE_EDIT. // See the bottom section of this file. // // - As of 27-Nov-2024 there is 1 shape defined in this file. // // // Net: FPGA_1V8 about ?? mA for I/O Bank #9 // // Fill Layer: Signal_12 // // Location: Top half of FPGA in the center // // Resolution: Medium // $$initial([ 150.0, 177.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 149.8, 177.5 ] ); $$terminal([ 125.2, 177.5 ] ); // Go West pver L103 and get some width $$terminal([ 125.0, 177.3 ] ); $$terminal([ 125.0, 173.2 ] ); // Go South $$terminal([ 124.8, 173.0 ] ); $$terminal([ 107.3, 173.0 ] ); // G0 West to a point where we can start into the BGA $$terminal([ 107.1, 172.8 ] ); // // Start into BGA $$terminal([ 107.1, 156.6 ] ); // Go a little South $$terminal([ 107.3, 156.4 ] ); $$terminal([ 110.9, 156.4 ] ); // Jog East $$terminal([ 111.1, 156.2 ] ); $$terminal([ 111.1, 138.3 ] ); // Go the whole way South $$terminal([ 111.3, 138.1 ] ); $$terminal([ 114.7, 138.1 ] ); // Jog East $$terminal([ 114.9, 138.3 ] ); $$terminal([ 114.9, 139.4 ] ); // Go a little North $$terminal([ 115.1, 139.6 ] ); $$terminal([ 120.4, 139.6 ] ); // Jog East $$terminal([ 120.6, 139.8 ] ); $$terminal([ 120.6, 150.2 ] ); // Go a long way North $$terminal([ 120.8, 150.4 ] ); $$terminal([ 121.4, 150.4 ] ); // Jog East $$terminal([ 121.6, 150.6 ] ); $$terminal([ 121.6, 153.3 ] ); // Go a little North $$terminal([ 121.8, 153.5 ] ); $$terminal([ 122.4, 153.5 ] ); // Jog East $$terminal([ 122.6, 153.7 ] ); $$terminal([ 122.6, 157.3 ] ); // Go a little North $$terminal([ 122.8, 157.5 ] ); $$terminal([ 123.3, 157.5 ] ); // Jog East $$terminal([ 123.5, 157.7 ] ); $$terminal([ 123.5, 162.8 ] ); // Go North to get out of BGA $$terminal([ 123.7, 163.0 ] ); // // Now back out of the BGA $$terminal([ 139.8, 163.0 ] ); // Go East just part way $$terminal([ 140.0, 163.2 ] ); $$terminal([ 140.0, 169.8 ] ); // Go North to make space for another fill $$terminal([ 140.2, 170.0 ] ); $$terminal([ 149.8, 170.0 ] ); // Go East to run under L103 $$terminal([ 150.0, 170.2 ] ); $$terminal([ 150.0, 177.3 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_2" 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: FPGA_1V8 about ?? mA for I/O Bank #9 // // Fill Layer: Signal_12 // // Location: Top half of FPGA in the center // // Resolution: Medium // $$initial([ 150.0, 177.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 149.8, 177.5 ] ); $$terminal([ 125.2, 177.5 ] ); // Go West pver L103 and get some width $$terminal([ 125.0, 177.3 ] ); $$terminal([ 125.0, 173.2 ] ); // Go South $$terminal([ 124.8, 173.0 ] ); $$terminal([ 107.3, 173.0 ] ); // G0 West to a point where we can start into the BGA $$terminal([ 107.1, 172.8 ] ); // // Start into BGA $$terminal([ 107.1, 156.6 ] ); // Go a little South $$terminal([ 107.3, 156.4 ] ); $$terminal([ 110.9, 156.4 ] ); // Jog East $$terminal([ 111.1, 156.2 ] ); $$terminal([ 111.1, 138.3 ] ); // Go the whole way South $$terminal([ 111.3, 138.1 ] ); $$terminal([ 114.7, 138.1 ] ); // Jog East $$terminal([ 114.9, 138.3 ] ); $$terminal([ 114.9, 139.4 ] ); // Go a little North $$terminal([ 115.1, 139.6 ] ); $$terminal([ 120.4, 139.6 ] ); // Jog East $$terminal([ 120.6, 139.8 ] ); $$terminal([ 120.6, 150.2 ] ); // Go a long way North $$terminal([ 120.8, 150.4 ] ); $$terminal([ 121.4, 150.4 ] ); // Jog East $$terminal([ 121.6, 150.6 ] ); $$terminal([ 121.6, 153.3 ] ); // Go a little North $$terminal([ 121.8, 153.5 ] ); $$terminal([ 122.4, 153.5 ] ); // Jog East $$terminal([ 122.6, 153.7 ] ); $$terminal([ 122.6, 157.3 ] ); // Go a little North $$terminal([ 122.8, 157.5 ] ); $$terminal([ 123.3, 157.5 ] ); // Jog East $$terminal([ 123.5, 157.7 ] ); $$terminal([ 123.5, 162.8 ] ); // Go North to get out of BGA $$terminal([ 123.7, 163.0 ] ); // // Now back out of the BGA $$terminal([ 139.8, 163.0 ] ); // Go East just part way $$terminal([ 140.0, 163.2 ] ); $$terminal([ 140.0, 169.8 ] ); // Go North to make space for another fill $$terminal([ 140.2, 170.0 ] ); $$terminal([ 149.8, 170.0 ] ); // Go East to run under L103 $$terminal([ 150.0, 170.2 ] ); $$terminal([ 150.0, 177.3 ] ); // Go North - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // FPGA BULK_1V2 Area Fills on Signal Layer 12 <--- // ================----------------------------==== // // // // Original Rev. 29-July-2024 // Current Rev. 10-Jan-2025 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_12 in this file are: // // BULK_1V2 to FPGA I/O Banks 0 and 6 and DDR4 Memory Chips // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_12 fill file is repeated // on both the layers: DIELECTRIC_2 and SHAPE_EDIT. // See the bottom section of this file. // // - As of 26-Nov-2024 there are 5 shapes defined in this file. // // // Net: BULK_1V2 about ?? mA // // Fill Layer: Signal_12 // // Location: Under only Bank #6 and down to just above the CPU DDR4 chips // // Resolution: HIGH // $$initial([ 110.9, 141.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 110.7, 141.7 ] ); $$terminal([ 80.2, 141.7 ] ); // Go West across the Top of Bank #6 $$terminal([ 80.0, 141.5 ] ); $$terminal([ 80.0, 113.7 ] ); // Go South to just above the CPU DDR4 array $$terminal([ 80.2, 113.5 ] ); $$terminal([ 109.6, 113.5 ] ); // Go East across the top of the CPU DDR4 chips $$terminal([ 109.8, 113.7 ] ); $$terminal([ 109.8, 125.6 ] ); // North to the top of the center line $$terminal([ 109.6, 125.8 ] ); $$terminal([ 106.5, 125.8 ] ); // West to where we can go up into the BGA $$terminal([ 106.3, 126.0 ] ); $$terminal([ 106.3, 130.5 ] ); // North to start cut through Bank #8 Start Slit $$terminal([ 113.7, 137.9 ] ); // North-East to top of the slit End of Slit $$terminal([ 111.1, 137.9 ] ); // Slit is finish now Jog West $$terminal([ 110.9, 138.1 ] ); $$terminal([ 110.9, 141.5 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: BULK_1V2 about ?? mA // // Fill Layer: Signal_12 // // Location: Under only Bank #0 and down to just above the FPGA DDR4 chips // // Resolution: HIGH // $$initial([ 140.0, 139.4], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 139.8, 139.6 ] ); $$terminal([ 120.8, 139.6 ] ); // Go West to where we need to jog down $$terminal([ 120.7, 139.4 ] ); // Go South just a little to get below the FPGA_1V8 Fill $$terminal([ 115.3, 139.4 ] ); // Go West across the top of Bank #0 $$terminal([ 115.1, 139.2 ] ); $$terminal([ 115.1, 138.1 ] ); // Go South a little $$terminal([ 114.9, 137.9 ] ); $$terminal([ 114.1, 137.9 ] ); // Go West to start of slit Start Slit $$terminal([ 106.7, 130.5 ] ); // Run South-West through Bank #8 End of Slit $$terminal([ 106.7, 126.4 ] ); // South to get out of the BGA $$terminal([ 106.9, 126.2 ] ); $$terminal([ 110.0, 126.2 ] ); // East over to the Center Line $$terminal([ 110.2, 126.0 ] ); $$terminal([ 110.2, 113.7 ] ); // Go South down to the top of the FPGA DDR4 $$terminal([ 110.4, 113.5 ] ); $$terminal([ 139.8, 113.5 ] ); // Go East across the top of the FPGA DDR4 chips $$terminal([ 140.0, 113.7 ] ); $$terminal([ 140.0, 139.4 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: BULK_1V2 about ?? mA // // Fill Layer: Signal_12 // // Location: Under only the CPU DDR4 Chips // // Resolution: VERY_HIGH // $$initial([ 109.8, 113.8], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 109.6, 114.0 ] ); $$terminal([ 80.2, 114.0 ] ); // Go West across the Top of the CPU DDR4 chips $$terminal([ 80.0, 113.8 ] ); $$terminal([ 80.0, 87.9 ] ); // Go South the whole way to the bottom of DDR4 chips $$terminal([ 80.2, 87.7 ] ); $$terminal([ 109.6, 87.7 ] ); // Go East just below the CPU DDR4 chips $$terminal([ 109.8, 87.9 ] ); $$terminal([ 109.8, 113.8 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: BULK_1V2 about ?? mA // // Fill Layer: Signal_12 // // Location: Under only the FPGA DDR4 Chips // // Resolution: VERY_HIGH // $$initial([ 140.0, 113.8], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 139.8, 114.0 ] ); $$terminal([ 110.4, 114.0 ] ); // Go West across the Top of the FPGA DDR4 chips $$terminal([ 110.2, 113.8 ] ); $$terminal([ 110.2, 87.9 ] ); // Go South the whole way to the bottom of DDR4 chips $$terminal([ 110.4, 87.7 ] ); $$terminal([ 139.8, 87.7 ] ); // Go East just below the FPGA DDR4 chips $$terminal([ 140.0, 87.9 ] ); $$terminal([ 140.0, 113.8 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: BULK_1V2 about ?? mA // // Fill Layer: Signal_12 // // Location: Under both CA Bus Terminators and down to DCDC3 // // Resolution: HIGH // $$initial([ 140.0, 88.0], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 139.8, 88.2 ] ); $$terminal([ 110.4, 88.2 ] ); // Go West across the Top to the Slit $$terminal([ 110.2, 88.0 ] ); $$terminal([ 110.2, 85.2 ] ); // South to the bottom of the slit $$terminal([ 110.0, 85.0 ] ); $$terminal([ 110.0, 85.0 ] ); // West to the other side of the slit $$terminal([ 109.8, 85.2 ] ); $$terminal([ 109.8, 88.0 ] ); // North to the top of the center line $$terminal([ 109.6, 88.2 ] ); $$terminal([ 80.2, 88.2 ] ); // Go West across to the far West side $$terminal([ 80.0, 88.0 ] ); $$terminal([ 80.0, 39.2 ] ); // Go South the whole way $$terminal([ 80.2, 39.0 ] ); $$terminal([ 102.8, 39.0 ] ); // Go East through DCDC3 $$terminal([ 103.0, 39.2 ] ); $$terminal([ 103.0, 61.8 ] ); // Go North a little bit to clear DCDC2 $$terminal([ 103.2, 62.0 ] ); $$terminal([ 139.8, 62.0 ] ); // Go further East for full width $$terminal([ 140.0, 62.2 ] ); $$terminal([ 140.0, 88.0 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_2" 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: BULK_1V2 about ?? mA // // Fill Layer: Signal_12 // // Location: Under only Bank #6 and down to just above the CPU DDR4 chips // // Resolution: HIGH // $$initial([ 110.9, 141.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 110.7, 141.7 ] ); $$terminal([ 80.2, 141.7 ] ); // Go West across the Top of Bank #6 $$terminal([ 80.0, 141.5 ] ); $$terminal([ 80.0, 113.7 ] ); // Go South to just above the CPU DDR4 array $$terminal([ 80.2, 113.5 ] ); $$terminal([ 109.6, 113.5 ] ); // Go East across the top of the CPU DDR4 chips $$terminal([ 109.8, 113.7 ] ); $$terminal([ 109.8, 125.6 ] ); // North to the top of the center line $$terminal([ 109.6, 125.8 ] ); $$terminal([ 106.5, 125.8 ] ); // West to where we can go up into the BGA $$terminal([ 106.3, 126.0 ] ); $$terminal([ 106.3, 130.5 ] ); // North to start cut through Bank #8 Start Slit $$terminal([ 113.7, 137.9 ] ); // North-East to top of the slit End of Slit $$terminal([ 111.1, 137.9 ] ); // Slit is finish now Jog West $$terminal([ 110.9, 138.1 ] ); $$terminal([ 110.9, 141.5 ] ); // Go North - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // Net: BULK_1V2 about ?? mA // // Fill Layer: Signal_12 // // Location: Under only Bank #0 and down to just above the FPGA DDR4 chips // // Resolution: HIGH // $$initial([ 140.0, 139.4], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 139.8, 139.6 ] ); $$terminal([ 120.8, 139.6 ] ); // Go West to where we need to jog down $$terminal([ 120.7, 139.4 ] ); // Go South just a little to get below the FPGA_1V8 Fill $$terminal([ 115.3, 139.4 ] ); // Go West across the top of Bank #0 $$terminal([ 115.1, 139.2 ] ); $$terminal([ 115.1, 138.1 ] ); // Go South a little $$terminal([ 114.9, 137.9 ] ); $$terminal([ 114.1, 137.9 ] ); // Go West to start of slit Start Slit $$terminal([ 106.7, 130.5 ] ); // Run South-West through Bank #8 End of Slit $$terminal([ 106.7, 126.4 ] ); // South to get out of the BGA $$terminal([ 106.9, 126.2 ] ); $$terminal([ 110.0, 126.2 ] ); // East over to the Center Line $$terminal([ 110.2, 126.0 ] ); $$terminal([ 110.2, 113.7 ] ); // Go South down to the top of the FPGA DDR4 $$terminal([ 110.4, 113.5 ] ); $$terminal([ 139.8, 113.5 ] ); // Go East across the top of the FPGA DDR4 chips $$terminal([ 140.0, 113.7 ] ); $$terminal([ 140.0, 139.4 ] ); // Go North - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // Net: BULK_1V2 about ?? mA // // Fill Layer: Signal_12 // // Location: Under only the CPU DDR4 Chips // // Resolution: VERY_HIGH // $$initial([ 109.8, 113.8], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 109.6, 114.0 ] ); $$terminal([ 80.2, 114.0 ] ); // Go West across the Top of the CPU DDR4 chips $$terminal([ 80.0, 113.8 ] ); $$terminal([ 80.0, 87.9 ] ); // Go South the whole way to the bottom of DDR4 chips $$terminal([ 80.2, 87.7 ] ); $$terminal([ 109.6, 87.7 ] ); // Go East just below the CPU DDR4 chips $$terminal([ 109.8, 87.9 ] ); $$terminal([ 109.8, 113.8 ] ); // Go North - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // Net: BULK_1V2 about ?? mA // // Fill Layer: Signal_12 // // Location: Under only the FPGA DDR4 Chips // // Resolution: VERY_HIGH // $$initial([ 140.0, 113.8], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 139.8, 114.0 ] ); $$terminal([ 110.4, 114.0 ] ); // Go West across the Top of the FPGA DDR4 chips $$terminal([ 110.2, 113.8 ] ); $$terminal([ 110.2, 87.9 ] ); // Go South the whole way to the bottom of DDR4 chips $$terminal([ 110.4, 87.7 ] ); $$terminal([ 139.8, 87.7 ] ); // Go East just below the FPGA DDR4 chips $$terminal([ 140.0, 87.9 ] ); $$terminal([ 140.0, 113.8 ] ); // Go North - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // Net: BULK_1V2 about ?? mA // // Fill Layer: Signal_12 // // Location: Under both CA Bus Terminators and down to DCDC3 // // Resolution: HIGH // $$initial([ 140.0, 88.0], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 139.8, 88.2 ] ); $$terminal([ 110.4, 88.2 ] ); // Go West across the Top to the Slit $$terminal([ 110.2, 88.0 ] ); $$terminal([ 110.2, 85.2 ] ); // South to the bottom of the slit $$terminal([ 110.0, 85.0 ] ); $$terminal([ 110.0, 85.0 ] ); // West to the other side of the slit $$terminal([ 109.8, 85.2 ] ); $$terminal([ 109.8, 88.0 ] ); // North to the top of the center line $$terminal([ 109.6, 88.2 ] ); $$terminal([ 80.2, 88.2 ] ); // Go West across to the far West side $$terminal([ 80.0, 88.0 ] ); $$terminal([ 80.0, 39.2 ] ); // Go South the whole way $$terminal([ 80.2, 39.0 ] ); $$terminal([ 102.8, 39.0 ] ); // Go East through DCDC3 $$terminal([ 103.0, 39.2 ] ); $$terminal([ 103.0, 61.8 ] ); // Go North a little bit to clear DCDC2 $$terminal([ 103.2, 62.0 ] ); $$terminal([ 139.8, 62.0 ] ); // Go further East for full width $$terminal([ 140.0, 62.2 ] ); $$terminal([ 140.0, 88.0 ] ); // Go North - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // DDR4 Term Area Fills on Signal Layer 1 & 10 <--- // ===========----------------------------======== // // // // Original Rev. 4-Oct-2024 // Current Rev. 8-Jan-2025 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_1 & Signal_10 in this file are: // // DDR4_FPGA_VTERM 0V6 termination supply for // the FPGA DDR4 memory // // DDR4_CPU_VTERM 0V6 termination supply for // the CPU DDR4 memory // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_1 & Signal_10 fill file // is written on both the layers: // SHAPE_EDIT and // Signal_1 fills are repeated on DIELECTRIC_4 and // Signal_10 files are repeated on DIELECTRIC_3 // // // - As of 10-Oct-2024 there are 4 shapes // that make 4 fills defined in this file. // // // ***** FPGA Memory Terminators ***** // ------ // // Net: DDR4_FPGA_VTERM 200 mA // // Fill Layer: Signal_1 <--- // // Location: Top side by R302:R324 (even) & associated bypass caps // // Resolution: Medium // $$initial([ 137.0, 80.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 136.7, 80.6 ] ); $$terminal([ 120.7, 80.6 ] ); // Go West across the Top $$terminal([ 120.4, 80.3 ] ); $$terminal([ 120.4, 77.5 ] ); // Go South down the West Edge $$terminal([ 120.7, 77.2 ] ); $$terminal([ 136.7, 77.2 ] ); // Go East under the bottom of the fill $$terminal([ 137.0, 77.5 ] ); $$terminal([ 137.0, 80.3 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: DDR4_FPGA_VTERM 200 mA // // Fill Layer: Signal_10 <--- // // Location: Bottom side by R301:R325 (odd) & associated bypass caps // // Resolution: Medium // $$initial([ 137.0, 80.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 136.7, 80.6 ] ); $$terminal([ 119.3, 80.6 ] ); // Go West across the Top $$terminal([ 119.0, 80.3 ] ); $$terminal([ 119.0, 77.5 ] ); // Go South down the West Edge $$terminal([ 119.3, 77.2 ] ); $$terminal([ 136.7, 77.2 ] ); // Go East under the bottom of the fill $$terminal([ 137.0, 77.5 ] ); $$terminal([ 137.0, 80.3 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // ***** CPU Memory Terminators ***** // ----- // // Net: DDR4_CPU_VTERM 200 mA // // Fill Layer: Signal_1 <--- // // Location: Top side by R402:R424 (even) & associated bypass caps // // Resolution: Medium // $$initial([ 99.6, 80.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 99.3, 80.6 ] ); $$terminal([ 83.3, 80.6 ] ); // Go West across the Top $$terminal([ 83.0, 80.3 ] ); $$terminal([ 83.0, 77.5 ] ); // Go South down the West Edge $$terminal([ 83.3, 77.2 ] ); $$terminal([ 99.3, 77.2 ] ); // Go East under the bottom of the fill $$terminal([ 99.6, 77.5 ] ); $$terminal([ 99.6, 80.3 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: DDR4_CPU_VTERM 200 mA // // Fill Layer: Signal_10 <--- // // Location: Bottom side by R401:R425 (odd) & associated bypass caps // // Resolution: Medium // $$initial([ 101.0, 80.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 100.7, 80.6 ] ); $$terminal([ 83.3, 80.6 ] ); // Go West across the Top $$terminal([ 83.0, 80.3 ] ); $$terminal([ 83.0, 77.5 ] ); // Go South down the West Edge $$terminal([ 83.3, 77.2 ] ); $$terminal([ 100.7, 77.2 ] ); // Go East under the bottom of the fill $$terminal([ 101.0, 77.5 ] ); $$terminal([ 101.0, 80.3 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer: Signal_1 ---> DIELECTRIC_4 // // Signal_10 ---> DIELECTRIC_3 // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: DDR4_FPGA_VTERM 200 mA // // Fill Layer: Signal_1 <--- // // Location: Top side by R302:R324 (even) & associated bypass caps // // Resolution: Medium // $$initial([ 137.0, 80.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 136.7, 80.6 ] ); $$terminal([ 120.7, 80.6 ] ); // Go West across the Top $$terminal([ 120.4, 80.3 ] ); $$terminal([ 120.4, 77.5 ] ); // Go South down the West Edge $$terminal([ 120.7, 77.2 ] ); $$terminal([ 136.7, 77.2 ] ); // Go East under the bottom of the fill $$terminal([ 137.0, 77.5 ] ); $$terminal([ 137.0, 80.3 ] ); // Go North - back to home. $$path( "DIELECTRIC_4", 0.0 ); // // Net: DDR4_FPGA_VTERM 200 mA // // Fill Layer: Signal_10 <--- // // Location: Bottom side by R301:R325 (odd) & associated bypass caps // // Resolution: Medium // $$initial([ 137.0, 80.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 136.7, 80.6 ] ); $$terminal([ 119.3, 80.6 ] ); // Go West across the Top $$terminal([ 119.0, 80.3 ] ); $$terminal([ 119.0, 77.5 ] ); // Go South down the West Edge $$terminal([ 119.3, 77.2 ] ); $$terminal([ 136.7, 77.2 ] ); // Go East under the bottom of the fill $$terminal([ 137.0, 77.5 ] ); $$terminal([ 137.0, 80.3 ] ); // Go North - back to home. $$path( "DIELECTRIC_3", 0.0 ); // // ***** CPU Memory Terminators ***** // ----- // // Net: DDR4_CPU_VTERM 200 mA // // Fill Layer: Signal_1 <--- // // Location: Top side by R402:R424 (even) & associated bypass caps // // Resolution: Medium // $$initial([ 99.6, 80.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 99.3, 80.6 ] ); $$terminal([ 83.3, 80.6 ] ); // Go West across the Top $$terminal([ 83.0, 80.3 ] ); $$terminal([ 83.0, 77.5 ] ); // Go South down the West Edge $$terminal([ 83.3, 77.2 ] ); $$terminal([ 99.3, 77.2 ] ); // Go East under the bottom of the fill $$terminal([ 99.6, 77.5 ] ); $$terminal([ 99.6, 80.3 ] ); // Go North - back to home. $$path( "DIELECTRIC_4", 0.0 ); // // Net: DDR4_CPU_VTERM 200 mA // // Fill Layer: Signal_10 <--- // // Location: Bottom side by R401:R425 (odd) & associated bypass caps // // Resolution: Medium // $$initial([ 101.0, 80.3], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 100.7, 80.6 ] ); $$terminal([ 83.3, 80.6 ] ); // Go West across the Top $$terminal([ 83.0, 80.3 ] ); $$terminal([ 83.0, 77.5 ] ); // Go South down the West Edge $$terminal([ 83.3, 77.2 ] ); $$terminal([ 100.7, 77.2 ] ); // Go East under the bottom of the fill $$terminal([ 101.0, 77.5 ] ); $$terminal([ 101.0, 80.3 ] ); // Go North - back to home. $$path( "DIELECTRIC_3", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // DDR4 Term BYPASS Area Fills on Signal Layer 1 & 10 <--- // ===================----------------------------======== // // // // Original Rev. 4-Oct-2024 // Current Rev. 8-Jan-2025 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power net that is distributed // on Signal_1 & Signal_10 in this file are: // // GROUND for the CPU and FPGA CA Bus // Terminator BYPASS Capacitors // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_1 & Signal_10 fill file // is written on both the layers: // SHAPE_EDIT and // Signal_1 fills are repeated on DIELECTRIC_4 and // Signal_10 files are repeated on DIELECTRIC_3 // // // - As of 22-Oct-2024 there are 4 shapes // that make 4 fills defined in this file. // // // ***** FPGA Memory Terminators ***** // ------ // // Net: GROUND for CA Bus Terminator Bypass Capacitors // // Fill Layer: Signal_1 <--- // // Location: Top side by R302:R324 (even) & associated bypass caps // // Resolution: Medium // $$initial([ 136.2, 76.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 135.9, 76.8 ] ); $$terminal([ 119.3, 76.8 ] ); // Go West across the Top $$terminal([ 119.0, 76.5 ] ); $$terminal([ 119.0, 73.8 ] ); // Go South down the West Edge $$terminal([ 119.3, 73.5 ] ); $$terminal([ 135.9, 73.5 ] ); // Go East under the bottom of the fill $$terminal([ 136.2, 73.8 ] ); $$terminal([ 136.2, 76.5 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: GROUND for CA Bus Terminator Bypass Capacitors // // Fill Layer: Signal_10 <--- // // Location: Bottom side by R301:R325 (odd) & associated bypass caps // // Resolution: Medium // $$initial([ 136.4, 76.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 136.1, 76.8 ] ); $$terminal([ 119.3, 76.8 ] ); // Go West across the Top $$terminal([ 119.0, 76.5 ] ); $$terminal([ 119.0, 73.8 ] ); // Go South down the West Edge $$terminal([ 119.3, 73.5 ] ); $$terminal([ 136.1, 73.5 ] ); // Go East under the bottom of the fill $$terminal([ 136.4, 73.8 ] ); $$terminal([ 136.4, 76.5 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // ***** CPU Memory Terminators ***** // ----- // // Net: GROUND for CA Bus Terminator Bypass Capacitors // // Fill Layer: Signal_1 <--- // // Location: Top side by R402:R424 (even) & associated bypass caps // // Resolution: Medium // $$initial([ 101.0, 76.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 100.7, 76.8 ] ); $$terminal([ 84.1, 76.8 ] ); // Go West across the Top $$terminal([ 83.8, 76.5 ] ); $$terminal([ 83.8, 73.8 ] ); // Go South down the West Edge $$terminal([ 84.1, 73.5 ] ); $$terminal([ 100.7, 73.5 ] ); // Go East under the bottom of the fill $$terminal([ 101.0, 73.8 ] ); $$terminal([ 101.0, 76.5 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: GROUND for CA Bus Terminator Bypass Capacitors // // Fill Layer: Signal_10 <--- // // Location: Bottom side by R401:R425 (odd) & associated bypass caps // // Resolution: Medium // $$initial([ 101.0, 76.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 100.7, 76.8 ] ); $$terminal([ 83.3, 76.8 ] ); // Go West across the Top $$terminal([ 83.0, 76.5 ] ); $$terminal([ 83.0, 73.8 ] ); // Go South down the West Edge $$terminal([ 83.3, 73.5 ] ); $$terminal([ 100.7, 73.5 ] ); // Go East under the bottom of the fill $$terminal([ 101.0, 73.8 ] ); $$terminal([ 101.0, 76.5 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer: Signal_1 ---> DIELECTRIC_4 // // Signal_10 ---> DIELECTRIC_3 // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: GROUND for CA Bus Terminator Bypass Capacitors // // Fill Layer: Signal_1 <--- // // Location: Top side by R302:R324 (even) & associated bypass caps // // Resolution: Medium // $$initial([ 136.2, 76.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 135.9, 76.8 ] ); $$terminal([ 119.3, 76.8 ] ); // Go West across the Top $$terminal([ 119.0, 76.5 ] ); $$terminal([ 119.0, 73.8 ] ); // Go South down the West Edge $$terminal([ 119.3, 73.5 ] ); $$terminal([ 135.9, 73.5 ] ); // Go East under the bottom of the fill $$terminal([ 136.2, 73.8 ] ); $$terminal([ 136.2, 76.5 ] ); // Go North - back to home. $$path( "DIELECTRIC_4", 0.0 ); // // Net: GROUND for CA Bus Terminator Bypass Capacitors // // Fill Layer: Signal_10 <--- // // Location: Bottom side by R301:R325 (odd) & associated bypass caps // // Resolution: Medium // $$initial([ 136.4, 76.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 136.1, 76.8 ] ); $$terminal([ 119.3, 76.8 ] ); // Go West across the Top $$terminal([ 119.0, 76.5 ] ); $$terminal([ 119.0, 73.8 ] ); // Go South down the West Edge $$terminal([ 119.3, 73.5 ] ); $$terminal([ 136.1, 73.5 ] ); // Go East under the bottom of the fill $$terminal([ 136.4, 73.8 ] ); $$terminal([ 136.4, 76.5 ] ); // Go North - back to home. $$path( "DIELECTRIC_3", 0.0 ); // // ***** CPU Memory Terminators ***** // ----- // // Net: GROUND for CA Bus Terminator Bypass Capacitors // // Fill Layer: Signal_1 <--- // // Location: Top side by R402:R424 (even) & associated bypass caps // // Resolution: Medium // $$initial([ 101.0, 76.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 100.7, 76.8 ] ); $$terminal([ 84.1, 76.8 ] ); // Go West across the Top $$terminal([ 83.8, 76.5 ] ); $$terminal([ 83.8, 73.8 ] ); // Go South down the West Edge $$terminal([ 84.1, 73.5 ] ); $$terminal([ 100.7, 73.5 ] ); // Go East under the bottom of the fill $$terminal([ 101.0, 73.8 ] ); $$terminal([ 101.0, 76.5 ] ); // Go North - back to home. $$path( "DIELECTRIC_4", 0.0 ); // // Net: GROUND for CA Bus Terminator Bypass Capacitors // // Fill Layer: Signal_10 <--- // // Location: Bottom side by R401:R425 (odd) & associated bypass caps // // Resolution: Medium // $$initial([ 101.0, 76.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 100.7, 76.8 ] ); $$terminal([ 83.3, 76.8 ] ); // Go West across the Top $$terminal([ 83.0, 76.5 ] ); $$terminal([ 83.0, 73.8 ] ); // Go South down the West Edge $$terminal([ 83.3, 73.5 ] ); $$terminal([ 100.7, 73.5 ] ); // Go East under the bottom of the fill $$terminal([ 101.0, 73.8 ] ); $$terminal([ 101.0, 76.5 ] ); // Go North - back to home. $$path( "DIELECTRIC_3", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // DDR4 Wordline 2V5 Area Fills on Signal Layer 11 <--- // ===================----------------------------==== // // // // Original Rev. 4-Oct-2024 // Current Rev. 25-Nov-2024 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_11 in this file are: // // DIGITAL_2V5 Wordline 2V5 supply to the DDR4 Memory Chips // for both the CPU and FPGA Memory Arrays // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // // - As of 22-Oct-2024 there are 2 shape // that make 2 fills defined in this file. // // // Net: DIGITAL_2V5 few mA // // Fill Layer: Signal_11 // // Location: East of the FPGA Memory Chips // // Resolution: Medium // $$initial([ 131.6, 113.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 131.3, 114.0 ] ); $$terminal([ 127.3, 114.0 ] ); // Go West across the Top $$terminal([ 127.0, 113.7 ] ); $$terminal([ 127.0, 87.5 ] ); // Go South down the West side $$terminal([ 127.3, 87.2 ] ); $$terminal([ 131.3, 87.2 ] ); // Go East under the bottom of the Fill $$terminal([ 131.6, 87.5 ] ); $$terminal([ 131.6, 113.7 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: DIGITAL_2V5 few mA // // Fill Layer: Signal_11 // // Location: West of the CPU Memory Chips // // Resolution: Medium // $$initial([ 93.0, 113.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 92.7, 114.0 ] ); $$terminal([ 88.3, 114.0 ] ); // Go West across the Top $$terminal([ 88.0, 113.7 ] ); $$terminal([ 88.0, 87.8 ] ); // Go South down the West side $$terminal([ 88.3, 87.5 ] ); $$terminal([ 92.7, 87.5 ] ); // Go East under the bottom of the Fill $$terminal([ 93.0, 87.8 ] ); $$terminal([ 93.0, 113.7 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer: Signal_11 ---> DIELECTRIC_1 // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: DIGITAL_2V5 few mA // // Fill Layer: Signal_11 // // Location: East of the FPGA Memory Chips // // Resolution: Medium // $$initial([ 131.6, 113.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 131.3, 114.0 ] ); $$terminal([ 127.3, 114.0 ] ); // Go West across the Top $$terminal([ 127.0, 113.7 ] ); $$terminal([ 127.0, 87.5 ] ); // Go South down the West side $$terminal([ 127.3, 87.2 ] ); $$terminal([ 131.3, 87.2 ] ); // Go East under the bottom of the Fill $$terminal([ 131.6, 87.5 ] ); $$terminal([ 131.6, 113.7 ] ); // Go North - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // Net: DIGITAL_2V5 few mA // // Fill Layer: Signal_11 // // Location: West of the CPU Memory Chips // // Resolution: Medium // $$initial([ 93.0, 113.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 92.7, 114.0 ] ); $$terminal([ 88.3, 114.0 ] ); // Go West across the Top $$terminal([ 88.0, 113.7 ] ); $$terminal([ 88.0, 87.8 ] ); // Go South down the West side $$terminal([ 88.3, 87.5 ] ); $$terminal([ 92.7, 87.5 ] ); // Go East under the bottom of the Fill $$terminal([ 93.0, 87.8 ] ); $$terminal([ 93.0, 113.7 ] ); // Go North - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // DDR4 Wordline 2V5 LINK Area Fills on Signal Layer 11 <--- // ===============--==========----------------------------==== // ==== // // // // Original Rev. 25-Dec-2024 // Current Rev. 3-Jan-2025 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_11 in this file are: // // DIGITAL_2V5 LINK from the Digital_2V5 L105 supply // down between the legs of L102 to feed the // Wordline 2V5 supply to the DDR4 Memory Chips // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // // - As of 25-Dec-2024 there 1s 1 shape // that makes 1 fill defined in this file. // // // Net: DIGITAL_2V5 few mA // // Fill Layer: Signal_11 // // Location: L105 then East of the FPGA then Down & through L102 to the Memory Chips // // Resolution: Medium // $$initial([ 150.5, 169.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 150.2, 170.0 ] ); $$terminal([ 117.3, 170.0 ] ); // Go West across the Top $$terminal([ 117.0, 169.7 ] ); $$terminal([ 117.0, 163.3 ] ); // Go South down inside the L105 Fill $$terminal([ 117.3, 163.0 ] ); $$terminal([ 143.1, 163.0 ] ); // Go East to get East of the FPGA East Side Fills $$terminal([ 143.4, 162.7 ] ); $$terminal([ 143.4, 121.6 ] ); // Go South to get down to the top of the L102 slot $$terminal([ 143.1, 121.3 ] ); $$terminal([ 130.0, 121.3 ] ); // Go West through L102 to gain access to WordLine Fills $$terminal([ 129.7, 121.0 ] ); $$terminal([ 129.7, 113.3 ] ); // Go South to get down into the FPGA WordLine Fill $$terminal([ 130.0, 113.0 ] ); $$terminal([ 131.3, 113.0 ] ); // Go East within the FPGA WordLine Fill $$terminal([ 131.6, 113.3 ] ); $$terminal([ 131.6, 119.4 ] ); // Go North up to the bottom of the L102 slot $$terminal([ 131.9, 119.7 ] ); $$terminal([ 150.2, 119.7 ] ); // Go East through the L102 slot to escape $$terminal([ 150.5, 120.0 ] ); $$terminal([ 150.5, 169.7 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer: Signal_11 ---> DIELECTRIC_1 // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: DIGITAL_2V5 few mA // // Fill Layer: Signal_11 // // Location: L105 then East of the FPGA then Down & through L102 to the Memory Chips // // Resolution: Medium // $$initial([ 150.5, 169.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 150.2, 170.0 ] ); $$terminal([ 117.3, 170.0 ] ); // Go West across the Top $$terminal([ 117.0, 169.7 ] ); $$terminal([ 117.0, 163.3 ] ); // Go South down inside the L105 Fill $$terminal([ 117.3, 163.0 ] ); $$terminal([ 143.1, 163.0 ] ); // Go East to get East of the FPGA East Side Fills $$terminal([ 143.4, 162.7 ] ); $$terminal([ 143.4, 121.6 ] ); // Go South to get down to the top of the L102 slot $$terminal([ 143.1, 121.3 ] ); $$terminal([ 130.0, 121.3 ] ); // Go West through L102 to gain access to WordLine Fills $$terminal([ 129.7, 121.0 ] ); $$terminal([ 129.7, 113.3 ] ); // Go South to get down into the FPGA WordLine Fill $$terminal([ 130.0, 113.0 ] ); $$terminal([ 131.3, 113.0 ] ); // Go East within the FPGA WordLine Fill $$terminal([ 131.6, 113.3 ] ); $$terminal([ 131.6, 119.4 ] ); // Go North up to the bottom of the L102 slot $$terminal([ 131.9, 119.7 ] ); $$terminal([ 150.2, 119.7 ] ); // Go East through the L102 slot to escape $$terminal([ 150.5, 120.0 ] ); $$terminal([ 150.5, 169.7 ] ); // Go North - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // Timing Gen Area Fills on Signal Layer 11 & 12 <--- // ============----------------------------========= // // // // Original Rev. 4-Oct-2024 // Current Rev. 3-Jan-2025 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_12 in this file are: // // TIME_GEN_1V8 Main 1V8 supply for the Timing Generator // Fill on Signal_11 // // TIME_GEN_IO_1V8 I/O 1V8 supply for the Timing Generator // Fill on Signal_12 // // BULK_1V8 BULK_1V8 feed from DCDC4 down to the Filter // Inductors for the Timing Generator 1V8 supplies // that are listed just above // Fill on Signal_12 // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // // - As of 3-Nov-2024 there are 3 shapes // that make 3 fills defined in this file. // // // Net: TIME_GEN_1V8 440 mA // // Fill Layer: Signal_11 // // Location: Under most of the Timing Generator area // // Resolution: Medium // $$initial([ 165.5, 59.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 144.3, 59.5 ] ); // Go West across the Top $$terminal([ 144.0, 59.2 ] ); $$terminal([ 144.0, 33.3 ] ); // Go South down the West side $$terminal([ 144.3, 33.0 ] ); $$terminal([ 173.7, 33.0 ] ); // Go East under the bottom of the Fill $$terminal([ 174.0, 33.3 ] ); $$terminal([ 174.0, 51.0 ] ); // Go North - part way back to the top of the fill (added 0.3) $$terminal([ 165.5, 59.5 ] ); // Go North-West at 45 deg - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: TIME_GEN_IO_1V8 5 mA // // Fill Layer: Signal_12 // // Location: Under the center part of the Timing Generator area // // Resolution: Medium // $$initial([ 170.5, 48.2], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 170.2, 48.5 ] ); $$terminal([ 144.3, 48.5 ] ); // Go West across the Top $$terminal([ 144.0, 48.2 ] ); $$terminal([ 144.0, 37.8 ] ); // Go South down the West side $$terminal([ 144.3, 37.5 ] ); $$terminal([ 170.2, 37.5 ] ); // Go East under the bottom of the Fill $$terminal([ 170.5, 37.8 ] ); $$terminal([ 170.5, 48.2 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // Net: BULK_1V8 450 mA // // Fill Layer: Signal_12 // // Location: Vertical Strip East of the FPGA & West of the PMT ADC // // Resolution: Medium // $$initial([ 160.8, 189.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 160.5, 190.0 ] ); $$terminal([ 150.8, 190.0 ] ); // Go West as far as we can for now $$terminal([ 150.5, 189.7 ] ); $$terminal([ 150.5, 169.8 ] ); // Go South down through filter inductor L103 $$terminal([ 150.2, 169.5 ] ); $$terminal([ 142.1, 169.5 ] ); // Go West to the full width for the run down South $$terminal([ 141.8, 169.2 ] ); $$terminal([ 141.8, 60.8 ] ); // Go South down the West side $$terminal([ 142.1, 60.5 ] ); $$terminal([ 152.7, 60.5 ] ); // Go East under L901 $$terminal([ 153.0, 60.8 ] ); $$terminal([ 153.0, 158.7 ] ); // Go North up to where we can get more width to the East $$terminal([ 153.3, 159.0 ] ); $$terminal([ 155.7, 159.0 ] ); // Go East further to run up to the 1V8 supply DCDC4 $$terminal([ 156.0, 159.3 ] ); $$terminal([ 156.0, 168.0 ] ); // Go North up to about the vertical middle of L604 $$terminal([ 156.3, 168.3 ] ); $$terminal([ 160.5, 168.3 ] ); // Go East to about the horizontal middle of L604 $$terminal([ 160.8, 168.6 ] ); $$terminal([ 160.8, 189.7 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer: Signal_11 ---> DIELECTRIC_1 // // Signal_12 ---> DIELECTRIC_2 // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: TIME_GEN_1V8 440 mA // // Fill Layer: Signal_11 // // Location: Under most of the Timing Generator area // // Resolution: Medium // $$initial([ 165.5, 59.5], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 144.3, 59.5 ] ); // Go West across the Top $$terminal([ 144.0, 59.2 ] ); $$terminal([ 144.0, 33.3 ] ); // Go South down the West side $$terminal([ 144.3, 33.0 ] ); $$terminal([ 173.7, 33.0 ] ); // Go East under the bottom of the Fill $$terminal([ 174.0, 33.3 ] ); $$terminal([ 174.0, 51.0 ] ); // Go North - part way back to the top of the fill (added 0.3) $$terminal([ 165.5, 59.5 ] ); // Go North-West at 45 deg - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // Net: TIME_GEN_IO_1V8 5 mA // // Fill Layer: Signal_12 // // Location: Under the center part of the Timing Generator area // // Resolution: Medium // $$initial([ 170.5, 48.2], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 170.2, 48.5 ] ); $$terminal([ 144.3, 48.5 ] ); // Go West across the Top $$terminal([ 144.0, 48.2 ] ); $$terminal([ 144.0, 37.8 ] ); // Go South down the West side $$terminal([ 144.3, 37.5 ] ); $$terminal([ 170.2, 37.5 ] ); // Go East under the bottom of the Fill $$terminal([ 170.5, 37.8 ] ); $$terminal([ 170.5, 48.2 ] ); // Go North - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // Net: BULK_1V8 450 mA // // Fill Layer: Signal_12 // // Location: Vertical Strip East of the FPGA & West of the PMT ADC // // Resolution: Medium // $$initial([ 160.8, 189.7], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 160.5, 190.0 ] ); $$terminal([ 150.8, 190.0 ] ); // Go West as far as we can for now $$terminal([ 150.5, 189.7 ] ); $$terminal([ 150.5, 169.8 ] ); // Go South down through filter inductor L103 $$terminal([ 150.2, 169.5 ] ); $$terminal([ 142.1, 169.5 ] ); // Go West to the full width for the run down South $$terminal([ 141.8, 169.2 ] ); $$terminal([ 141.8, 60.8 ] ); // Go South down the West side $$terminal([ 142.1, 60.5 ] ); $$terminal([ 152.7, 60.5 ] ); // Go East under L901 $$terminal([ 153.0, 60.8 ] ); $$terminal([ 153.0, 158.7 ] ); // Go North up to where we can get more width to the East $$terminal([ 153.3, 159.0 ] ); $$terminal([ 155.7, 159.0 ] ); // Go East further to run up to the 1V8 supply DCDC4 $$terminal([ 156.0, 159.3 ] ); $$terminal([ 156.0, 168.0 ] ); // Go North up to about the vertical middle of L604 $$terminal([ 156.3, 168.3 ] ); $$terminal([ 160.5, 168.3 ] ); // Go East to about the horizontal middle of L604 $$terminal([ 160.8, 168.6 ] ); $$terminal([ 160.8, 189.7 ] ); // Go North - back to home. $$path( "DIELECTRIC_2", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // 2V5 Filter Feed Area Fills on Signal Layer 11 <--- // =================----------------------------==== // // // // Original Rev. 4-Oct-2024 // Current Rev. 30-Oct-2024 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_12 in this file are: // // BULK_2V5 Feed to the Filters on the BULK 2V5 supply // Fill on Signal_11 // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // // - As of 10-Oct-2024 there is 1 shape // that makes 1 fill defined in this file. // // // Net: BULK_2V5 ?? mA // // Fill Layer: Signal_11 // // Location: Under DCDC5 and L104 & L105 // // Resolution: Medium // $$initial([ 134.8, 202.2], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 134.5, 202.5 ] ); $$terminal([ 103.3, 202.5 ] ); // Go West across the Top $$terminal([ 103.0, 202.2 ] ); $$terminal([ 103.0, 184.8 ] ); // Go South down the West side $$terminal([ 103.3, 184.5 ] ); $$terminal([ 134.5, 184.5 ] ); // Go East under the bottom of the Fill $$terminal([ 134.8, 184.8 ] ); $$terminal([ 134.8, 202.2 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer: Signal_11 ---> DIELECTRIC_1 // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: BULK_2V5 ?? mA // // Fill Layer: Signal_11 // // Location: Under DCDC5 and L104 & L105 // // Resolution: Medium // $$initial([ 134.8, 202.2], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 134.5, 202.5 ] ); $$terminal([ 103.3, 202.5 ] ); // Go West across the Top $$terminal([ 103.0, 202.2 ] ); $$terminal([ 103.0, 184.8 ] ); // Go South down the West side $$terminal([ 103.3, 184.5 ] ); $$terminal([ 134.5, 184.5 ] ); // Go East under the bottom of the Fill $$terminal([ 134.8, 184.8 ] ); $$terminal([ 134.8, 202.2 ] ); // Go North - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // BULK_3V3 Area Fills on Signal Layer 11 <--- // ==========----------------------------==== // // // // Original Rev. 4-Oct-2024 // Current Rev. 7-Jan-2025 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - The principal power nets that are distributed // on Signal_11 in this file are: // // BULK_3V3 from the 3V3 DCDC6 converter to the // various 3V3 loads on the DK and to the Interposer. // // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_11 fill file is repeated // on both the layers: DIELECTRIC_1 and SHAPE_EDIT. // See the bottom section of this file. // // - As of 4-Oct-2024 there is 1 shape defined in this file. // // - Note that there is a separate high resolution fill shape // just under the FPGA for the BULK_3V3 net. // // // Net: BULK_3V3 up to 500 mA // // Fill Layer: Signal_11 // // Location: This is a large fill - it merges with the 3V3 fill under the FPGA // // Resolution: Medium // $$initial([ 210.0, 231.0], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 209.0, 232.0 ] ); $$terminal([ 185.0, 232.0 ] ); // Go West across the top of the BB ADC $$terminal([ 184.0, 231.0 ] ); $$terminal([ 184.0, 225.0 ] ); // South to get under the K1 mount and J4 $$terminal([ 183.0, 224.0 ] ); $$terminal([ 132.0, 224.0 ] ); // Go West across part of the Top $$terminal([ 131.0, 225.0 ] ); $$terminal([ 131.0, 228.0 ] ); // Jog North to pick up 3V3 feed to Interposer A - J4 $$terminal([ 130.0, 229.0 ] ); $$terminal([ 123.5, 229.0 ] ); // Go West to where we need to start around the Mounting Screw $$terminal([ 122.5, 228.0 ] ); $$terminal([ 122.5, 225.0 ] ); // Go South to get under the Mounting Screw $$terminal([ 121.5, 224.0 ] ); $$terminal([ 113.5, 224.0 ] ); // Go West under the Mounting Screw to its West Side $$terminal([ 112.5, 225.0 ] ); $$terminal([ 112.5, 228.0 ] ); // Go North back up to our normal run line - now past the Screw $$terminal([ 111.5, 229.0 ] ); $$terminal([ 105.0, 229.0 ] ); // Go West to pick up 3V3 feed to Interposer B - J5 $$terminal([ 104.0, 228.0 ] ); $$terminal([ 104.0, 225.0 ] ); // Go South back to the original Y for the run West $$terminal([ 103.0, 224.0 ] ); $$terminal([ 54.0, 224.0 ] ); // Go West over to the JTAG Buffers $$terminal([ 53.0, 225.0 ] ); $$terminal([ 53.0, 231.0 ] ); // Go North to feed the JTAG Buffers $$terminal([ 52.0, 232.0 ] ); $$terminal([ 17.0, 232.0 ] ); // Go West across the Top of the JTAG Buffers $$terminal([ 16.0, 231.0 ] ); $$terminal([ 16.0, 206.0 ] ); // Go South and avoid the NW corner $$terminal([ 15.0, 205.0 ] ); $$terminal([ 4.0, 205.0 ] ); // Go West to feed the USB Hub $$terminal([ 3.0, 204.0 ] ); $$terminal([ 3.0, 167.5 ] ); // Go South down past the USB Hub - Stop above Isolated RS-485 $$terminal([ 4.0, 166.5 ] ); // Start the relief around the Isolated RS-485 and the Input Power Filter $$terminal([ 16.0, 166.5 ] ); // Go East past the J1 Main Cable Connector $$terminal([ 17.0, 165.5 ] ); $$terminal([ 17.0, 161.0 ] ); // Go South to Top of Isolated RS-485 Transceiver $$terminal([ 18.0, 160.0 ] ); $$terminal([ 50.0, 160.0 ] ); // Go East across the Top of the Iso RS-485 Transceiver $$terminal([ 51.0, 159.0 ] ); $$terminal([ 51.0, 146.0 ] ); // Go South across the end of the Iso RS_485 Transceiver $$terminal([ 50.0, 145.0 ] ); $$terminal([ 41.0, 145.0 ] ); // Go West as far as you can up to the Input Power Filter $$terminal([ 40.0, 144.0 ] ); $$terminal([ 40.0, 17.0 ] ); // Go South down through all of the discrete logic $$terminal([ 41.0, 16.0 ] ); $$terminal([ 69.0, 16.0 ] ); // Go East to get past the Barnacle Connector J7 $$terminal([ 70.0, 15.0 ] ); $$terminal([ 70.0, 4.5 ] ); // Go South so that we can run under DCDC2 & DCDC3 $$terminal([ 71.0, 3.5 ] ); $$terminal([ 111.5, 3.5 ] ); // Go East to where we need to start around the Mounting Screw $$terminal([ 112.5, 4.5 ] ); $$terminal([ 112.5, 10.0 ] ); // Go North to get above the Mounting Screw $$terminal([ 113.5, 11.0 ] ); $$terminal([ 121.5, 11.0 ] ); // Go East above the Mounting Screw to its East Side $$terminal([ 122.5, 10.0 ] ); $$terminal([ 122.5, 4.5 ] ); // Go South back up to our normal run line - now past the Screw $$terminal([ 123.5, 3.5 ] ); $$terminal([ 140.0, 3.5 ] ); // Go East at the bottom of DCDC2 and DCDC3 $$terminal([ 141.0, 2.5 ] ); $$terminal([ 141.0, -30.0 ] ); // Go South so we can pickup up the SFP loads $$terminal([ 142.0, -31.0 ] ); $$terminal([ 176.0, -31.0 ] ); // Go East running under the SFP loads $$terminal([ 177.0, -30.0 ] ); $$terminal([ 177.0, 30.0 ] ); // Go North up past both SFP connectors $$terminal([ 176.0, 31.0 ] ); $$terminal([ 141.0, 31.0 ] ); // Go West just under the Timing Generator $$terminal([ 140.0, 32.0 ] ); $$terminal([ 140.0, 35.5 ] ); // Jog North to pick up some more Width $$terminal([ 139.0, 36.5 ] ); $$terminal([ 102.0, 36.5 ] ); // Go West just through DCDC2 to where we need to start North $$terminal([ 101.0, 37.5 ] ); $$terminal([ 101.0, 69.5 ] ); // Go North up the west side of DCDC2 $$terminal([ 100.0, 70.5 ] ); $$terminal([ 96.0, 70.5 ] ); // Go West so we can pickup the CPU DDR4 Ref & Term Supply $$terminal([ 95.0, 71.5 ] ); $$terminal([ 95.0, 72.0 ] ); // Go North up through the CPU DDR4 Ref & Term Supply $$terminal([ 94.0, 73.0 ] ); $$terminal([ 82.5, 73.0 ] ); // Go West to clear the CPU DDR4 Memory Array $$terminal([ 81.5, 74.0 ] ); $$terminal([ 81.5, 138.1 ] ); // Go North up to where we can join the 3V3 Fill under the FPGA $$terminal([ 82.5, 139.1 ] ); $$terminal([ 94.0, 139.1 ] ); // Go East to get 1 mm into the 3V3 FPGA Fill $$terminal([ 95.0, 140.1 ] ); $$terminal([ 95.0, 162.5 ] ); // Go North up through the 3V3 FPGA Fill $$terminal([ 96.0, 163.5 ] ); $$terminal([ 105.6, 163.5 ] ); // Go East through the 3V3 FPGA Fill $$terminal([ 106.6, 164.5 ] ); $$terminal([ 106.6, 170.0 ] ); // Go North up to where the 2V5 Fill starts $$terminal([ 105.6, 171.0 ] ); $$terminal([ 103.3, 171.0 ] ); // Go West to clear the 2V5 Fill $$terminal([ 102.3, 172.0 ] ); $$terminal([ 102.3, 204.7 ] ); // Go North to get above the 2V5 Fill $$terminal([ 103.3, 205.7 ] ); $$terminal([ 165.5, 205.7 ] ); // Go East $$terminal([ 166.5, 206.7 ] ); $$terminal([ 166.5, 208.0 ] ); // Go North to get above DCDC4 but under the BB ADC $$terminal([ 167.5, 209.0 ] ); $$terminal([ 209.0, 209.0 ] ); // Go East running under the BB ADC $$terminal([ 210.0, 210.0 ] ); $$terminal([ 210.0, 231.0 ] ); // Go North - back to home. $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_1" 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: BULK_3V3 up to 500 mA // // Fill Layer: Signal_11 // // Location: This is a large fill - it merges with the 3V3 fill under the FPGA // // Resolution: Medium // $$initial([ 210.0, 231.0], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 209.0, 232.0 ] ); $$terminal([ 185.0, 232.0 ] ); // Go West across the top of the BB ADC $$terminal([ 184.0, 231.0 ] ); $$terminal([ 184.0, 225.0 ] ); // South to get under the K1 mount and J4 $$terminal([ 183.0, 224.0 ] ); $$terminal([ 132.0, 224.0 ] ); // Go West across part of the Top $$terminal([ 131.0, 225.0 ] ); $$terminal([ 131.0, 228.0 ] ); // Jog North to pick up 3V3 feed to Interposer A - J4 $$terminal([ 130.0, 229.0 ] ); $$terminal([ 123.5, 229.0 ] ); // Go West to where we need to start around the Mounting Screw $$terminal([ 122.5, 228.0 ] ); $$terminal([ 122.5, 225.0 ] ); // Go South to get under the Mounting Screw $$terminal([ 121.5, 224.0 ] ); $$terminal([ 113.5, 224.0 ] ); // Go West under the Mounting Screw to its West Side $$terminal([ 112.5, 225.0 ] ); $$terminal([ 112.5, 228.0 ] ); // Go North back up to our normal run line - now past the Screw $$terminal([ 111.5, 229.0 ] ); $$terminal([ 105.0, 229.0 ] ); // Go West to pick up 3V3 feed to Interposer B - J5 $$terminal([ 104.0, 228.0 ] ); $$terminal([ 104.0, 225.0 ] ); // Go South back to the original Y for the run West $$terminal([ 103.0, 224.0 ] ); $$terminal([ 54.0, 224.0 ] ); // Go West over to the JTAG Buffers $$terminal([ 53.0, 225.0 ] ); $$terminal([ 53.0, 231.0 ] ); // Go North to feed the JTAG Buffers $$terminal([ 52.0, 232.0 ] ); $$terminal([ 17.0, 232.0 ] ); // Go West across the Top of the JTAG Buffers $$terminal([ 16.0, 231.0 ] ); $$terminal([ 16.0, 206.0 ] ); // Go South and avoid the NW corner $$terminal([ 15.0, 205.0 ] ); $$terminal([ 4.0, 205.0 ] ); // Go West to feed the USB Hub $$terminal([ 3.0, 204.0 ] ); $$terminal([ 3.0, 167.5 ] ); // Go South down past the USB Hub - Stop above Isolated RS-485 $$terminal([ 4.0, 166.5 ] ); // Start the relief around the Isolated RS-485 and the Input Power Filter $$terminal([ 16.0, 166.5 ] ); // Go East past the J1 Main Cable Connector $$terminal([ 17.0, 165.5 ] ); $$terminal([ 17.0, 161.0 ] ); // Go South to Top of Isolated RS-485 Transceiver $$terminal([ 18.0, 160.0 ] ); $$terminal([ 50.0, 160.0 ] ); // Go East across the Top of the Iso RS-485 Transceiver $$terminal([ 51.0, 159.0 ] ); $$terminal([ 51.0, 146.0 ] ); // Go South across the end of the Iso RS_485 Transceiver $$terminal([ 50.0, 145.0 ] ); $$terminal([ 41.0, 145.0 ] ); // Go West as far as you can up to the Input Power Filter $$terminal([ 40.0, 144.0 ] ); $$terminal([ 40.0, 17.0 ] ); // Go South down through all of the discrete logic $$terminal([ 41.0, 16.0 ] ); $$terminal([ 69.0, 16.0 ] ); // Go East to get past the Barnacle Connector J7 $$terminal([ 70.0, 15.0 ] ); $$terminal([ 70.0, 4.5 ] ); // Go South so that we can run under DCDC2 & DCDC3 $$terminal([ 71.0, 3.5 ] ); $$terminal([ 111.5, 3.5 ] ); // Go East to where we need to start around the Mounting Screw $$terminal([ 112.5, 4.5 ] ); $$terminal([ 112.5, 10.0 ] ); // Go North to get above the Mounting Screw $$terminal([ 113.5, 11.0 ] ); $$terminal([ 121.5, 11.0 ] ); // Go East above the Mounting Screw to its East Side $$terminal([ 122.5, 10.0 ] ); $$terminal([ 122.5, 4.5 ] ); // Go South back up to our normal run line - now past the Screw $$terminal([ 123.5, 3.5 ] ); $$terminal([ 140.0, 3.5 ] ); // Go East at the bottom of DCDC2 and DCDC3 $$terminal([ 141.0, 2.5 ] ); $$terminal([ 141.0, -30.0 ] ); // Go South so we can pickup up the SFP loads $$terminal([ 142.0, -31.0 ] ); $$terminal([ 176.0, -31.0 ] ); // Go East running under the SFP loads $$terminal([ 177.0, -30.0 ] ); $$terminal([ 177.0, 30.0 ] ); // Go North up past both SFP connectors $$terminal([ 176.0, 31.0 ] ); $$terminal([ 141.0, 31.0 ] ); // Go West just under the Timing Generator $$terminal([ 140.0, 32.0 ] ); $$terminal([ 140.0, 35.5 ] ); // Jog North to pick up some more Width $$terminal([ 139.0, 36.5 ] ); $$terminal([ 102.0, 36.5 ] ); // Go West just through DCDC2 to where we need to start North $$terminal([ 101.0, 37.5 ] ); $$terminal([ 101.0, 69.5 ] ); // Go North up the west side of DCDC2 $$terminal([ 100.0, 70.5 ] ); $$terminal([ 96.0, 70.5 ] ); // Go West so we can pickup the CPU DDR4 Ref & Term Supply $$terminal([ 95.0, 71.5 ] ); $$terminal([ 95.0, 72.0 ] ); // Go North up through the CPU DDR4 Ref & Term Supply $$terminal([ 94.0, 73.0 ] ); $$terminal([ 82.5, 73.0 ] ); // Go West to clear the CPU DDR4 Memory Array $$terminal([ 81.5, 74.0 ] ); $$terminal([ 81.5, 138.1 ] ); // Go North up to where we can join the 3V3 Fill under the FPGA $$terminal([ 82.5, 139.1 ] ); $$terminal([ 94.0, 139.1 ] ); // Go East to get 1 mm into the 3V3 FPGA Fill $$terminal([ 95.0, 140.1 ] ); $$terminal([ 95.0, 162.5 ] ); // Go North up through the 3V3 FPGA Fill $$terminal([ 96.0, 163.5 ] ); $$terminal([ 105.6, 163.5 ] ); // Go East through the 3V3 FPGA Fill $$terminal([ 106.6, 164.5 ] ); $$terminal([ 106.6, 170.0 ] ); // Go North up to where the 2V5 Fill starts $$terminal([ 105.6, 171.0 ] ); $$terminal([ 103.3, 171.0 ] ); // Go West to clear the 2V5 Fill $$terminal([ 102.3, 172.0 ] ); $$terminal([ 102.3, 204.7 ] ); // Go North to get above the 2V5 Fill $$terminal([ 103.3, 205.7 ] ); $$terminal([ 165.5, 205.7 ] ); // Go East $$terminal([ 166.5, 206.7 ] ); $$terminal([ 166.5, 208.0 ] ); // Go North to get above DCDC4 but under the BB ADC $$terminal([ 167.5, 209.0 ] ); $$terminal([ 209.0, 209.0 ] ); // Go East running under the BB ADC $$terminal([ 210.0, 210.0 ] ); $$terminal([ 210.0, 231.0 ] ); // Go North - back to home. $$path( "DIELECTRIC_1", 0.0 ); // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // Shield Ground Fill on Signal Layer 1 <--- // -----------------------------------=== // // // Analog Input Shield Fill on Signal Layer 1 // ---------------------------------------=======-- // // // Original Rev. 21-Feb-2025 // Current Rev. 6-Mar-2025 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - This Fill is a Ground Plane on the Top L1 Signal 1 // layer that is a Shield Grounded that is over the PMT // Analog Input Section. // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_1 fill file is repeated // on both the layers: DIELECTRIC_4 and SHAPE_EDIT. // See the bottom section of this file. // // - As of 21-Feb-2025 there are 1 shape defined in this file. // // - All required mitters are built into this file. // This file does not use the external mitter program. // // // Net: Net Name SHIELD - Ground Plane over Analog Input Section // // Fill Layer: Signal_1 // // Location: Top side PMT Analog Input Section // // Resolution: Medium // $$initial([ 227.9, 174.0 ], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 181.7, 174.0 ] ); // Go West across the Top $$terminal([ 180.2, 172.5 ] ); // $$terminal([ 180.2, 168.3 ] ); // Go South to stay within the Analog Section $$terminal([ 179.7, 167.8 ] ); // $$terminal([ 177.0, 167.8 ] ); // Go West the rest of the way $$terminal([ 176.5, 167.3 ] ); // $$terminal([ 176.5, 162.2 ] ); // Go South just to clear PVA618 $$terminal([ 176.0, 161.7 ] ); // $$terminal([ 165.5, 161.7 ] ); // Go West just past the PMT ADC $$terminal([ 165.0, 161.2 ] ); // power feed e.g. to pick up SH2 $$terminal([ 165.0, 141.1 ] ); // Go South just past SH2 $$terminal([ 165.5, 140.6 ] ); // $$terminal([ 174.0, 140.6 ] ); // Go back East to the classic $$terminal([ 174.5, 140.1 ] ); // part of this fill $$terminal([ 174.5, 138.9 ] ); // Go South $$terminal([ 175.0, 138.4 ] ); // $$terminal([ 178.0, 138.4 ] ); // Go East $$terminal([ 178.5, 137.9 ] ); // // Jog East to clear C621 $$terminal([ 178.5, 106.5 ] ); // Go South $$terminal([ 179.0, 106.0 ] ); // $$terminal([ 180.3, 106.0 ] ); // Go East $$terminal([ 180.8, 105.5 ] ); // $$terminal([ 180.8, 102.3 ] ); // Go South $$terminal([ 180.3, 101.8 ] ); // $$terminal([ 175.2, 101.8 ] ); // Go West until we run $$terminal([ 174.7, 101.3 ] ); // into C602 $$terminal([ 174.7, 99.0 ] ); // Go South just to clear $$terminal([ 174.2, 98.5 ] ); // the Hot pin of C602 $$terminal([ 164.5, 98.5 ] ); // Go West over to SH1 $$terminal([ 164.0, 98.0 ] ); // $$terminal([ 164.0, 84.8 ] ); // Go South to where we $$terminal([ 164.5, 84.3 ] ); // run into PVA601 $$terminal([ 176.4, 84.3 ] ); // Go back East to the $$terminal([ 176.8, 83.9 ] ); // classic part of this fill $$terminal([ 176.8, 77.7 ] ); // Go South $$terminal([ 177.3, 77.2 ] ); // $$terminal([ 178.3, 77.2 ] ); // Go East $$terminal([ 179.2, 76.3 ] ); // $$terminal([ 179.2, 72.5 ] ); // Go South // Start a 45 deg run to the South East $$terminal([ 187.7, 64.0 ] ); // Go South-East $$terminal([ 201.8, 64.0 ] ); // Go East // Start a 45 deg run to the South East $$terminal([ 204.8, 61.0 ] ); // Go South-East $$terminal([ 227.9, 61.0 ] ); // Go East // Now run North back Home $$terminal([ 227.9, 174.0 ] ); // Go North $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_4", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: Net Name SHIELD - Ground Plane over Analog Input Section // // Fill Layer: Signal_1 // // Location: Top side PMT Analog Input Section // // Resolution: Medium // $$initial([ 227.9, 174.0 ], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 181.7, 174.0 ] ); // Go West across the Top $$terminal([ 180.2, 172.5 ] ); // $$terminal([ 180.2, 168.3 ] ); // Go South to stay within the Analog Section $$terminal([ 179.7, 167.8 ] ); // $$terminal([ 177.0, 167.8 ] ); // Go West the rest of the way $$terminal([ 176.5, 167.3 ] ); // $$terminal([ 176.5, 162.2 ] ); // Go South just to clear PVA618 $$terminal([ 176.0, 161.7 ] ); // $$terminal([ 165.5, 161.7 ] ); // Go West just past the PMT ADC $$terminal([ 165.0, 161.2 ] ); // power feed e.g. to pick up SH2 $$terminal([ 165.0, 141.1 ] ); // Go South just past SH2 $$terminal([ 165.5, 140.6 ] ); // $$terminal([ 174.0, 140.6 ] ); // Go back East to the classic $$terminal([ 174.5, 140.1 ] ); // part of this fill $$terminal([ 174.5, 138.9 ] ); // Go South $$terminal([ 175.0, 138.4 ] ); // $$terminal([ 178.0, 138.4 ] ); // Go East $$terminal([ 178.5, 137.9 ] ); // // Jog East to clear C621 $$terminal([ 178.5, 106.5 ] ); // Go South $$terminal([ 179.0, 106.0 ] ); // $$terminal([ 180.3, 106.0 ] ); // Go East $$terminal([ 180.8, 105.5 ] ); // $$terminal([ 180.8, 102.3 ] ); // Go South $$terminal([ 180.3, 101.8 ] ); // $$terminal([ 175.2, 101.8 ] ); // Go West until we run $$terminal([ 174.7, 101.3 ] ); // into C602 $$terminal([ 174.7, 99.0 ] ); // Go South just to clear $$terminal([ 174.2, 98.5 ] ); // the Hot pin of C602 $$terminal([ 164.5, 98.5 ] ); // Go West over to SH1 $$terminal([ 164.0, 98.0 ] ); // $$terminal([ 164.0, 84.8 ] ); // Go South to where we $$terminal([ 164.5, 84.3 ] ); // run into PVA601 $$terminal([ 176.4, 84.3 ] ); // Go back East to the $$terminal([ 176.8, 83.9 ] ); // classic part of this fill $$terminal([ 176.8, 77.7 ] ); // Go South $$terminal([ 177.3, 77.2 ] ); // $$terminal([ 178.3, 77.2 ] ); // Go East $$terminal([ 179.2, 76.3 ] ); // $$terminal([ 179.2, 72.5 ] ); // Go South // Start a 45 deg run to the South East $$terminal([ 187.7, 64.0 ] ); // Go South-East $$terminal([ 201.8, 64.0 ] ); // Go East // Start a 45 deg run to the South East $$terminal([ 204.8, 61.0 ] ); // Go South-East $$terminal([ 227.9, 61.0 ] ); // Go East // Now run North back Home $$terminal([ 227.9, 174.0 ] ); // Go North $$path( "DIELECTRIC_4", 0.0 ); // // Shape Edit Section of the // -==========----------------- // // Disco-Kraken Printed Circuit Board Geometry File // ---------------------------------------------------- // // // Shield Ground Fill on Signal Layer 10 <--- // -----------------------------------==== // // // Analog Input Shield Fill on Signal Layer 10 // ---------------------------------------========-- // // // Original Rev. 21-Feb-2025 // Current Rev. 6-Mar-2025 // // // Notes: // // - These are Area Fills because they are on a Signal layer // in the Mentor design. // // - This Fill is a Ground Plane on the Bottom L12 Signal 10 // layer that is a Shield Grounded that is over the PMT // Analog Input Section. // // - These fills are kept back at least 1mm from all // edges of the DK PCB to comply with normal decorum. // // - EVERYTHING in this Signal_10 fill file is repeated // on both the layers: DIELECTRIC_3 and SHAPE_EDIT. // See the bottom section of this file. // // - As of 21-Feb-2025 there are 1 shape defined in this file. // // - All required mitters are built into this file. // This file does not use the external mitter program. // // // Net: Net Name SHIELD - Ground Plane over Analog Input Section // // Fill Layer: Signal_10 // // Location: Bottom side PMT Analog Input Section // // Resolution: Medium // $$initial([ 227.9, 174.0 ], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 181.7, 174.0 ] ); // Go West across the Top $$terminal([ 180.2, 172.5 ] ); // $$terminal([ 180.2, 168.3 ] ); // Go South to stay within the Analog Section $$terminal([ 179.7, 167.8 ] ); // $$terminal([ 177.0, 167.8 ] ); // Go West the rest of the way $$terminal([ 176.5, 167.3 ] ); // $$terminal([ 176.5, 159.8 ] ); // Go South to just the Hot $$terminal([ 176.0, 159.3 ] ); // pin on C618 $$terminal([ 165.5, 159.3 ] ); // Go West to the far side $$terminal([ 165.0, 158.8 ] ); // of SH2 $$terminal([ 165.0, 141.1 ] ); // Go South down to SH2 $$terminal([ 165.5, 140.6 ] ); // $$terminal([ 174.0, 140.6 ] ); // Go back East towards the $$terminal([ 174.5, 140.1 ] ); // classic part of this fill $$terminal([ 174.5, 138.9 ] ); // Go South just a little down $$terminal([ 175.0, 138.4 ] ); // to C620 $$terminal([ 178.0, 138.4 ] ); // Go back East now into $$terminal([ 178.5, 137.9 ] ); // the classic fill shape $$terminal([ 178.5, 102.3 ] ); // Go South $$terminal([ 178.0, 101.8 ] ); // $$terminal([ 174.8, 101.8 ] ); // Go West $$terminal([ 174.3, 101.3 ] ); // towards PVA602 $$terminal([ 174.3, 99.9 ] ); // Go South $$terminal([ 173.8, 99.4 ] ); // to get under PVA602 $$terminal([ 164.5, 99.4 ] ); // Go West towards SH1 $$terminal([ 164.0, 98.9 ] ); // $$terminal([ 164.0, 87.1 ] ); // Go South $$terminal([ 164.5, 86.6 ] ); // into C601 $$terminal([ 174.4, 86.6 ] ); // Go East back towards $$terminal([ 174.9, 86.1 ] ); // the classic part of this fill $$terminal([ 174.9, 85.8 ] ); // Go South with a $$terminal([ 176.8, 83.9 ] ); // big 45 deg mitter to the SE $$terminal([ 176.8, 77.7 ] ); // Go South $$terminal([ 177.3, 77.2 ] ); // $$terminal([ 178.3, 77.2 ] ); // Go East $$terminal([ 179.2, 76.3 ] ); // $$terminal([ 179.2, 72.5 ] ); // Go South // Start a 45 deg run to the South East $$terminal([ 187.7, 64.0 ] ); // Go South-East $$terminal([ 201.8, 64.0 ] ); // Go East // Start a 45 deg run to the South East $$terminal([ 204.8, 61.0 ] ); // Go South-East $$terminal([ 227.9, 61.0 ] ); // Go East // Now run North back Home $$terminal([ 227.9, 174.0 ] ); // Go North $$path( "SHAPE_EDIT", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // Repete the above on design layer $$path( "DIELECTRIC_3", 0.0 ); // // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- // // // Net: Net Name SHIELD - Ground Plane over Analog Input Section // // Fill Layer: Signal_10 // // Location: Bottom side PMT Analog Input Section // // Resolution: Medium // $$initial([ 227.9, 174.0 ], , @nosnap ); // Start in the NE corner - go CCW $$terminal([ 181.7, 174.0 ] ); // Go West across the Top $$terminal([ 180.2, 172.5 ] ); // $$terminal([ 180.2, 168.3 ] ); // Go South to stay within the Analog Section $$terminal([ 179.7, 167.8 ] ); // $$terminal([ 177.0, 167.8 ] ); // Go West the rest of the way $$terminal([ 176.5, 167.3 ] ); // $$terminal([ 176.5, 159.8 ] ); // Go South to just the Hot $$terminal([ 176.0, 159.3 ] ); // pin on C618 $$terminal([ 165.5, 159.3 ] ); // Go West to the far side $$terminal([ 165.0, 158.8 ] ); // of SH2 $$terminal([ 165.0, 141.1 ] ); // Go South down to SH2 $$terminal([ 165.5, 140.6 ] ); // $$terminal([ 174.0, 140.6 ] ); // Go back East towards the $$terminal([ 174.5, 140.1 ] ); // classic part of this fill $$terminal([ 174.5, 138.9 ] ); // Go South just a little down $$terminal([ 175.0, 138.4 ] ); // to C620 $$terminal([ 178.0, 138.4 ] ); // Go back East now into $$terminal([ 178.5, 137.9 ] ); // the classic fill shape $$terminal([ 178.5, 102.3 ] ); // Go South $$terminal([ 178.0, 101.8 ] ); // $$terminal([ 174.8, 101.8 ] ); // Go West $$terminal([ 174.3, 101.3 ] ); // towards PVA602 $$terminal([ 174.3, 99.9 ] ); // Go South $$terminal([ 173.8, 99.4 ] ); // to get under PVA602 $$terminal([ 164.5, 99.4 ] ); // Go West towards SH1 $$terminal([ 164.0, 98.9 ] ); // $$terminal([ 164.0, 87.1 ] ); // Go South $$terminal([ 164.5, 86.6 ] ); // into C601 $$terminal([ 174.4, 86.6 ] ); // Go East back towards $$terminal([ 174.9, 86.1 ] ); // the classic part of this fill $$terminal([ 174.9, 85.8 ] ); // Go South with a $$terminal([ 176.8, 83.9 ] ); // big 45 deg mitter to the SE $$terminal([ 176.8, 77.7 ] ); // Go South $$terminal([ 177.3, 77.2 ] ); // $$terminal([ 178.3, 77.2 ] ); // Go East $$terminal([ 179.2, 76.3 ] ); // $$terminal([ 179.2, 72.5 ] ); // Go South // Start a 45 deg run to the South East $$terminal([ 187.7, 64.0 ] ); // Go South-East $$terminal([ 201.8, 64.0 ] ); // Go East // Start a 45 deg run to the South East $$terminal([ 204.8, 61.0 ] ); // Go South-East $$terminal([ 227.9, 61.0 ] ); // Go East // Now run North back Home $$terminal([ 227.9, 174.0 ] ); // Go North $$path( "DIELECTRIC_3", 0.0 ); // // file: disco_pcb_ground_plane_exclusions.txt // // date: Original Rev. 10-July-2024 // Current Rev. 9-Mar-2025 // // // // // Notes: // // This source file in the overall Disco pcb design holds the // various cuts and exclusion areas in the ground planes // of the Disco-Kraken pcb. // // There are 4 ground planes in the Disco PCB. // During Gerber Plot generation all 4 of these Ground Planes // will be plotted individually - even though some of them // may be equivalent. // // As the Gnd Planes are plotted as negative data we can put // cuts or exclusions in them by including graphic elements // in the Disco's pcb geometry. // // As the Disco's "artwork_order" file is setup: // // Elements on PREPREG 1 will remove copper from the Upper Gnd Pln // Elements on PREPREG 2 will remove copper from the Lower Gnd Pln // Elements on PREPREG 3 will remove copper from the ALL Gnd Plns // // // We don't want to allow currents to flow in the ground planes // in the PMT Analgo Input section. The following are slits in the // gound planes both above and below the PMT Analog Input section // to control ground currents that otherwise would flow in this // area. // // // Slits above the PMT Analog Input section: // $$path( "PREPREG_3", 0.20, , [ 156.0, 168.0, 179.0, 168.0 ]); $$path( "PREPREG_3", 0.20, , [ 179.0, 168.0, 180.0, 169.0 ]); $$path( "PREPREG_3", 0.20, , [ 180.0, 169.0, 180.0, 174.0 ]); $$path( "PREPREG_3", 0.20, , [ 180.0, 174.0, 181.0, 175.0 ]); $$path( "PREPREG_3", 0.20, , [ 181.0, 175.0, 235.0, 175.0 ]); // // Slits below the PMT Analog Input section: // $$path( "PREPREG_3", 0.20, , [ 156.0, 77.0, 178.0, 77.0 ]); $$path( "PREPREG_3", 0.20, , [ 178.0, 77.0, 179.0, 76.0 ]); $$path( "PREPREG_3", 0.20, , [ 179.0, 76.0, 179.0, 71.0 ]); $$path( "PREPREG_3", 0.20, , [ 179.0, 71.0, 187.0, 63.0 ]); $$path( "PREPREG_3", 0.20, , [ 187.0, 63.0, 202.0, 63.0 ]); $$path( "PREPREG_3", 0.20, , [ 202.0, 63.0, 205.0, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 205.0, 60.0, 235.0, 60.0 ]); // // Exclusion at the East boarder of the PMT Analog Input section: // $$path( "PREPREG_3", 0.20, , [ 234.9, 175.0, 234.9, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 234.8, 175.0, 234.8, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 234.7, 175.0, 234.7, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 234.6, 175.0, 234.6, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 234.5, 175.0, 234.5, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 234.4, 175.0, 234.4, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 234.3, 175.0, 234.3, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 234.2, 175.0, 234.2, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 234.1, 175.0, 234.1, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 234.0, 175.0, 234.0, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 233.9, 175.0, 233.9, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 233.8, 175.0, 233.8, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 233.7, 175.0, 233.7, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 233.6, 175.0, 233.6, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 233.5, 175.0, 233.5, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 233.4, 175.0, 233.4, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 233.3, 175.0, 233.3, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 233.2, 175.0, 233.2, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 233.1, 175.0, 233.1, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 233.0, 175.0, 233.0, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 232.9, 175.0, 232.9, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 232.8, 175.0, 232.8, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 232.7, 175.0, 232.7, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 232.6, 175.0, 232.6, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 232.5, 175.0, 232.5, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 232.4, 175.0, 232.4, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 232.3, 175.0, 232.3, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 232.2, 175.0, 232.2, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 232.1, 175.0, 232.1, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 232.0, 175.0, 232.0, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 231.9, 175.0, 231.9, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 231.8, 175.0, 231.8, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 231.7, 175.0, 231.7, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 231.6, 175.0, 231.6, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 231.5, 175.0, 231.5, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 231.4, 175.0, 231.4, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 231.3, 175.0, 231.3, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 231.2, 175.0, 231.2, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 231.1, 175.0, 231.1, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 231.0, 175.0, 231.0, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 230.9, 175.0, 230.9, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 230.8, 175.0, 230.8, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 230.7, 175.0, 230.7, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 230.6, 175.0, 230.6, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 230.5, 175.0, 230.5, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 230.4, 175.0, 230.4, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 230.3, 175.0, 230.3, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 230.2, 175.0, 230.2, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 230.1, 175.0, 230.1, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 230.0, 175.0, 230.0, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 229.9, 175.0, 229.9, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 229.8, 175.0, 229.8, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 229.7, 175.0, 229.7, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 229.6, 175.0, 229.6, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 229.5, 175.0, 229.5, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 229.4, 175.0, 229.4, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 229.3, 175.0, 229.3, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 229.2, 175.0, 229.2, 60.0 ]); $$path( "PREPREG_3", 0.20, , [ 229.1, 175.0, 229.1, 60.0 ]); // // Relieve the Ground Planes (all 4) from around the Harwin // connector (PMT Input Connector) Mounting Screw Holes. // This is a 3.75 mm diameter relief. It is needed on the // DK board because these plated screw holes are connectd to // the SHIELD Net and not to the GROUND Net. // $$circle( "PREPREG_3", 227.9, 171.5, 3.75, 0.0 ); $$circle( "PREPREG_3", 227.9, 134.5, 3.75, 0.0 ); $$circle( "PREPREG_3", 227.9, 100.5, 3.75, 0.0 ); $$circle( "PREPREG_3", 227.9, 63.5, 3.75, 0.0 ); // // Relieve the Ground Planes (all 4) from around the // Center East Board Mounting Hole. Jumper JMP1B can // be used to connect this board mounting hole to the // SHIELD net not to the GROUND net. // $$circle( "PREPREG_3", 229.0, 117.5, 7.60, 0.0 ); // // Slits along the West edge to provide Ground Isolation // for the: Input Power Filter and for the ER RS-485 Bus // // Recall that the only thing in the Input Power Filter // that is connected to the DK Board's Signal Ground are // the over voltage protection components: TVS1 and TVS2. // See Drawing #2 // // Recall that the only thing in the Isolated side of the // RS-458 Transceiver that is tied to the DK Board's // Signal Ground is the over voltage protection TVS1001. // // See Drawing #82 // // // Slit around the Isolated part of the RS-485 Transceiver // --------------------------------------- // $$path( "PREPREG_3", 0.30, , [ 0.0, 166.0, 15.5, 166.0 ]); $$path( "PREPREG_3", 0.30, , [ 15.5, 166.0, 16.5, 165.0 ]); $$path( "PREPREG_3", 0.30, , [ 16.5, 165.0, 16.5, 160.8 ]); // Run East $$path( "PREPREG_3", 0.30, , [ 16.5, 160.8, 17.5, 159.8 ]); $$path( "PREPREG_3", 0.30, , [ 17.5, 159.8, 48.7, 159.8 ]); $$path( "PREPREG_3", 0.30, , [ 48.7, 159.8, 49.5, 159.0 ]); // Run South $$path( "PREPREG_3", 0.30, , [ 49.5, 159.0, 49.5, 147.5 ]); $$path( "PREPREG_3", 0.30, , [ 49.5, 147.5, 47.5, 145.5 ]); // Run Back West $$path( "PREPREG_3", 0.30, , [ 47.5, 145.5, 16.0, 145.5 ]); $$path( "PREPREG_3", 0.30, , [ 16.0, 145.5, 14.8, 146.7 ]); $$path( "PREPREG_3", 0.30, , [ 14.8, 146.7, 0.0, 146.7 ]); // // Slit around the Power Input Filter // -------------------- // $$path( "PREPREG_3", 0.30, , [ 33.0, 145.5, 33.0, 136.0 ]); $$path( "PREPREG_3", 0.30, , [ 33.0, 136.0, 34.0, 135.0 ]); $$path( "PREPREG_3", 0.30, , [ 34.0, 135.0, 38.5, 135.0 ]); $$path( "PREPREG_3", 0.30, , [ 38.5, 135.0, 39.5, 134.0 ]); $$path( "PREPREG_3", 0.30, , [ 39.5, 134.0, 39.5, 118.5 ]); $$path( "PREPREG_3", 0.30, , [ 39.5, 118.5, 38.5, 117.5 ]); $$path( "PREPREG_3", 0.30, , [ 38.5, 117.5, 31.5, 117.5 ]); $$path( "PREPREG_3", 0.30, , [ 31.5, 117.5, 30.5, 116.5 ]); $$path( "PREPREG_3", 0.30, , [ 30.5, 116.5, 30.5, 97.0 ]); $$path( "PREPREG_3", 0.30, , [ 30.5, 97.0, 27.5, 94.0 ]); $$path( "PREPREG_3", 0.30, , [ 27.5, 94.0, 27.5, 77.0 ]); $$path( "PREPREG_3", 0.30, , [ 27.5, 77.0, 23.5, 73.0 ]); $$path( "PREPREG_3", 0.30, , [ 23.5, 73.0, 0.0, 73.0 ]); // // Recall that in addition to the above, that the ground plane // is relieved back 0.5mm from all of the actual edges of the pcb. // This is controlled by the board_edge_clearance attribute in // the Hub's "artwork_order" file. // // // file: disco_pcb_sierra_silkscreen.txt // // date: Original Rev. 23-Jan-2025 // Current Rev. 18-Feb-2025 // // Dan Edit 6-Mar-2025 Comment out the Serial Number wide line // Repair the P-ONE Label missing width // // Dan Edit 11-Mar-2025 Move and add many witness lines for // the Memory chip risistor and capacitor // reference designators // // Dan Edit 12-Mar-2025 Rotate labels for the Interposer connectors // so they are right side up for perimeter reading // Merge in Sierra's work from 10-Mar-25 Jumper Labels // Start adding Bottom Side witness lines // // Dan Edit 13,14-Mar-2025 Add many more witness lines // // // // Disco-Kraken // // PCB Geometry Sierra's Reference Designator Silkscreen // // // This file in the overall DK PCB Geometry holds various // silkscreen lines and such associated with making the // crowded Reference Designators easier to read. // // // // Bottom of board Witness Lines and such: // // XCVR Box of Ref Desig $$path( "SILKSCREEN_2", 0.20, , [ 141.0, 165.0, 153.0, 165.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 153.0, 165.0, 153.0, 143.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 153.0, 143.0, 141.0, 143.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 141.0, 143.0, 141.0, 165.0 ]); // Witness into FPGA BGA $$path( "SILKSCREEN_2", 0.20, , [ 129.5, 152.5, 130.1, 153.1 ]); $$path( "SILKSCREEN_2", 0.20, , [ 130.1, 153.1, 141.0, 153.1 ]); // XCVR Box in FPGA BGA $$path( "SILKSCREEN_2", 0.20, , [ 125.5, 152.5, 129.5, 152.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 129.5, 152.5, 129.5, 133.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 129.5, 133.5, 121.5, 133.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 121.5, 147.5, 121.5, 133.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 121.5, 147.5, 123.5, 147.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 123.5, 147.5, 123.5, 152.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 123.5, 152.5, 125.5, 152.5 ]); // Top Left Box in the FPGA $$path( "SILKSCREEN_2", 0.20, , [ 104.5, 157.5, 104.5, 151.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 104.5, 151.5, 106.5, 151.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 106.5, 151.5, 106.5, 148.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 106.5, 148.0, 108.6, 148.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 109.4, 148.0, 109.6, 148.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 110.4, 148.0, 110.6, 148.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 111.4, 148.0, 112.6, 148.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 113.3, 147.7, 113.5, 147.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 113.5, 147.5, 121.5, 147.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 123.5, 152.5, 123.5, 156.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 122.6, 156.0, 119.4, 156.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 113.6, 156.0, 109.0, 156.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 109.0, 156.0, 109.0, 157.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 109.0, 157.5, 104.5, 157.5 ]); // Top Left Witness Lines box to box $$path( "SILKSCREEN_2", 0.20, , [ 95.0, 157.5, 95.0, 155.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 95.0, 155.5, 96.0, 154.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 96.0, 154.5, 104.5, 154.5 ]); // Top Left Ref Desig Box $$path( "SILKSCREEN_2", 0.20, , [ 77.5, 170.5, 77.5, 157.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 77.5, 157.5, 98.5, 157.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 98.5, 157.5, 98.5, 170.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 98.5, 170.5, 77.5, 170.5 ]); // Bottom Left Box in the BGA $$path( "SILKSCREEN_2", 0.20, , [ 114.5, 147.5, 114.5, 139.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 114.5, 139.5, 117.5, 139.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 117.5, 139.5, 117.5, 133.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 116.6, 133.0, 116.4, 133.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 115.6, 133.0, 115.4, 133.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 114.6, 133.0, 113.8, 133.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 110.5, 148.0, 110.5, 145.9 ]); $$path( "SILKSCREEN_2", 0.20, , [ 110.5, 145.9, 110.8, 145.7 ]); $$path( "SILKSCREEN_2", 0.20, , [ 110.5, 143.7, 110.8, 143.9 ]); $$path( "SILKSCREEN_2", 0.20, , [ 110.5, 143.7, 110.5, 139.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 110.5, 139.5, 109.0, 139.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 109.0, 138.6, 108.8, 137.7 ]); $$path( "SILKSCREEN_2", 0.20, , [ 108.6, 135.2, 108.3, 134.8 ]); $$path( "SILKSCREEN_2", 0.20, , [ 108.4, 132.2, 111.9, 132.2 ]); $$path( "SILKSCREEN_2", 0.20, , [ 111.9, 132.2, 112.2, 132.5 ]); // Bottom Left Box for Ref Desig $$path( "SILKSCREEN_2", 0.20, , [ 73.5, 135.5, 73.5, 122.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 73.5, 122.5, 67.0, 122.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 67.0, 122.5, 67.0, 111.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 67.0, 111.0, 80.4, 111.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 80.4, 111.0, 80.4, 126.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 80.4, 126.5, 77.0, 126.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 77.0, 126.5, 77.0, 135.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 77.0, 135.5, 73.5, 135.5 ]); // Bottom Left Witness $$path( "SILKSCREEN_2", 0.20, , [ 77.0, 130.5, 92.5, 130.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 92.5, 130.5, 95.1, 131.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 59.7, 97.0, 82.7, 97.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 76.5, 97.0, 76.5, 82.9 ]); $$path( "SILKSCREEN_2", 0.20, , [ 76.5, 82.9, 78.5, 80.9 ]); $$path( "SILKSCREEN_2", 0.20, , [ 78.5, 80.9, 84.0, 80.9 ]); $$path( "SILKSCREEN_2", 0.20, , [ 165.5, 39.5, 165.5, 40.3 ]); $$path( "SILKSCREEN_2", 0.20, , [ 156.5, 39.5, 165.5, 39.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 156.5, 40.3, 156.5, 39.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 156.5, 47.5, 156.5, 42.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 156.5, 47.5, 158.4, 47.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 165.5, 47.5, 161.2, 47.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 165.5, 47.5, 165.5, 42.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 165.5, 47.5, 168.5, 51.3 ]); $$path( "SILKSCREEN_2", 0.20, , [ 168.5, 51.3, 180.7, 51.3 ]); $$path( "SILKSCREEN_2", 0.20, , [ 180.7, 51.3, 180.7, 54.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 175.7, 54.0, 185.7, 54.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 175.7, 54.0, 173.2, 57.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 185.7, 54.0, 188.2, 57.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 173.2, 65.0, 173.2, 57.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 188.2, 65.0, 188.2, 57.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 161.4, 51.9, 161.4, 50.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 58.0, 210.6, 73.5, 210.6 ]); $$path( "SILKSCREEN_2", 0.20, , [ 58.0, 210.6, 58.0, 211.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 60.0, 210.6, 60.0, 211.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 63.5, 210.6, 63.5, 211.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 68.9, 210.2, 68.9, 210.6 ]); $$path( "SILKSCREEN_2", 0.20, , [ 71.2, 210.2, 71.2, 210.6 ]); $$path( "SILKSCREEN_2", 0.20, , [ 73.5, 210.2, 73.5, 210.6 ]); $$path( "SILKSCREEN_2", 0.20, , [ 64.4, 216.5, 67.8, 216.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 41.1, 64.2, 41.1, 68.3 ]); $$path( "SILKSCREEN_2", 0.20, , [ 41.1, 68.3, 42.7, 69.9 ]); $$path( "SILKSCREEN_2", 0.20, , [ 42.7, 69.9, 46.8, 69.9 ]); $$path( "SILKSCREEN_2", 0.20, , [ 46.8, 69.9, 47.5, 70.6 ]); $$path( "SILKSCREEN_2", 0.20, , [ 47.5, 70.6, 47.5, 73.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 47.5, 70.6, 49.3, 70.6 ]); $$path( "SILKSCREEN_2", 0.20, , [ 25.0, 85.4, 25.0, 81.8 ]); $$path( "SILKSCREEN_2", 0.20, , [ 25.0, 82.5, 36.0, 82.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 36.0, 82.5, 36.0, 83.7 ]); $$path( "SILKSCREEN_2", 0.20, , [ 36.0, 83.3, 38.6, 83.3 ]); $$path( "SILKSCREEN_2", 0.20, , [ 36.4, 53.2, 36.4, 51.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 40.0, 95.0, 40.0, 107.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 40.0, 107.0, 55.7, 107.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 55.7, 107.0, 55.7, 100.3 ]); $$path( "SILKSCREEN_2", 0.20, , [ 55.7, 100.3, 52.0, 100.3 ]); $$path( "SILKSCREEN_2", 0.20, , [ 52.0, 100.3, 52.0, 95.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 90.2, 107.0, 90.2, 106.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 90.2, 106.0, 98.0, 106.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 136.2, 82.2, 156.6, 82.2 ]); $$path( "SILKSCREEN_2", 0.20, , [ 136.0, 80.9, 146.4, 80.9 ]); $$path( "SILKSCREEN_2", 0.20, , [ 146.4, 80.9, 146.4, 82.2 ]); $$path( "SILKSCREEN_2", 0.20, , [ 117.3, 97.0, 121.3, 97.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 129.5, 98.9, 129.5, 97.3 ]); $$path( "SILKSCREEN_2", 0.20, , [ 129.5, 97.3, 130.1, 97.3 ]); $$path( "SILKSCREEN_2", 0.20, , [ 119.0, 88.3, 120.2, 87.8 ]); $$path( "SILKSCREEN_2", 0.20, , [ 122.0, 89.5, 129.9, 88.6 ]); $$path( "SILKSCREEN_2", 0.20, , [ 122.2, 93.0, 127.9, 93.4 ]); $$path( "SILKSCREEN_2", 0.20, , [ 118.2, 93.9, 119.9, 94.8 ]); $$path( "SILKSCREEN_2", 0.20, , [ 117.5, 110.0, 121.2, 110.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 122.3, 106.0, 124.5, 106.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 171.7, 120.0, 173.7, 120.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 169.1, 122.6, 171.4, 123.4 ]); $$path( "SILKSCREEN_2", 0.20, , [ 163.9, 118.0, 166.9, 118.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 113.2, 165.6, 113.2, 159.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 115.5, 165.6, 115.5, 157.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 118.5, 165.6, 118.5, 158.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 120.5, 165.6, 120.5, 158.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 103.0, 160.3, 103.3, 159.6 ]); $$path( "SILKSCREEN_2", 0.20, , [ 101.3, 151.7, 102.3, 151.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 101.1, 148.6, 101.9, 148.1 ]); $$path( "SILKSCREEN_2", 0.20, , [ 101.9, 148.1, 103.6, 148.1 ]); $$path( "SILKSCREEN_2", 0.20, , [ 101.4, 147.0, 105.6, 147.0 ]); $$path( "SILKSCREEN_2", 0.20, , [ 105.6, 145.6, 108.3, 145.6 ]); $$path( "SILKSCREEN_2", 0.20, , [ 98.9, 139.5, 101.0, 139.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 102.8, 133.1, 103.6, 134.3 ]); $$path( "SILKSCREEN_2", 0.20, , [ 116.5, 127.0, 116.5, 131.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 116.5, 131.5, 115.1, 131.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 116.5, 129.5, 112.1, 129.5 ]); $$path( "SILKSCREEN_2", 0.20, , [ 116.5, 127.0, 117.0, 127.0 ]); // Top of board reference designator witness lines $$path( "SILKSCREEN_1", 0.20, , [ 131.0, 95.0, 132.7, 95.0 ]); $$path( "SILKSCREEN_1", 0.20, , [ 134.3, 95.0, 142.0, 95.0 ]); $$path( "SILKSCREEN_1", 0.20, , [ 131.0, 108.0, 132.7, 108.0 ]); $$path( "SILKSCREEN_1", 0.20, , [ 134.3, 108.0, 142.0, 108.0 ]); $$path( "SILKSCREEN_1", 0.20, , [ 80.0, 108.0, 85.7, 108.0 ]); $$path( "SILKSCREEN_1", 0.20, , [ 87.3, 108.0, 89.0, 108.0 ]); $$path( "SILKSCREEN_1", 0.20, , [ 77.5, 95.0, 85.7, 95.0 ]); $$path( "SILKSCREEN_1", 0.20, , [ 87.3, 95.0, 89.0, 95.0 ]); $$path( "SILKSCREEN_1", 0.20, , [ 85.5, 103.1, 89.1, 103.1 ]); $$path( "SILKSCREEN_1", 0.20, , [ 83.5, 101.5, 88.0, 101.5 ]); $$path( "SILKSCREEN_1", 0.20, , [ 88.0, 101.5, 89.6, 99.9 ]); $$path( "SILKSCREEN_1", 0.20, , [ 89.6, 99.9, 91.5, 99.9 ]); $$path( "SILKSCREEN_1", 0.20, , [ 81.8, 99.2, 83.1, 99.4 ]); $$path( "SILKSCREEN_1", 0.20, , [ 81.8, 97.2, 83.1, 97.4 ]); $$path( "SILKSCREEN_1", 0.20, , [ 80.3, 90.1, 88.9, 90.1 ]); $$path( "SILKSCREEN_1", 0.20, , [ 80.2, 80.9, 83.8, 80.9 ]); $$path( "SILKSCREEN_1", 0.20, , [ 78.2, 71.9, 86.2, 71.9 ]); $$path( "SILKSCREEN_1", 0.20, , [ 91.5, 66.4, 91.5, 65.8 ]); $$path( "SILKSCREEN_1", 0.20, , [ 91.5, 62.2, 91.5, 60.6 ]); $$path( "SILKSCREEN_1", 0.20, , [ 110.0, 84.0, 110.0, 71.2 ]); $$path( "SILKSCREEN_1", 0.20, , [ 115.8, 96.8, 115.8, 95.0 ]); $$path( "SILKSCREEN_1", 0.20, , [ 128.6, 90.1, 133.2, 90.1 ]); $$path( "SILKSCREEN_1", 0.20, , [ 125.8, 99.9, 141.2, 99.9 ]); $$path( "SILKSCREEN_1", 0.20, , [ 128.5, 103.1, 130.0, 103.1 ]); $$path( "SILKSCREEN_1", 0.20, , [ 130.0, 103.1, 132.0, 101.1 ]); $$path( "SILKSCREEN_1", 0.20, , [ 132.0, 101.1, 139.0, 101.1 ]); $$path( "SILKSCREEN_1", 0.20, , [ 139.0, 101.1, 140.0, 102.1 ]); $$path( "SILKSCREEN_1", 0.20, , [ 140.0, 102.1, 141.0, 102.1 ]); $$path( "SILKSCREEN_1", 0.20, , [ 136.2, 80.9, 139.9, 80.9 ]); $$path( "SILKSCREEN_1", 0.20, , [ 157.2, 39.0, 154.8, 34.9 ]); // End of Top Side Silk Witness Lines // Box $$path( "SILKSCREEN_1", 0.2, , [ 172.0, 57.0, 185.0, 57.0 ]); $$path( "SILKSCREEN_1", 0.2, , [ 185.0, 57.0, 185.0, 62.5 ]); $$path( "SILKSCREEN_1", 0.2, , [ 185.0, 62.5, 172.0, 62.5 ]); $$path( "SILKSCREEN_1", 0.2, , [ 172.0, 62.5, 172.0, 57.0 ]); $$path( "SILKSCREEN_1", 0.2, , [ 167.7, 54.5, 172.0, 57.0 ]); // Connector Labels // J4 $$text("SILKSCREEN_1", "Interposer", 184.5, 229.2, 2.0, @BC, 180, 0.7, 0.20, "std", "None", 0.0, 0.0, , , @noright_reading ); $$text("SILKSCREEN_1", "A", 184.5, 233.5, 2.5, @BC, 180, 0.7, 0.20, "std", "None", 0.0, 0.0, , , @noright_reading ); // J5 $$text("SILKSCREEN_1", "Interposer", 54.2, 229.0, 2.0, @BC, 180, 0.7, 0.20, "std", "None", 0.0, 0.0, , , @noright_reading ); $$text("SILKSCREEN_1", "B", 50.6, 233.5, 2.5, @BC, 180, 0.7, 0.20, "std", "None", 0.0, 0.0, , , @noright_reading ); //J2 $$text("SILKSCREEN_1", "PMT A", 230.5, 129.8, 2.0, @tr, 90, 0.7, 0.20, "std", "None", 0.0, 0.0 ); //J3 $$text("SILKSCREEN_1", "PMT B", 230.5, 105.2, 2.0, @tl, 90, 0.7, 0.20, "std", "None", 0.0, 0.0 ); // J7 $$text("SILKSCREEN_1", "Barnacle", 29.2, 5.6, 2.0, @tr, 0, 0.7, 0.20, "std", "None", 0.0, 0.0 ); // SFPs $$text("SILKSCREEN_1", "ENet SFP", 182.7, -9.5, 1.5, @cc, 90, 0.7, 0.20, "std", "None", 0.0, 0.0 ); $$text("SILKSCREEN_1", "Time SFP", 182.7, -19.4, 1.5, @cc, 90, 0.7, 0.20, "std", "None", 0.0, 0.0 ); // Example of a circle at x = 3 y = 4 diameter = 5 line width = 0.20 // $$circle( "SILKSCREEN_1", 3.00, 4.00, 5.00, 0.20 ); //large center circle, separated into arcs //$$circle( "SILKSCREEN_1", 83.55, 150, 13.4, 0.6); $$arc("SILKSCREEN_1", 90.0217, 148.266, 90.25, 150, 90.0127, 151.734, 0.6); $$arc("SILKSCREEN_1", 88.2876, 154.738, 86.9, 155.802, 85.2841, 156.472, 0.6); $$arc("SILKSCREEN_1", 81.8159, 156.472, 80.2, 155.802, 78.8124, 154.738, 0.6); $$arc("SILKSCREEN_1", 77.0783, 151.734, 76.85, 150, 77.0783, 148.266, 0.6); $$arc("SILKSCREEN_1", 78.8124, 145.262, 80.2, 144.198, 81.8159, 143.528, 0.6); $$arc("SILKSCREEN_1", 85.2841, 143.528, 86.9, 144.198, 88.2876, 145.262, 0.6); //small center circle $$circle( "SILKSCREEN_1", 83.55, 150, 3.5, 0.6); //small outer circles $$circle( "SILKSCREEN_1", 89.3524, 153.35, 3.5, 0.6); $$circle( "SILKSCREEN_1", 83.55, 156.7, 3.5, 0.6); $$circle( "SILKSCREEN_1", 77.7476, 153.35, 3.5, 0.6); $$circle( "SILKSCREEN_1", 77.7476, 146.65, 3.5, 0.6); $$circle( "SILKSCREEN_1", 83.55, 143.3, 3.5, 0.6); $$circle( "SILKSCREEN_1", 89.3524, 146.65, 3.5, 0.6); // P-ONE text $$text("SILKSCREEN_1", "P-", 81.25, 150, 1.7, @cr, 0, 1.0, 0.2, "std", "None", 0.0, 0.0 ); $$text("SILKSCREEN_1", "NE", 85.85, 150, 1.7, @cl, 0, 1.0, 0.2, "std", "None", 0.0, 0.0 ); // Kraken // Left Head $$path( "SILKSCREEN_2", 0.10, , [9.35, 44.25, 8.35, 43.75 ]); $$path( "SILKSCREEN_2", 0.10, , [8.35, 43.75, 7.35, 42.75 ]); $$path( "SILKSCREEN_2", 0.10, , [7.35, 42.75, 7.35, 41.75]); $$path( "SILKSCREEN_2", 0.10, , [7.35, 41.75, 8.10, 40.75]); $$path( "SILKSCREEN_2", 0.10, , [8.10, 40.75, 8.15, 40.00]); $$path( "SILKSCREEN_2", 0.10, , [8.15, 40.75, 7.85, 40.5]); $$path( "SILKSCREEN_2", 0.10, , [7.85, 40.50, 7.85, 40.25]); $$path( "SILKSCREEN_2", 0.10, , [7.85, 40.25, 8.15, 40.00]); // Left Tentacles $$path( "SILKSCREEN_2", 0.10, , [8.15, 40.0, 7.55, 38.45]); $$path( "SILKSCREEN_2", 0.10, , [7.55, 38.45, 5.85, 37.90]); $$path( "SILKSCREEN_2", 0.10, , [5.85, 37.90, 4.55, 39.25]); $$path( "SILKSCREEN_2", 0.10, , [4.55, 39.25, 5.15, 40.75]); $$path( "SILKSCREEN_2", 0.10, , [5.15, 40.76, 6.15, 40.75]); $$path( "SILKSCREEN_2", 0.10, , [6.15, 40.75, 6.45, 39.35]); $$path( "SILKSCREEN_2", 0.10, , [6.45, 39.35, 5.85, 38.50]); $$path( "SILKSCREEN_2", 0.10, , [5.85, 38.50, 6.55, 38.55]); $$path( "SILKSCREEN_2", 0.10, , [6.55, 38.55, 7.25, 39.55]); $$path( "SILKSCREEN_2", 0.10, , [7.25, 39.55, 7.10, 40.75]); $$path( "SILKSCREEN_2", 0.10, , [7.10, 40.75, 5.55, 41.35]); $$path( "SILKSCREEN_2", 0.10, , [5.55, 41.35, 4.55, 41.15]); $$path( "SILKSCREEN_2", 0.10, , [4.55, 41.15, 3.55, 39.75]); $$path( "SILKSCREEN_2", 0.10, , [3.55, 39.75, 3.85, 38.25]); $$path( "SILKSCREEN_2", 0.10, , [3.85, 38.25, 5.55, 36.85]); $$path( "SILKSCREEN_2", 0.10, , [5.55, 36.85, 7.15, 36.85]); $$path( "SILKSCREEN_2", 0.10, , [7.15, 36.85, 6.15, 35.25]); $$path( "SILKSCREEN_2", 0.10, , [6.15, 35.25, 5.35, 34.75]); $$path( "SILKSCREEN_2", 0.10, , [5.35, 34.75, 4.45, 35.35]); $$path( "SILKSCREEN_2", 0.10, , [4.45, 35.35, 4.45, 36.05]); $$path( "SILKSCREEN_2", 0.10, , [4.45, 36.05, 5.05, 36.45]); $$path( "SILKSCREEN_2", 0.10, , [5.05, 36.45, 5.55, 35.85]); $$path( "SILKSCREEN_2", 0.10, , [5.55, 35.85, 5.35, 35.55]); $$path( "SILKSCREEN_2", 0.10, , [5.35, 35.55, 5.85, 36.05]); $$path( "SILKSCREEN_2", 0.10, , [5.85, 36.05, 5.65, 36.55]); $$path( "SILKSCREEN_2", 0.10, , [5.65, 36.55, 4.95, 36.75]); $$path( "SILKSCREEN_2", 0.10, , [4.95, 36.75, 4.15, 36.25]); $$path( "SILKSCREEN_2", 0.10, , [4.15, 36.25, 3.95, 35.35]); $$path( "SILKSCREEN_2", 0.10, , [3.95, 35.35, 4.75, 34.25]); $$path( "SILKSCREEN_2", 0.10, , [4.75, 34.25, 6.15, 34.25]); $$path( "SILKSCREEN_2", 0.10, , [6.15, 34.25, 7.05, 34.95]); $$path( "SILKSCREEN_2", 0.10, , [7.05, 34.95, 8.35, 37.15]); $$path( "SILKSCREEN_2", 0.10, , [8.35, 37.15, 7.85, 35.25]); $$path( "SILKSCREEN_2", 0.10, , [7.85, 35.25, 7.05, 33.65]); $$path( "SILKSCREEN_2", 0.10, , [7.05, 33.65, 7.25, 32.55]); $$path( "SILKSCREEN_2", 0.10, , [7.25, 32.55, 8.35, 31.95]); $$path( "SILKSCREEN_2", 0.10, , [8.35, 31.95, 8.95, 32.35]); $$path( "SILKSCREEN_2", 0.10, , [8.95, 32.35, 9.15, 33.35]); $$path( "SILKSCREEN_2", 0.10, , [9.15, 33.35, 8.75, 32.65]); $$path( "SILKSCREEN_2", 0.10, , [8.75, 32.65, 8.05, 32.45]); $$path( "SILKSCREEN_2", 0.10, , [8.05, 32.45, 7.65, 32.85]); $$path( "SILKSCREEN_2", 0.10, , [7.65, 32.85, 7.55, 33.65]); $$path( "SILKSCREEN_2", 0.10, , [7.55, 33.65, 8.95, 36.55]); $$path( "SILKSCREEN_2", 0.10, , [8.95, 36.55, 9.05, 35.45]); $$path( "SILKSCREEN_2", 0.10, , [9.05, 35.45, 7.85, 33.65]); $$path( "SILKSCREEN_2", 0.10, , [7.85, 33.65, 7.95, 32.85]); $$path( "SILKSCREEN_2", 0.10, , [7.95, 32.85, 8.35, 33.65]); $$path( "SILKSCREEN_2", 0.10, , [8.35, 33.65, 9.35, 34.75]); // Right head $$path( "SILKSCREEN_2", 0.10, , [9.35, 44.25, 10.35, 43.75]); $$path( "SILKSCREEN_2", 0.10, , [10.35, 43.75, 11.35, 42.75]); $$path( "SILKSCREEN_2", 0.10, , [11.35, 42.75, 11.35, 41.75]); $$path( "SILKSCREEN_2", 0.10, , [11.35, 41.75, 10.60, 40.75]); $$path( "SILKSCREEN_2", 0.10, , [10.60, 40.75, 10.55, 40.00]); $$path( "SILKSCREEN_2", 0.10, , [10.55, 40.75, 10.85, 40.50]); $$path( "SILKSCREEN_2", 0.10, , [10.85, 40.50, 10.85, 40.25]); $$path( "SILKSCREEN_2", 0.10, , [10.85, 40.25, 10.55, 40.00]); // Right Tentacles $$path( "SILKSCREEN_2", 0.10, , [10.55, 40.00, 11.15, 38.45]); $$path( "SILKSCREEN_2", 0.10, , [11.15, 38.45, 12.85, 37.90]); $$path( "SILKSCREEN_2", 0.10, , [12.85, 37.90, 14.15, 39.25]); $$path( "SILKSCREEN_2", 0.10, , [14.15, 39.25, 13.55, 40.75]); $$path( "SILKSCREEN_2", 0.10, , [13.55, 40.75, 12.55, 40.75]); $$path( "SILKSCREEN_2", 0.10, , [12.55, 40.75, 12.25, 39.35]); $$path( "SILKSCREEN_2", 0.10, , [12.25, 39.35, 12.85, 38.50]); $$path( "SILKSCREEN_2", 0.10, , [12.85, 38.50, 12.15, 38.55]); $$path( "SILKSCREEN_2", 0.10, , [12.15, 38.55, 11.45, 39.55]); $$path( "SILKSCREEN_2", 0.10, , [11.45, 39.55, 11.60, 40.75]); $$path( "SILKSCREEN_2", 0.10, , [11.60, 40.75, 13.15, 41.35]); $$path( "SILKSCREEN_2", 0.10, , [13.15, 41.35, 14.15, 41.15]); $$path( "SILKSCREEN_2", 0.10, , [14.15, 41.15, 15.15, 39.75]); $$path( "SILKSCREEN_2", 0.10, , [15.15, 39.75, 14.85, 38.25]); $$path( "SILKSCREEN_2", 0.10, , [14.85, 38.25, 13.15, 36.85]); $$path( "SILKSCREEN_2", 0.10, , [13.15, 36.85, 11.55, 36.85]); $$path( "SILKSCREEN_2", 0.10, , [11.55, 36.85, 12.55, 35.25]); $$path( "SILKSCREEN_2", 0.10, , [12.55, 35.25, 13.35, 34.75]); $$path( "SILKSCREEN_2", 0.10, , [13.35, 34.75, 14.25, 35.35]); $$path( "SILKSCREEN_2", 0.10, , [14.25, 35.35, 14.25, 36.05]); $$path( "SILKSCREEN_2", 0.10, , [14.25, 36.05, 13.65, 36.45]); $$path( "SILKSCREEN_2", 0.10, , [13.65, 36.45, 13.15, 35.85]); $$path( "SILKSCREEN_2", 0.10, , [13.15, 35.85, 13.35, 35.55]); $$path( "SILKSCREEN_2", 0.10, , [13.35, 35.55, 12.85, 36.05]); $$path( "SILKSCREEN_2", 0.10, , [12.85, 36.05, 13.05, 36.55]); $$path( "SILKSCREEN_2", 0.10, , [13.05, 36.55, 13.75, 36.75]); $$path( "SILKSCREEN_2", 0.10, , [13.75, 36.75, 14.55, 36.25]); $$path( "SILKSCREEN_2", 0.10, , [14.55, 36.25, 14.75, 35.35]); $$path( "SILKSCREEN_2", 0.10, , [14.75, 35.35, 13.95, 34.25]); $$path( "SILKSCREEN_2", 0.10, , [13.95, 34.25, 12.55, 34.25]); $$path( "SILKSCREEN_2", 0.10, , [12.55, 34.25, 11.65, 34.95]); $$path( "SILKSCREEN_2", 0.10, , [11.65, 34.95, 10.35, 37.15]); $$path( "SILKSCREEN_2", 0.10, , [10.35, 37.15, 10.85, 35.25]); $$path( "SILKSCREEN_2", 0.10, , [10.85, 35.25, 11.65, 33.65]); $$path( "SILKSCREEN_2", 0.10, , [11.65, 33.65, 11.45, 32.55]); $$path( "SILKSCREEN_2", 0.10, , [11.45, 32.55, 10.35, 31.95]); $$path( "SILKSCREEN_2", 0.10, , [10.35, 31.95, 9.75, 32.35]); $$path( "SILKSCREEN_2", 0.10, , [9.75, 32.35, 9.55, 33.35]); $$path( "SILKSCREEN_2", 0.10, , [9.55, 33.35, 9.95, 32.65]); $$path( "SILKSCREEN_2", 0.10, , [9.95, 32.65, 10.65, 32.45]); $$path( "SILKSCREEN_2", 0.10, , [10.65, 32.45, 11.05, 32.85]); $$path( "SILKSCREEN_2", 0.10, , [11.05, 32.85, 11.15, 33.65]); $$path( "SILKSCREEN_2", 0.10, , [11.15, 33.65, 9.75, 36.55]); $$path( "SILKSCREEN_2", 0.10, , [9.75, 36.55, 9.65, 35.45]); $$path( "SILKSCREEN_2", 0.10, , [9.65, 35.45, 10.85, 33.65]); $$path( "SILKSCREEN_2", 0.10, , [10.85, 33.65, 10.75, 32.85]); $$path( "SILKSCREEN_2", 0.10, , [10.75, 32.85, 10.35, 33.65]); $$path( "SILKSCREEN_2", 0.10, , [10.35, 33.65, 9.35, 34.75]); // Jumper Labels // JMP1003, JMP1004 // Connect the RS-485 Bus in the Module to the Terminator (for the top module in a string) $$text("SILKSCREEN_2", "TERMINATE", 26.0, 141.5, 1.5, @tc, 0, 0.7, 0.20, "std", "None", 0.0, 0.0 ); // JMP1001, JMP1002 // Connect the RS-485 Bus in the Module to the Up going Main Cable $$text("SILKSCREEN_2", "UP CABLE", 24.2, 161.5, 1.5, @bc, 0, 0.7, 0.20, "std", "None", 0.0, 0.0 );