#
#
#           CPU I/O   Bank 2
#
#      Connections to the  U1  FPGA
#     which is a:  MPFS250T-1FCVG784E
#
#
#    Description of the pins in  Bank 2
#
#    There are  24 pins  in Bank 2
#
#
#
#  N2      MSSIO14B2      2     I/O     MSSIO
#  N3      MSSIO15B2      2     I/O     MSSIO
#  M4      MSSIO16B2      2     I/O     MSSIO
#  M5      MSSIO17B2      2     I/O     MSSIO
#  N1      MSSIO18B2      2     I/O     MSSIO
#  M1      MSSIO19B2      2     I/O     MSSIO
#  L3      MSSIO20B2      2     I/O     MSSIO
#  L4      MSSIO21B2      2     I/O     MSSIO
#  M2      MSSIO22B2      2     I/O     MSSIO
#  L2      MSSIO23B2      2     I/O     MSSIO
#  L5      MSSIO24B2      2     I/O     MSSIO
#  M6      MSSIO25B2      2     I/O     MSSIO
#  N8      MSSIO26B2      2     I/O     MSSIO
#  M7      MSSIO27B2      2     I/O     MSSIO
#  L7      MSSIO28B2      2     I/O     MSSIO
#  K8      MSSIO29B2      2     I/O     MSSIO
#  M10     MSSIO30B2      2     I/O     MSSIO
#  N9      MSSIO31B2      2     I/O     MSSIO
#  L10     MSSIO32B2      2     I/O     MSSIO
#  M9      MSSIO33B2      2     I/O     MSSIO
#  M11     MSSIO34B2      2     I/O     MSSIO
#  N11     MSSIO35B2      2     I/O     MSSIO
#  L8      MSSIO36B2      2     I/O     MSSIO
#  L9      MSSIO37B2      2     I/O     MSSIO
#



NET 'FPGA_Bank_2'    U1-N2      U1-N3      U1-M4      U1-M5      U1-N1
NET 'FPGA_Bank_2'    U1-M1      U1-L3      U1-L4      U1-M2      U1-L2
NET 'FPGA_Bank_2'    U1-L5      U1-M6      U1-N8      U1-M7      U1-L7
NET 'FPGA_Bank_2'    U1-K8      U1-M10     U1-N9      U1-L10     U1-M9
NET 'FPGA_Bank_2'    U1-M11     U1-N11     U1-L8      U1-L9