#
#
#        JTAG SPI & DEDIO   Bank 3
#
#      Connections to the  U1  FPGA
#     which is a:  MPFS250T-1FCVG784E
#
#
#    Description of the pins in  Bank 3
#
#    There are  13 pins  in Bank 3
#
#
#  J12     TMS            3       I       JTAG
#  H11     TDI            3       I       JTAG
#  J11     TDO            3       O       JTAG
#  H12     TCK            3       I       JTAG
#  J10     TRSTB          3       I       JTAG
#
#  H9      DEVRST_N       3       I       DEDIO
#
#  J8      SCK            3       I/O     DEDIO
#  J9      SS             3       I/O     DEDIO
#  H8      SDO            3       O       DEDIO
#  K10     SDI            3       I       DEDIO
#
#  H13     IO_CFG_INTF    3       I       DEDIO
#  J13     FF_EXIT_N      3       I       DEDIO
#  K12     SPI_EN  N/A    3       I       DEDIO
#



NET 'FPGA_Bank_3'    U1-J12     U1-H11     U1-J11     U1-H12     U1-J10
NET 'FPGA_Bank_3'    U1-H9      U1-J8      U1-J9      U1-H8      U1-K10
NET 'FPGA_Bank_3'    U1-H13     U1-J13     U1-K12