#
#
#           CPU SGMII   Bank 5
#
#      Connections to the  U1  FPGA
#     which is a:  MPFS250T-1FCVG784E
#
#
#    Description of the pins in  Bank 5
#
#    There are  10 pins  in Bank 5
#
#
#
#  T8      MSS_SGMII_RXN1      MSS_DDR_SGMII     5     I/O     MSS_SGMII
#  R8      MSS_SGMII_RXP1      MSS_DDR_SGMII     5     I/O     MSS_SGMII
#  T10     MSS_SGMII_TXN1      MSS_DDR_SGMII     5     I/O     MSS_SGMII
#  T9      MSS_SGMII_TXP1      MSS_DDR_SGMII     5     I/O     MSS_SGMII
#  P9      MSS_SGMII_RXN0      MSS_DDR_SGMII     5     I/O     MSS_SGMII
#  P8      MSS_SGMII_RXP0      MSS_DDR_SGMII     5     I/O     MSS_SGMII
#  R10     MSS_SGMII_TXN0      MSS_DDR_SGMII     5     I/O     MSS_SGMII
#  P10     MSS_SGMII_TXP0      MSS_DDR_SGMII     5     I/O     MSS_SGMII
#  R11     MSS_REFCLK_IN_N     MSS_DDR_SGMII     5     I/O     MSS_REFCLK
#  P11     MSS_REFCLK_IN_P     MSS_DDR_SGMII     5     I/O     MSS_REFCLK
#


NET 'FPGA_Bank_5'    U1-T8      U1-R8      U1-T10     U1-T9      U1-P9
NET 'FPGA_Bank_5'    U1-P8      U1-R10     U1-P10     U1-R11     U1-P11