# # # CPU HSIO DRR Bank 6 # # Connections to the U1 FPGA # which is a: MPFS250T-1FCVG784E # # # Description of the pins in Bank 6 # # There are 88 pins in Bank 6 # # # AH4 MSS_DDR_DM3 MSS_DDR_DATA3 6 I/O MSS_DDR # AG4 MSS_DDR_DQ31 MSS_DDR_DATA3 6 I/O MSS_DDR # AG5 MSS_DDR_DQ30 MSS_DDR_DATA3 6 I/O MSS_DDR # AH3 MSS_DDR_DQ29 MSS_DDR_DATA3 6 I/O MSS_DDR # AH2 MSS_DDR_DQ28 MSS_DDR_DATA3 6 I/O MSS_DDR # AG2 MSS_DDR_DQS_N3 MSS_DDR_DATA3 6 I/O MSS_DDR # AF2 MSS_DDR_DQS_P3 MSS_DDR_DATA3 6 I/O MSS_DDR # AG1 MSS_DDR_DQ27 MSS_DDR_DATA3 6 I/O MSS_DDR # AF1 MSS_DDR_DQ26 MSS_DDR_DATA3 6 I/O MSS_DDR # AF3 MSS_DDR_DQ25 MSS_DDR_DATA3 6 I/O MSS_DDR # AF4 MSS_DDR_DQ24 MSS_DDR_DATA3 6 I/O MSS_DDR # AE1 MSS_DDR_DM2 MSS_DDR_DATA2 6 I/O MSS_DDR # AD1 MSS_DDR_DQ23 MSS_DDR_DATA2 6 I/O MSS_DDR # AE2 MSS_DDR_DQ22 MSS_DDR_DATA2 6 I/O MSS_DDR # AE6 MSS_DDR_DQ21 MSS_DDR_DATA2 6 I/O MSS_DDR # AF5 MSS_DDR_DQ20 MSS_DDR_DATA2 6 I/O MSS_DDR # AE3 MSS_DDR_DQS_N2 MSS_DDR_DATA2 6 I/O MSS_DDR # AD3 MSS_DDR_DQS_P2 MSS_DDR_DATA2 6 I/O MSS_DDR # AD4 MSS_DDR_DQ19 MSS_DDR_DATA2 6 I/O MSS_DDR # AD5 MSS_DDR_DQ18 MSS_DDR_DATA2 6 I/O MSS_DDR # AE5 MSS_DDR_DQ17 MSS_DDR_DATA2 6 I/O MSS_DDR # AD6 MSS_DDR_DQ16 MSS_DDR_DATA2 6 I/O MSS_DDR # AC9 MSS_DDR_DM1 MSS_DDR_DATA1 6 I/O MSS_DDR # AB9 MSS_DDR_DQ15 MSS_DDR_DATA1 6 I/O MSS_DDR # AA9 MSS_DDR_DQ14 MSS_DDR_DATA1 6 I/O MSS_DDR # AC8 MSS_DDR_DQ13 MSS_DDR_DATA1 6 I/O MSS_DDR # AB6 MSS_DDR_DQ12 MSS_DDR_DATA1 6 I/O MSS_DDR # AA8 MSS_DDR_DQS_N1 MSS_DDR_DATA1 6 I/O MSS_DDR # AA7 MSS_DDR_DQS_P1 MSS_DDR_DATA1 6 I/O MSS_DDR # AA5 MSS_DDR_DQ11 MSS_DDR_DATA1 6 I/O MSS_DDR # AC7 MSS_DDR_DQ10 MSS_DDR_DATA1 6 I/O MSS_DDR # AC6 MSS_DDR_DQ9 MSS_DDR_DATA1 6 I/O MSS_DDR # AB7 MSS_DDR_DQ8 MSS_DDR_DATA1 6 I/O MSS_DDR # AC3 MSS_DDR_DM0 MSS_DDR_DATA0 6 I/O MSS_DDR # AC2 MSS_DDR_DQ7 MSS_DDR_DATA0 6 I/O MSS_DDR # AC1 MSS_DDR_DQ6 MSS_DDR_DATA0 6 I/O MSS_DDR # AC4 MSS_DDR_DQ5 MSS_DDR_DATA0 6 I/O MSS_DDR # AA2 MSS_DDR_DQ4 MSS_DDR_DATA0 6 I/O MSS_DDR # AB1 MSS_DDR_DQS_N0 MSS_DDR_DATA0 6 I/O MSS_DDR # AB2 MSS_DDR_DQS_P0 MSS_DDR_DATA0 6 I/O MSS_DDR # AA3 MSS_DDR_DQ3 MSS_DDR_DATA0 6 I/O MSS_DDR # AA4 MSS_DDR_DQ2 MSS_DDR_DATA0 6 I/O MSS_DDR # AB4 MSS_DDR_DQ1 MSS_DDR_DATA0 6 I/O MSS_DDR # AB5 MSS_DDR_DQ0 MSS_DDR_DATA0 6 I/O MSS_DDR # Y10 MSS_DDR_VREF_IN N/A 6 I MSS_DDR_VREF # W11 MSS_DDR_DM4 MSS_DDR_ECC 6 I/O MSS_DDR # Y8 MSS_DDR_DQS_N4 MSS_DDR_ECC 6 I/O MSS_DDR # Y7 MSS_DDR_DQS_P4 MSS_DDR_ECC 6 I/O MSS_DDR # Y11 MSS_DDR_DQ35 MSS_DDR_ECC 6 I/O MSS_DDR # AA10 MSS_DDR_DQ34 MSS_DDR_ECC 6 I/O MSS_DDR # AB11 MSS_DDR_DQ33 MSS_DDR_ECC 6 I/O MSS_DDR # AB10 MSS_DDR_DQ32 MSS_DDR_ECC 6 I/O MSS_DDR # Y5 MSS_DDR_A9 MSS_DDR_ADDCMD0 6 I/O MSS_DDR # W6 MSS_DDR_A8 MSS_DDR_ADDCMD0 6 I/O MSS_DDR # Y6 MSS_DDR_A7 MSS_DDR_ADDCMD0 6 I/O MSS_DDR # W5 MSS_DDR_A6 MSS_DDR_ADDCMD0 6 I/O MSS_DDR # W4 MSS_DDR_A5 MSS_DDR_ADDCMD0 6 I/O MSS_DDR # W3 MSS_DDR_A4 MSS_DDR_ADDCMD0 6 I/O MSS_DDR # W1 MSS_DDR_A3 MSS_DDR_ADDCMD0 6 I/O MSS_DDR # Y1 MSS_DDR_A2 MSS_DDR_ADDCMD0 6 I/O MSS_DDR # V2 MSS_DDR_A1 MSS_DDR_ADDCMD0 6 I/O MSS_DDR # V1 MSS_DDR_A0 MSS_DDR_ADDCMD0 6 I/O MSS_DDR # Y2 MSS_DDR_CK_N0 MSS_DDR_ADDCMD0 6 I/O MSS_DDR # # Y3 MSS_DDR_CK0/ # DDR_PLL0_OUT0 MSS_DDR_ADDCMD0 6 I/O MSS_DDR # # W10 MSS_DDR_BA1 MSS_DDR_ADDCMD1 6 I/O MSS_DDR # U11 MSS_DDR_BA0 MSS_DDR_ADDCMD1 6 I/O MSS_DDR # V11 MSS_DDR3_WE_N MSS_DDR_ADDCMD1 6 I/O MSS_DDR # U10 MSS_DDR_A16 MSS_DDR_ADDCMD1 6 I/O MSS_DDR # U7 MSS_DDR_A15 MSS_DDR_ADDCMD1 6 I/O MSS_DDR # T7 MSS_DDR_A14 MSS_DDR_ADDCMD1 6 I/O MSS_DDR # V8 MSS_DDR_A13 MSS_DDR_ADDCMD1 6 I/O MSS_DDR # V7 MSS_DDR_A12 MSS_DDR_ADDCMD1 6 I/O MSS_DDR # U9 MSS_DDR_A11 MSS_DDR_ADDCMD1 6 I/O MSS_DDR # V9 MSS_DDR_A10 MSS_DDR_ADDCMD1 6 I/O MSS_DDR # W9 MSS_DDR_CK_N1 MSS_DDR_ADDCMD1 6 I/O MSS_DDR # # W8 MSS_DDR_CK1/ # DDR_PLL0_OUT0 MSS_DDR_ADDCMD1 6 I/O MSS_DDR # # V6 MSS_DDR_ALERT_N MSS_DDR_ADDCMD2 6 I/O MSS_DDR # U6 MSS_DDR_PARITY MSS_DDR_ADDCMD2 6 I/O MSS_DDR # U5 MSS_DDR_ACT_N MSS_DDR_ADDCMD2 6 I/O MSS_DDR # T5 MSS_DDR_ODT1 MSS_DDR_ADDCMD2 6 I/O MSS_DDR # T2 MSS_DDR_CKE1 MSS_DDR_ADDCMD2 6 I/O MSS_DDR # T3 MSS_DDR_CS1 MSS_DDR_ADDCMD2 6 I/O MSS_DDR # V3 MSS_DDR_ODT0 MSS_DDR_ADDCMD2 6 I/O MSS_DDR # V4 MSS_DDR_CKE0 MSS_DDR_ADDCMD2 6 I/O MSS_DDR # T4 MSS_DDR_CS0 MSS_DDR_ADDCMD2 6 I/O MSS_DDR # U4 MSS_DDR_BG1 MSS_DDR_ADDCMD2 6 I/O MSS_DDR # U2 MSS_DDR_BG0 MSS_DDR_ADDCMD2 6 I/O MSS_DDR # # U1 MSS_DDR_RAM_RST_N/ # DDR_PLL0_OUT1 MSS_DDR_ADDCMD2 6 I/O MSS_DDR # # NET 'FPGA_Bank_6' U1-AH4 U1-AG4 U1-AG5 U1-AH3 U1-AH2 NET 'FPGA_Bank_6' U1-AG2 U1-AF2 U1-AG1 U1-AF1 U1-AF3 NET 'FPGA_Bank_6' U1-AF4 U1-AE1 U1-AD1 U1-AE2 U1-AE6 NET 'FPGA_Bank_6' U1-AF5 U1-AE3 U1-AD3 U1-AD4 U1-AD5 NET 'FPGA_Bank_6' U1-AE5 U1-AD6 U1-AC9 U1-AB9 U1-AA9 NET 'FPGA_Bank_6' U1-AC8 U1-AB6 U1-AA8 U1-AA7 U1-AA5 NET 'FPGA_Bank_6' U1-AC7 U1-AC6 U1-AB7 U1-AC3 U1-AC2 NET 'FPGA_Bank_6' U1-AC1 U1-AC4 U1-AA2 U1-AB1 U1-AB2 NET 'FPGA_Bank_6' U1-AA3 U1-AA4 U1-AB4 U1-AB5 U1-Y10 NET 'FPGA_Bank_6' U1-W11 U1-Y8 U1-Y7 U1-Y11 U1-AA10 NET 'FPGA_Bank_6' U1-AB11 U1-AB10 U1-Y5 U1-W6 U1-Y6 NET 'FPGA_Bank_6' U1-W5 U1-W4 U1-W3 U1-W1 U1-Y1 NET 'FPGA_Bank_6' U1-V2 U1-V1 U1-Y2 U1-Y3 U1-W10 NET 'FPGA_Bank_6' U1-U11 U1-V11 U1-U10 U1-U7 U1-T7 NET 'FPGA_Bank_6' U1-V8 U1-V7 U1-U9 U1-V9 U1-W9 NET 'FPGA_Bank_6' U1-W8 U1-V6 U1-U6 U1-U5 U1-T5 NET 'FPGA_Bank_6' U1-T2 U1-T3 U1-V3 U1-V4 U1-T4 NET 'FPGA_Bank_6' U1-U4 U1-U2 U1-U1