#
#
#           FPGA GPIO   Bank 7
#
#      Connections to the  U1  FPGA
#     which is a:  MPFS250T-1FCVG784E
#
#
#    Description of the pins in  Bank 7
#
#    There are  24 pins  in Bank 7
#
#
#
#  K5      GPIO138NB7               DDR_W_4     I/O     GPIO
#  K6      GPIO138PB7               DDR_W_4     I/O     GPIO
#  K3      GPIO139NB7               DDR_W_4     I/O     GPIO
#  J3      GPIO139PB7/CLKIN_W_7     DDR_W_4     I/O     GPIO
#  J4      GPIO140NB7               DDR_W_4     I/O     GPIO
#  J5      GPIO140PB7/CLKIN_W_6     DDR_W_4     I/O     GPIO
#  H4      GPIO141NB7/DQS           DDR_W_4     I/O     GPIO
#  H3      GPIO141PB7/DQS           DDR_W_4     I/O     GPIO
#  J6      GPIO142NB7               DDR_W_4     I/O     GPIO
#  K7      GPIO142PB7/CLKIN_W_5     DDR_W_4     I/O     GPIO
#  H6      GPIO143NB7               DDR_W_4     I/O     GPIO
#  H7      GPIO143PB7/CLKIN_W_4     DDR_W_4     I/O     GPIO
#  K2      GPIO162NB7               DDR_W_0     I/O     GPIO
#
#  K1      GPIO162PB7/CLKIN_W_3/    DDR_W_0     I/O     GPIO
#          CCC_SW_CLKIN_W_3
#
#  J1      GPIO163NB7               DDR_W_0     I/O     GPIO
#
#  H1      GPIO163PB7/CLKIN_W_2/    DDR_W_0     I/O     GPIO
#          CCC_SW_CLKIN_W_2/
#          CCC_SW_PLL0_OUT0
#
#  F3      GPIO164NB7               DDR_W_0     I/O     GPIO
#
#  F4      GPIO164PB7/CLKIN_W_1/    DDR_W_0     I/O     GPIO
#          CCC_SW_CLKIN_W_1
#
#  H2      GPIO165NB7/DQS           DDR_W_0     I/O     GPIO
#
#  G2      GPIO165PB7/DQS/          DDR_W_0     I/O     GPIO
#          CCC_SW_PLL0_OUT0
#
#  G1      GPIO166NB7               DDR_W_0     I/O     GPIO
#  F2      GPIO166PB7               DDR_W_0     I/O     GPIO
#  G4      GPIO167NB7               DDR_W_0     I/O     GPIO
#
#  G5      GPIO167PB7/CLKIN_W_0/    DDR_W_0     I/O     GPIO
#          CCC_SW_CLKIN_W_0
#




NET 'FPGA_Bank_7'    U1-K5      U1-K6      U1-K3      U1-J3      U1-J4
NET 'FPGA_Bank_7'    U1-J5      U1-H4      U1-H3      U1-J6      U1-K7
NET 'FPGA_Bank_7'    U1-H6      U1-H7      U1-K2      U1-K1      U1-J1
NET 'FPGA_Bank_7'    U1-H1      U1-F3      U1-F4      U1-H2      U1-G2
NET 'FPGA_Bank_7'    U1-G1      U1-F2      U1-G4      U1-G5