# # Access Connector J12 # ------------------------- # # and Miscellaneous UART Connections # ------------------------------------ # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 14-Dec-2022 # Current Rev. 18-Dec-2023 # # # This net list holds the connections to the J12 # Access Connector Pins 11:40 and miscellaneous # UART connections. # # # Additional connections to the Access Connector are # made in the net list file: jtag_for_fpga_cpu_nets.txt # # # Additional UART connections are made in the following # net list files: # # barnacle_interface_nets.txt CPU MMUART #2 3V3 # # interposer_all_other_nets.txt CPU MMUART #3 1V8 Interposer #1 # CPU MMUART #4 1V8 Interposer #2 # # rescue_rs485_nets.txt Rescue UART #0 to the RS-485 Cable # Rescue UART #1 to the Access Header # Rescue UART #2 to the FPGA/CPU MMUART #1 # Rescue UART #3 to the TOMCat via LVDS # Rescue UART #4 to the Not Used # # # All of the actual UART connections to the FPGA/CPU are # made in the net list file: # # fpga_cpu_floating_connection_nets.txt # # # The components for the Access Connector # are in the range 1401 to 1449. # # # # Access Connector J12 Pinout # ------------------------------- # # # 1. JTAG_TCLK 2. GROUND # 3. JTAG_TDO 4. NO_Connection # 5. JTAG_TMS 6. JTAG_3V3 # 7. NO_Connection 8. JTAG_TRST # 9. JTAG_TDI 10. GROUND # # 11. GROUND 12. GROUND # 13. CPU MMUART #0 Tx 3V3 14. CPU MMUART #0 Rx 3V3 # 15. GROUND 16. GROUND # 17. Rescue UART #1 Tx 3V3 18. Rescue UART #1 Rx 3V3 # 19. GROUND 20. GROUND # # 21. Access_Signal_1 22. GROUND # 23. Access_Signal_2 24. GROUND # 25. Access_Signal_3 26. GROUND # 27. Access_Signal_4 28. GROUND # 29. Access_Signal_5 30. GROUND # # 31. GROUND 32. GROUND # 33. Diff_Signal_1_Dir 34. Diff_Signal_1_Cmp # 35. GROUND 36. GROUND # 37. Diff_Signal_2_Dir 38. Diff_Signal_2_Cmp # 39. GROUND 40. GROUND # # # # Connect the FPGA/CPU MMUART #1 with the Rescue UART #2 # ----------------------------------------------------------- # # Connect these Tx to Rx via 499 Ohm resistors to help # limit the current flow when one device is powered up # and the other is not yet driving it output banks. # NET 'RESCUE_PIO_0_20_UART_2_Tx' R1411-1 # ER UART 2 Tx Data to NET 'CPU_UART_1_Rx_from_ER_uProc' R1411-2 # FPGA/CPU MMUART 1 Rx NET 'RESCUE_PIO_0_19_UART_2_Rx' R1412-1 # ER UART 2 Rx Data from NET 'CPU_UART_1_Tx__to__ER_uProc' R1412-2 # FPGA/CPU MMUART 1 Tx # # Connect pins 11 through 40 of the J12 Access Connector # -------------------------------------------------------------- # # NET 'GROUND' J12-11 J12-12 NET 'CPU_UART_0_Tx__to__Access' J12-13 # CPU UART 0 Tx Data to Access Connector NET 'CPU_UART_0_Rx_from_Access' J12-14 # CPU UART 0 Rx Data from Access Connector NET 'GROUND' J12-15 J12-16 NET 'RESCUE_PIO_0_7_UART_1_Tx' J12-17 # ER UART 1 Tx Data to Header Pin NET 'RESCUE_PIO_0_6_UART_1_Rx' J12-18 # ER UART 1 Rx Data from Header Pin NET 'GROUND' J12-19 J12-20 NET 'Access_Signal_1' J12-21 # Access Connector FPGA Signal #1 NET 'GROUND' J12-22 NET 'Access_Signal_2' J12-23 # Access Connector FPGA Signal #2 NET 'GROUND' J12-24 NET 'Access_Signal_3' J12-25 # Access Connector FPGA Signal #3 NET 'GROUND' J12-26 NET 'Access_Signal_4' J12-27 # Access Connector FPGA Signal #4 NET 'GROUND' J12-28 NET 'Access_Signal_5' J12-29 # Access Connector FPGA Signal #5 NET 'GROUND' J12-30 NET 'GROUND' J12-31 J12-32 NET 'Access_Diff_Pair_1_Dir' J12-33 # Access Connector FPGA Differential Pair #1 DIR NET 'Access_Diff_Pair_1_Cmp' J12-34 # Access Connector FPGA Differential Pair #1 CMP NET 'GROUND' J12-35 J12-36 NET 'Access_Diff_Pair_2_Dir' J12-37 # Access Connector FPGA Differential Pair #2 DIR NET 'Access_Diff_Pair_2_Cmp' J12-38 # Access Connector FPGA Differential Pair #2 CMP NET 'GROUND' J12-39 J12-40 # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # These are 3V3 signals: CPU MMUART #0 Data to/from Access Connector # ------------------------------------------------------------------------ # # NET 'CPU_UART_0_Tx__to__Access' # CPU UART 0 Tx Data to Access Connector # NET 'CPU_UART_0_Rx_from_Access' # CPU UART 0 Rx Data from Access Connector # # # These are 3V3 signals: CPU MMUART #1 Data to/from Emergency Rescue uProcessor # ----------------------------------------------------------------------------------- # # NET 'CPU_UART_1_Tx__to__ER_uProc' # CPU UART 1 Tx Data to Emergency Rescue uProc # NET 'CPU_UART_1_Rx_from_ER_uProc' # CPU UART 1 Rx Data from Emergency Rescue uProc # # # # These are 3V3 signals: FPGA/CPU <--> Access Connector Single Ended Signals # --------------------------------------------------------------------------------- # # NET 'Access_Signal_1' # Access Connector FPGA Signal #1 # NET 'Access_Signal_2' # Access Connector FPGA Signal #2 # NET 'Access_Signal_3' # Access Connector FPGA Signal #3 # NET 'Access_Signal_4' # Access Connector FPGA Signal #4 # NET 'Access_Signal_5' # Access Connector FPGA Signal #5 # # # # Both of these are Differential signals, e.g. LVDS: # # FPGA/CPU <--> Access Connector Differential Pairs # ---------------------------------------------------------------------------------------- # # NET 'Access_Diff_Pair_1_Dir' # Access Connector FPGA Differential Pair #1 DIR # NET 'Access_Diff_Pair_1_Cmp' # Access Connector FPGA Differential Pair #1 CMP # # NET 'Access_Diff_Pair_2_Dir' # Access Connector FPGA Differential Pair #2 DIR # NET 'Access_Diff_Pair_2_Cmp' # Access Connector FPGA Differential Pair #2 CMP #