# # BARNACLE Interface # ---------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 6-Dec-2022 # Current Rev. 27-Dec-2023 # # # This net list holds the Barnacle Interface # # # The components for the Barnacle Interface # are in the range 1551 to 1599. # # # NOTE: In another net list file the Emergency Rescue # functions use 1 section of the U1551 hex inverter # that is officially part of the Barnacle Interface circuit. # # # Barnacle Interface UART Data Buffers and their FPGA/CPU Connection: # -------------------------------------------------------------------------- # NET 'CPU_UART_2_Tx__to__Barnacle' R1551-1 # DK CPU UART Tx Data to Terminator NET 'Tx_to_Barnacle_Term_Buf' R1551-2 U1551-3 # DK CPU UART Tx Data to Data Buffer NET 'CPU_UART_Tx_to_Barnacle_B' U1551-4 U1551-5 # Inverted NET 'Data_to_Barnacle_Buf_Term' U1551-6 R1552-1 # Tx Data to the DK Tx Terminator NET 'DK_Tx_Data_to_Barnacle' R1552-2 J7-5 # Tx Data to the Barnacle Connector NET 'DK_Rx_Data_from_Barnacle' J7-7 U1551-11 # Rx Data from the Barnacle Connector NET 'DK_Rx_Data_from_Barnacle_B' U1551-10 U1551-9 # Inverted NET 'DK_Rx_Data_to_Terminator' U1551-8 R1553-1 # Rx Data from the Barnacle to Term NET 'CPU_UART_2_Rx_from_Barnacle' R1553-2 # Rx Data from the Barnacle via Buf # and Term to the DK's CPU UART # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are 3V3 signals: Barnacle UART Data # --------------------------------------------------------------------------- # # NET 'CPU_UART_2_Tx__to__Barnacle' # DK CPU UART 2 Tx Data to Barnacle # NET 'CPU_UART_2_Rx_from_Barnacle' # DK CPU UART 2 Rx Data from Barnacle # # # # # Barnacle Interface Master_Reset_B & CONTROL Signals to the Barnacle: # ----------------------------------------------------------------------------- # NET 'Barnacle_Master_Reset_B' J7-3 # Master_Reset_B to the Barnacle NET 'DK_Control_1_to_Barnacle' J7-9 # Control Signal #1 from DK to the Barnacle NET 'DK_Control_2_to_Barnacle' J7-11 # Control Signal #2 from DK to the Barnacle # These 3 Barnacle Control Signals come from the Hardwired # Reset Circuits where they are all forced LOW during Power Up. # # Barnacle Interface Power Feed and Ground Pins: # ----------------------------------------------------- # NET 'BULK_5V0' L1551-2 C1551-2 # Bulk_5V0 Power to Filter NET 'GROUND' C1551-1 # Ground Filter Input Capacitor NET 'BARNACLE_5V0' L1551-1 C1552-2 # Filtered Barnacle 5V0 Power NET 'GROUND' C1552-1 # Ground the Bypass Capacitor NET 'BARNACLE_5V0' J7-1 J7-13 # Filtered 5V0 to the Barnacle Connector NET 'GROUND' J7-2 J7-4 J7-6 # Grounds to the Barnacle Connector NET 'GROUND' J7-8 J7-10 J7-12 NET 'GROUND' J7-14 # # 3.3 Volt Power and Grounds to the UART Data Buffers: # --------------------------------------------------------- # NET 'BULK_3V3' C1553-1 C1554-1 # UART Data Buffer 3V3 Bypass Caps NET 'GROUND' C1553-2 C1554-2 # Ground Side of Bypass Caps NET 'BULK_3V3' U1551-14 # 3V3 Power to UART Data Buffer chip NET 'GROUND' U1551-7 # Ground to UART Data Buffer chip NET 'GROUND' U1551-13 # Tie Down the unused input of the # U1551 hex inverter