# # FPGA Boot Memory FPGA Bank #3 # -=====---------------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 27-Nov-2022 # Current Rev. 30-Nov-2023 # # # This net list holds the: # # FPGA Boot Memory and its connections to the DK FPGA Bank #3 # ------------------------------------------------------------- # # # NOTE: This file also holds the nets for some: # # Bank #3 Pull-Up Resistors for Default Operation # --------------------------------------------------- # # # The components for the FPGA Boot Memory # are in the range 1251 to 1299. # # The components for the Bank #3 Default Operation Pull-Up Resistors # are from a separate Comps file: R1351, R1352, R1353. # # # FPGA Boot Memory to/from Multiplexer: # -===--------------------------------------- # NET 'FPGA_Boot_Mem_SELECT_B' U1251-7 U1252-3 U1252-18 # Select_B from Mux. NET 'FPGA_Boot_Mem_DQ1' U1251-8 U1252-15 U1252-4 # MISO / DQ1 to Mux. NET 'FPGA_Boot_Mem_DQ0' U1251-15 U1252-7 U1252-14 # MOSI / DQ0 from Mux. NET 'FPGA_Boot_Mem_CLOCK' U1251-16 U1252-9 U1252-12 # CLOCK / SCK from Mux. # # Multiplexer to/from DK FPGA Bank #3: # ------------------------------------------ # NET 'FPGA_Bank_3_SPI_SS' U1-J9 U1252-2 # FPGA SPI SEL_B to FPGA Boot Mem Mux. NET 'FPGA_Boot_Mux_FPGA_MISO' U1252-16 R1254-2 # SPI MISO from Mux to Term Res NET 'FPGA_Bank_3_SPI_MISO' U1-K10 R1254-1 # Term Res to FPGA SPI MISO NET 'FPGA_Bank_3_SPI_MOSI' U1-H8 R1255-1 # FPGA SPI MOSI to Term Res NET 'FPGA_Boot_Mux_FPGA_MOSI' U1252-6 R1255-2 # Term Res to FPGA Boot Mem Mux. NET 'FPGA_Bank_3_SPI_SCK' U1-J8 R1256-1 # FPGA SPI SCK to Term Res NET 'FPGA_Boot_Mux_FPGA_SCK' U1252-8 R1256-2 # Term Res to FPGA Boot Mem Mux. # # Multiplexer to/from ER uProcessor: # --------------------------------------- # NET 'RESCUE_PIO_0_21_SPI_SSEL0' U1252-17 # ER uProc SPI SEL_B to FPGA Boot Mem Mux. NET 'FPGA_Boot_Mux_ER_MISO' U1252-5 R1251-2 # SPI MISO from Mux to Term Res NET 'RESCUE_PIO_0_22_SPI_MISO' R1251-1 # Term Res to ER uProc SPI MISO NET 'RESCUE_PIO_0_23_SPI_MOSI' R1252-1 # ER uProc SPI MOSI to Term Res NET 'FPGA_Boot_Mux_ER_MOSI' U1252-13 R1252-2 # Term Res to FPGA Boot Mem Mux. NET 'RESCUE_PIO_0_14_SPI_SCK' R1253-1 # ER uProc SPI SCK to Term Res NET 'FPGA_Boot_Mux_ER_SCK' U1252-11 R1253-2 # Term Res to FPGA Boot Mem Mux. NET 'ER_Controls_Boot_SPI' U1252-1 U1252-19 # Control Signal from ER uProcessor # HW Logic HI ---> ER Takes Control # of the FPGA Boot Memory SPI Bus # # Pull-Up & Pull-Down Resistors for FPGA Boot Memory Clock Signal: # -------------------------------------------------------------------- # NET 'FPGA_Boot_Mem_CLOCK' R1261-2 R1262-2 # FPGA Boot Mem CLOCK / SCLK NET 'BULK_3V3' R1261-1 # Pull-Up 3V3 Source NET 'GROUND' R1262-1 # Pull-Down Anchor # # Pull-Up Resistors on the FPGA Boot Memory: # ----------------------------====-------------- # NET 'FPGA_Boot_Mem_DQ3_HOLD_B' U1251-1 R1257-2 # FPGA Boot Memory DQ3/HOLD_B pin NET 'FPGA_Boot_Mem_RESET_B' U1251-3 R1258-2 # FPGA Boot Memory RESET_B pin NET 'FPGA_Boot_Mem_DQ2_W_B' U1251-9 R1259-1 # FPGA Boot Memory DQ2/W_B pin NET 'BULK_3V3' R1257-1 R1258-1 R1259-2 # Pull-Up 3V3 Source NET 'FPGA_Boot_Mem_SELECT_B' R1260-2 # FPGA Boot Memory SELECT_B pin NET 'BULK_3V3' R1260-1 # Pull-Up 3V3 Source # # 3.3 Volt Power and Grounds to the FPGA Boot Memory & Multiplexer Chip: # ------------------------------------===------------------------------------ # NET 'BULK_3V3' C1251-1 C1252-2 C1253-1 C1254-2 # 3V3 Bypass Caps NET 'GROUND' C1251-2 C1252-1 C1253-2 C1254-1 # Ground Side of Bypass Caps NET 'BULK_3V3' U1251-2 U1252-20 # 3V3 Power to the FPGA Boot & Mux NET 'GROUND' U1251-10 U1252-10 # Ground to the FPGA Boot & Mux # # FPGA Boot Memory No_Connect Pins: # -====------------------------------- # NET 'NO_CONN_FPGA_Boot_Mem_Pin_4' U1251-4 # No Conn U1201 Pin 4 NET 'NO_CONN_FPGA_Boot_Mem_Pin_5' U1251-5 # No Conn U1201 Pin 5 NET 'NO_CONN_FPGA_Boot_Mem_Pin_6' U1251-6 # No Conn U1201 Pin 6 NET 'NO_CONN_FPGA_Boot_Mem_Pin_11' U1251-11 # No Conn U1201 Pin 11 NET 'NO_CONN_FPGA_Boot_Mem_Pin_12' U1251-12 # No Conn U1201 Pin 12 NET 'NO_CONN_FPGA_Boot_Mem_Pin_13' U1251-13 # No Conn U1201 Pin 13 NET 'NO_CONN_FPGA_Boot_Mem_Pin_14' U1251-14 # No Conn U1201 Pin 14 # # Bank #3 Default Operation Pull-Up Resistors # ------------------------------------------------- # NET 'Bank_3_FF_EXIT_N' U1-J13 R1351-2 # Pull-Up FF_EXIT_N NET 'Bank_3_IO_CFG_INTF' U1-H13 R1352-2 # Pull-Up IO_CFG_INTF NET 'Bank_3_SPI_EN' U1-K12 R1353-2 # Pull-Up SPI_EN NET 'BULK_3V3' R1351-1 R1352-1 R1353-1 # Pull-Up 3V3 Source