#
#     CPU  DDR4 Controller  to  DDR4 Memory Chips
#    -----
#
#       Address and Command Signals    Net List
#    ---------------------------------------------
#
#
#                                        Initial Rev.  29-Dec-2022
#                                        Current Rev.  14-Mar-2023
#
#
#   This net list holds the connections between the  CPU's DDR4
#   Controller  and  the two  DDR4 Memory Chips.  The CPU's DDR4
#   Controller uses pins in the  CPU HSIO Back #6.
#
#   The DDR4 memory chips  which are assumed to be Micron
#   MT40A1G16  16 Gbit, 1 Gig Address by 16 Data Bits in the
#   96 pin BGA package.
#
#       U1  is the MPFS250T  FPGA-CPU in the  FCVG784  package
#
#     U401  is the  MT40A1G16  SDRAM for data bits  0:15
#     U402  is the  MT40A1G16  SDRAM for data bits 16:31
#
#
#   The following signals have external termination resistors:
#
#     ADRS0 through ADRS13,  ADRS14_WE_B,  ADRS15_CAS_B,
#     ADRS16_RAS_B,  BA0, BA1, BG0,  ODT,  CLK_ENB,  CS_B,
#     PAR_IN,  ACT_B
#
#   This is 25 termination resistors to the VTERM_DDR4_CPU supply.
#
#
#   The  CLK_DIR - CLK_CMP  differential pair clock signal
#   has an external differential resistor terminator.
#
#   This is 2 more termination resistors.
#
#
#   That makes for a total of  27  external termination resistors
#   of 39 Ohms each.
#
#
#   The  ALERT_B  signal has an external Pull-Up resistor
#   to the 1V2 rail.
#
#   The  RESET_B  and  TEN  signals have an external Pull-Down
#   resistors to Ground.
#
#
#   This net list file defines:
#
#     30 pins  on each Memory Chip
#     29 pins  on the DDR4 Memory Controller Bank 6
#


#
#   Start with the Address and Control Bus that
#   goes to both U401 and U402.
#

NET   'DDR4_CPU_ADRS0'        U1-V1     U401-P3   U402-P3   R409-2
NET   'DDR4_CPU_ADRS1'        U1-V2     U401-P7   U402-P7   R410-2
NET   'DDR4_CPU_ADRS2'        U1-Y1     U401-R3   U402-R3   R405-2
NET   'DDR4_CPU_ADRS3'        U1-W1     U401-N7   U402-N7   R414-2
NET   'DDR4_CPU_ADRS4'        U1-W3     U401-N3   U402-N3   R413-2
NET   'DDR4_CPU_ADRS5'        U1-W4     U401-P8   U402-P8   R411-2
NET   'DDR4_CPU_ADRS6'        U1-W5     U401-P2   U402-P2   R408-2
NET   'DDR4_CPU_ADRS7'        U1-Y6     U401-R8   U402-R8   R407-2
NET   'DDR4_CPU_ADRS8'        U1-W6     U401-R2   U402-R2   R404-2
NET   'DDR4_CPU_ADRS9'        U1-Y5     U401-R7   U402-R7   R406-2

NET  'DDR4_CPU_ADRS10'        U1-V9     U401-M3   U402-M3   R417-2
NET  'DDR4_CPU_ADRS11'        U1-U9     U401-T2   U402-T2   R401-2
NET  'DDR4_CPU_ADRS12'        U1-V7     U401-M7   U402-M7   R418-2
NET  'DDR4_CPU_ADRS13'        U1-V8     U401-T8   U402-T8   R403-2

NET  'DDR4_CPU_ADRS14_WE_B'   U1-T7     U401-L2   U402-L2   R420-2
NET  'DDR4_CPU_ADRS15_CAS_B'  U1-U7     U401-M8   U402-M8   R419-2
NET  'DDR4_CPU_ADRS16_RAS_B'  U1-U10    U401-L8   U402-L8   R423-2

NET  'DDR4_CPU_BA0'           U1-U11    U401-N2   U402-N2   R412-2
NET  'DDR4_CPU_BA1'           U1-W10    U401-N8   U402-N8   R415-2

NET  'DDR4_CPU_BG0'           U1-U2     U401-M2   U402-M2   R416-2

NET  'DDR4_CPU_ODT'           U1-V3     U401-K3   U402-K3   R425-2

NET  'DDR4_CPU_CLK_DIR'       U1-Y3     U401-K7   U402-K7
NET  'DDR4_CPU_ClK_CMP'       U1-Y2     U401-K8   U402-K8

NET  'DDR4_CPU_CLK_ENB'       U1-V4     U401-K2   U402-K2   R424-2

NET  'DDR4_CPU_CS_B'          U1-T4     U401-L7   U402-L7   R422-2

NET  'DDR4_CPU_ALERT_B'       U1-V6     U401-P9   U402-P9

NET  'DDR4_CPU_PARITY'        U1-U6     U401-T3   U402-T3   R402-2

NET  'DDR4_CPU_ACT_B'         U1-U5     U401-L3   U402-L3   R421-2

NET  'DDR4_CPU_RESET_B'       U1-U1     U401-P1   U402-P1

NET  'DDR4_CPU_TEN'                     U401-N9   U402-N9   #  NOT Driven ?


#
#   Note:  the CPU (MSS)  DDR4 Controller in
#   the MPFS250T  does not appear to generate
#   a TEN signal.  MUST Verify.
#   TEN is the  High Active  Test Enable  signal.
#


#
#   Note:  the  ALERT_B,  RESET_B,  and  TEN  signals
#   do not have   termination resistors but the do have
#   pull-up  or  pull-down  resistors.  These connections
#   are made in the file:
#
#      ddr4_cpu_bank_6_power_and_sundry_nets.txt
#


#
#   Note:  the  DDR4_CPU_CLK  signals do have
#   differential termination resistors.  These
#   connections are made in the file:
#
#      ddr4_cpu_bank_6_power_and_sundry_nets.txt
#



#
#   Now connect the Termination Resistors to the
#   DDR4_VTERM_CPU  supply  and  connect the
#   bypass capacitors for this supply to it and
#   to ground.
#

NET  'DDR4_VTERM_CPU'    R401-1   R402-1   R403-1   R404-1   R405-1
NET  'DDR4_VTERM_CPU'    R406-1   R407-1   R408-1   R409-1   R410-1
NET  'DDR4_VTERM_CPU'    R411-1   R412-1   R413-1   R414-1   R415-1
NET  'DDR4_VTERM_CPU'    R416-1   R417-1   R418-1   R419-1   R420-1
NET  'DDR4_VTERM_CPU'    R421-1   R422-1   R423-1   R424-1   R425-1


NET  'DDR4_VTERM_CPU'    C471-2   C472-2   C473-2   C474-2   C475-2
NET  'DDR4_VTERM_CPU'    C476-2   C477-2   C478-2   C479-2   C480-2
NET  'DDR4_VTERM_CPU'    C481-2   C482-2   C483-2   C484-2

NET  'GROUND'            C471-1   C472-1   C473-1   C474-1   C475-1
NET  'GROUND'            C476-1   C477-1   C478-1   C479-1   C480-1
NET  'GROUND'            C481-1   C482-1   C483-1   C484-1