#
#     CPU  DDR4 Controller  to  DDR4 Memory Chips
#    -----
#               Data Path     Net List
#    ---------------------------------------------
#
#
#                                        Initial Rev.  29-Dec-2022
#                                        Current Rev.   8-Mar-2023
#
#
#   This net list holds the connections between the  CPU's DDR4
#   Controller  and  the two  DDR4 Memory Chips.  The CPU's DDR4
#   Controller uses pins in the  CPU HSIO Back #6.
#
#   The DDR4 memory chips  which are assumed to be Micron
#   MT40A1G16  16 Gbit, 1 Gig Address by 16 Data Bits in the
#   96 pin BGA package.
#
#       U1  is the MPFS250T  FPGA-CPU in the  FCVG784  package
#
#     U401  is the  MT40A1G16  SDRAM for data bits  0:15
#     U402  is the  MT40A1G16  SDRAM for data bits 16:31
#
#
#   This net list file defines:
#
#     22 pins  on each Memory Chip
#     44 pins  on the DDR4 Memory Controller Bank 6
#



#
#   Now the Data Path type signals D0:D15 to U401
#

NET  'DDR4_CPU_DQ0'           U1-AB5    U401-G2
NET  'DDR4_CPU_DQ1'           U1-AB4    U401-F7
NET  'DDR4_CPU_DQ2'           U1-AA4    U401-H3
NET  'DDR4_CPU_DQ3'           U1-AA3    U401-H7
NET  'DDR4_CPU_DQ4'           U1-AA2    U401-H2
NET  'DDR4_CPU_DQ5'           U1-AC4    U401-H8
NET  'DDR4_CPU_DQ6'           U1-AC1    U401-J3
NET  'DDR4_CPU_DQ7'           U1-AC2    U401-J7

NET  'DDR4_CPU_DQS0_DIR'      U1-AB2    U401-G3
NET  'DDR4_CPU_DQS0_CMP'      U1-AB1    U401-F3

NET  'DDR4_CPU_DM0_B'         U1-AC3    U401-E7


NET  'DDR4_CPU_DQ8'           U1-AB7    U401-A3
NET  'DDR4_CPU_DQ9'           U1-AC6    U401-B8
NET  'DDR4_CPU_DQ10'          U1-AC7    U401-C3
NET  'DDR4_CPU_DQ11'          U1-AA5    U401-C7
NET  'DDR4_CPU_DQ12'          U1-AB6    U401-C2
NET  'DDR4_CPU_DQ13'          U1-AC8    U401-C8
NET  'DDR4_CPU_DQ14'          U1-AA9    U401-D3
NET  'DDR4_CPU_DQ15'          U1-AB9    U401-D7

NET  'DDR4_CPU_DQS1_DIR'      U1-AA7    U401-B7
NET  'DDR4_CPU_DQS1_CMP'      U1-AA8    U401-A7

NET  'DDR4_CPU_DM1_B'         U1-AC9    U401-E2




#
#   Now the Data Path type signals D16:D31 to U402
#

NET  'DDR4_CPU_DQ16'          U1-AD6    U402-G2
NET  'DDR4_CPU_DQ17'          U1-AE5    U402-F7
NET  'DDR4_CPU_DQ18'          U1-AD5    U402-H3
NET  'DDR4_CPU_DQ19'          U1-AD4    U402-H7
NET  'DDR4_CPU_DQ20'          U1-AF5    U402-H2
NET  'DDR4_CPU_DQ21'          U1-AE6    U402-H8
NET  'DDR4_CPU_DQ22'          U1-AE2    U402-J3
NET  'DDR4_CPU_DQ23'          U1-AD1    U402-J7

NET  'DDR4_CPU_DQS2_DIR'      U1-AD3    U402-G3
NET  'DDR4_CPU_DQS2_CMP'      U1-AE3    U402-F3

NET  'DDR4_CPU_DM2_B'         U1-AE1    U402-E7


NET  'DDR4_CPU_DQ24'          U1-AF4    U402-A3
NET  'DDR4_CPU_DQ25'          U1-AF3    U402-B8
NET  'DDR4_CPU_DQ26'          U1-AF1    U402-C3
NET  'DDR4_CPU_DQ27'          U1-AG1    U402-C7
NET  'DDR4_CPU_DQ28'          U1-AH2    U402-C2
NET  'DDR4_CPU_DQ29'          U1-AH3    U402-C8
NET  'DDR4_CPU_DQ30'          U1-AG5    U402-D3
NET  'DDR4_CPU_DQ31'          U1-AG4    U402-D7

NET  'DDR4_CPU_DQS3_DIR'      U1-AF2    U402-B7
NET  'DDR4_CPU_DQS3_CMP'      U1-AG2    U402-A7

NET  'DDR4_CPU_DM3_B'         U1-AH4    U402-E2