# # CPU DDR4 Controller to DDR4 Memory Chips # ----- # # CPU (MSS) Bank 6 No Connection Net List # ----------------------------------------------- # # # Initial Rev. 29-Dec-2022 # Current Rev. 8-Mar-2023 # # # This net list holds the pins in the CPU (MSS) # BANK 6 DDR Controller that have No Connection # when this DDR Controller is used with DDR4 Memory Chips. # # # # Un-Used Pins in the U1 CPU's Bank 6 # i.e. the DDR Controller. # # These pins are declared as "Single Pin Nets". # # This net list file holds 15 pins in the Bank 6 DDR Memory Controller. # # # Pins for a Second Rank of memory chips. # NET 'NO_CONN_U1_PIN_U4' U1-U4 # CPU DDR4 Controller BG1 pin U4 NET 'NO_CONN_U1_PIN_T5' U1-T5 # CPU DDR4 Controller ODT1 pin T5 NET 'NO_CONN_U1_PIN_W8' U1-W8 # CPU DDR4 Controller CLK1_P pin W8 NET 'NO_CONN_U1_PIN_W9' U1-W9 # CPU DDR4 Controller CLK1_N pin W9 NET 'NO_CONN_U1_PIN_T2' U1-T2 # CPU DDR4 Controller CKE1 pin T2 NET 'NO_CONN_U1_PIN_T3' U1-T3 # CPU DDR4 Controller CS1_n pin T3 # # Pin for a Error Checking Correcting memory system. # NET 'NO_CONN_U1_PIN_AB10' U1-AB10 # CPU DDR4 Controller DQ0_ECC pin AB10 NET 'NO_CONN_U1_PIN_AB11' U1-AB11 # CPU DDR4 Controller DQ1_ECC pin AB11 NET 'NO_CONN_U1_PIN_AA10' U1-AA10 # CPU DDR4 Controller DQ2_ECC pin AA10 NET 'NO_CONN_U1_PIN_Y11' U1-Y11 # CPU DDR4 Controller DQ3_ECC pin Y11 NET 'NO_CONN_U1_PIN_Y7' U1-Y7 # CPU DDR4 Controller DQSP_ECC pin Y7 NET 'NO_CONN_U1_PIN_Y8' U1-Y8 # CPU DDR4 Controller DQSN_ECC pin Y8 NET 'NO_CONN_U1_PIN_W11' U1-W11 # CPU DDR4 Controller DQM_ECC/DBI_ECC pin W11 # # Other Un-Used Pins in the CPU DDR Controller Bank 6 # NET 'NO_CONN_U1_PIN_V11' U1-V11 # CPU DDR4 Controller MSS_DDR3_WE_N NET 'NO_CONN_U1_PIN_Y10' U1-Y10 # CPU DDR4 Controller MSS_DDR_VREF_IN