#
#     FPGA  DDR4 Controller  to  DDR4 Memory Chips
#    ------
#
#        Address and Command Signals   Net List
#    ----------------------------------------------
#
#
#                                        Initial Rev.  10-Mar-2023
#                                        Current Rev.  14-Mar-2023
#
#
#   This net list holds the connections between the  FPGA's DDR4
#   Controller  and  the two  DDR4 Memory Chips.  The FPGA's DDR4
#   Controller uses pins in the  FPGA HSIO Back #0.
#
#   The DDR4 memory chips  which are assumed to be Micron
#   MT40A1G16  16 Gbit, 1 Gig Address by 16 Data Bits in the
#   96 pin BGA package.
#
#       U1  is the MPFS250T  FPGA-CPU in the  FCVG784  package
#
#     U301  is the  MT40A1G16  SDRAM for data bits  0:15
#     U302  is the  MT40A1G16  SDRAM for data bits 16:31
#
#
#   The following signals have external termination resistors:
#
#     ADRS0 through ADRS13,  ADRS14_WE_B,  ADRS15_CAS_B,
#     ADRS16_RAS_B,  BA0, BA1, BG0,  ODT,  CLK_ENB,  CS_B,
#     PAR_IN,  ACT_B
#
#   This is 25 termination resistors to the VTERM_DDR4_FPGA supply.
#
#
#   The  CLK_DIR - CLK_CMP  differential pair clock signal
#   has an external differential resistor terminator.
#
#   This is 2 more termination resistors.
#
#
#   That makes for a total of  27  external termination resistors
#   of 39 Ohms each.
#
#
#   The  ALERT_B  signal has an external Pull-Up resistor
#   to the 1V2 rail.
#
#   The  RESET_B  and  TEN  signals have an external Pull-Down
#   resistors to Ground.
#
#
#   This net list file defines:
#
#     30 pins  on each Memory Chip
#     30 pins  on the DDR4 Memory Controller Bank 0
#


#
#   Start with the Address and Control Bus that
#   goes to both U301 and U302.
#

NET   'DDR4_FPGA_ADRS0'        U1-AG28   U301-P3   U302-P3   R309-2
NET   'DDR4_FPGA_ADRS1'        U1-Y22    U301-P7   U302-P7   R310-2
NET   'DDR4_FPGA_ADRS2'        U1-AC26   U301-R3   U302-R3   R305-2
NET   'DDR4_FPGA_ADRS3'        U1-Y23    U301-N7   U302-N7   R314-2
NET   'DDR4_FPGA_ADRS4'        U1-AE26   U301-N3   U302-N3   R313-2
NET   'DDR4_FPGA_ADRS5'        U1-AC27   U301-P8   U302-P8   R311-2
NET   'DDR4_FPGA_ADRS6'        U1-AG27   U301-P2   U302-P2   R308-2
NET   'DDR4_FPGA_ADRS7'        U1-AC22   U301-R8   U302-R8   R307-2
NET   'DDR4_FPGA_ADRS8'        U1-Y21    U301-R2   U302-R2   R304-2
NET   'DDR4_FPGA_ADRS9'        U1-AC28   U301-R7   U302-R7   R306-2

NET  'DDR4_FPGA_ADRS10'        U1-AE25   U301-M3   U302-M3   R317-2
NET  'DDR4_FPGA_ADRS11'        U1-W21    U301-T2   U302-T2   R301-2
NET  'DDR4_FPGA_ADRS12'        U1-AA22   U301-M7   U302-M7   R318-2
NET  'DDR4_FPGA_ADRS13'        U1-AB22   U301-T8   U302-T8   R303-2

NET  'DDR4_FPGA_ADRS14_WE_B'   U1-AF25   U301-L2   U302-L2   R320-2
NET  'DDR4_FPGA_ADRS15_CAS_B'  U1-AF28   U301-M8   U302-M8   R319-2
NET  'DDR4_FPGA_ADRS16_RAS_B'  U1-AF27   U301-L8   U302-L8   R323-2

NET  'DDR4_FPGA_BA0'           U1-AD24   U301-N2   U302-N2   R312-2
NET  'DDR4_FPGA_BA1'           U1-AD28   U301-N8   U302-N8   R315-2

NET  'DDR4_FPGA_BG0'           U1-AF24   U301-M2   U302-M2   R316-2

NET  'DDR4_FPGA_ODT'           U1-AH26   U301-K3   U302-K3   R325-2

NET  'DDR4_FPGA_CLK_DIR'       U1-AB25   U301-K7   U302-K7
NET  'DDR4_FPGA_ClK_CMP'       U1-AB24   U301-K8   U302-K8

NET  'DDR4_FPGA_CLK_ENB'       U1-AG26   U301-K2   U302-K2   R324-2

NET  'DDR4_FPGA_CS_B'          U1-AH27   U301-L7   U302-L7   R322-2

NET  'DDR4_FPGA_ALERT_B'       U1-W22    U301-P9   U302-P9

NET  'DDR4_FPGA_PARITY'        U1-AC24   U301-T3   U302-T3   R302-2

NET  'DDR4_FPGA_ACT_B'         U1-AD25   U301-L3   U302-L3   R321-2

NET  'DDR4_FPGA_RESET_B'       U1-AD21   U301-P1   U302-P1

NET  'DDR4_FPGA_TEN'           U1-AA23   U301-N9   U302-N9



#
#   Note:  the  ALERT_B,  RESET_B,  and  TEN  signals
#   do not have   termination resistors but the do have
#   pull-up  or  pull-down  resistors.  These connections
#   are made in the file:
#
#      ddr4_fpga_bank_0_power_and_sundry_nets.txt
#


#
#   Note:  the  DDR4_FPGA_CLK  signals do have
#   differential termination resistors.  These
#   connections are made in the file:
#
#      ddr4_fpga_bank_0_power_and_sundry_nets.txt
#



#
#   Now connect the Termination Resistors to the
#   DDR4_VTERM_FPGA  supply  and  connect the
#   bypass capacitors for this supply to it and
#   to ground.
#

NET  'DDR4_VTERM_FPGA'   R301-1   R302-1   R303-1   R304-1   R305-1
NET  'DDR4_VTERM_FPGA'   R306-1   R307-1   R308-1   R309-1   R310-1
NET  'DDR4_VTERM_FPGA'   R311-1   R312-1   R313-1   R314-1   R315-1
NET  'DDR4_VTERM_FPGA'   R316-1   R317-1   R318-1   R319-1   R320-1
NET  'DDR4_VTERM_FPGA'   R321-1   R322-1   R323-1   R324-1   R325-1


NET  'DDR4_VTERM_FPGA'   C371-2   C372-2   C373-2   C374-2   C375-2
NET  'DDR4_VTERM_FPGA'   C376-2   C377-2   C378-2   C379-2   C380-2
NET  'DDR4_VTERM_FPGA'   C381-2   C382-2   C383-2   C384-2

NET  'GROUND'            C371-1   C372-1   C373-1   C374-1   C375-1
NET  'GROUND'            C376-1   C377-1   C378-1   C379-1   C380-1
NET  'GROUND'            C381-1   C382-1   C383-1   C384-1