#
#     FPGA  DDR4 Controller  to  DDR4 Memory Chips
#    ------
#
#               Data Path       Net List
#    ----------------------------------------------
#
#
#                                        Initial Rev.  10-Mar-2023
#                                        Current Rev.  10-Mar-2023
#
#
#   This net list holds the connections between the  FPGA's DDR4
#   Controller  and  the two  DDR4 Memory Chips.  The FPGA's DDR4
#   Controller uses pins in the  FPGA HSIO Back #0.
#
#   The DDR4 memory chips  which are assumed to be Micron
#   MT40A1G16  16 Gbit, 1 Gig Address by 16 Data Bits in the
#   96 pin BGA package.
#
#       U1  is the MPFS250T  FPGA-CPU in the  FCVG784  package
#
#     U301  is the  MT40A1G16  SDRAM for data bits  0:15
#     U302  is the  MT40A1G16  SDRAM for data bits 16:31
#
#
#   This net list file defines:
#
#     22 pins  on each Memory Chip
#     44 pins  on the DDR4 Memory Controller Bank 0
#



#
#   Now the Data Path type signals D0:D15 to U301
#

NET  'DDR4_FPGA_DQ0'           U1-AG24   U301-G2
NET  'DDR4_FPGA_DQ1'           U1-AE23   U301-F7
NET  'DDR4_FPGA_DQ2'           U1-AF23   U301-H3
NET  'DDR4_FPGA_DQ3'           U1-AH23   U301-H7
NET  'DDR4_FPGA_DQ4'           U1-AH22   U301-H2
NET  'DDR4_FPGA_DQ5'           U1-AG21   U301-H8
NET  'DDR4_FPGA_DQ6'           U1-AH21   U301-J3
NET  'DDR4_FPGA_DQ7'           U1-AF22   U301-J7

NET  'DDR4_FPGA_DQS0_DIR'      U1-AE21   U301-G3
NET  'DDR4_FPGA_DQS0_CMP'      U1-AE22   U301-F3

NET  'DDR4_FPGA_DM0_B'         U1-AG22   U301-E7


NET  'DDR4_FPGA_DQ8'           U1-AG20   U301-A3
NET  'DDR4_FPGA_DQ9'           U1-AD19   U301-B8
NET  'DDR4_FPGA_DQ10'          U1-AC19   U301-C3
NET  'DDR4_FPGA_DQ11'          U1-AG19   U301-C7
NET  'DDR4_FPGA_DQ12'          U1-AF19   U301-C2
NET  'DDR4_FPGA_DQ13'          U1-AH19   U301-C8
NET  'DDR4_FPGA_DQ14'          U1-AH18   U301-D3
NET  'DDR4_FPGA_DQ15'          U1-AF18   U301-D7

NET  'DDR4_FPGA_DQS1_DIR'      U1-AE20   U301-B7
NET  'DDR4_FPGA_DQS1_CMP'      U1-AD20   U301-A7

NET  'DDR4_FPGA_DM1_B'         U1-AE18   U301-E2




#
#   Now the Data Path type signals D16:D31 to U302
#

NET  'DDR4_FPGA_DQ16'          U1-AC21   U302-G2
NET  'DDR4_FPGA_DQ17'          U1-AB21   U302-F7
NET  'DDR4_FPGA_DQ18'          U1-Y20    U302-H3
NET  'DDR4_FPGA_DQ19'          U1-W20    U302-H7
NET  'DDR4_FPGA_DQ20'          U1-Y19    U302-H2
NET  'DDR4_FPGA_DQ21'          U1-W19    U302-H8
NET  'DDR4_FPGA_DQ22'          U1-AA19   U302-J3
NET  'DDR4_FPGA_DQ23'          U1-AB19   U302-J7

NET  'DDR4_FPGA_DQS2_DIR'      U1-AB20   U302-G3
NET  'DDR4_FPGA_DQS2_CMP'      U1-AA20   U302-F3

NET  'DDR4_FPGA_DM2_B'         U1-AA18   U302-E7


NET  'DDR4_FPGA_DQ24'          U1-AE16   U302-A3
NET  'DDR4_FPGA_DQ25'          U1-AD16   U302-B8
NET  'DDR4_FPGA_DQ26'          U1-AC18   U302-C3
NET  'DDR4_FPGA_DQ27'          U1-AD18   U302-C7
NET  'DDR4_FPGA_DQ28'          U1-AH17   U302-C2
NET  'DDR4_FPGA_DQ29'          U1-AG17   U302-C8
NET  'DDR4_FPGA_DQ30'          U1-AH16   U302-D3
NET  'DDR4_FPGA_DQ31'          U1-AG16   U302-D7

NET  'DDR4_FPGA_DQS3_DIR'      U1-AE17   U302-B7
NET  'DDR4_FPGA_DQS3_CMP'      U1-AF17   U302-A7

NET  'DDR4_FPGA_DM3_B'         U1-AC17   U302-E2