# # FPGA DDR4 Controller to DDR4 Memory Chips # ------ # # FPGA Bank 0 No Connection Net List # ------------------------------------------------ # # # Initial Rev. 10-Mar-2023 # Current Rev. 13-Mar-2023 # # # This net list holds the pins in the FPGA BANK 0 # DDR Controller that have No Connection when this # DDR Controller is used with DDR4 Memory Chips. # # # # Un-Used Pins in the U1 FPGA's Bank 0 # i.e. the DDR Controller. # # These pins are declared as "Single Pin Nets". # # We are using BANK 0 pins for the FPGA's DDR4 Controller # with 32 Data Bits and One Rank. Microchip may call this # the North-NE Option 1. # # These BANK 0 pins are used with some other DDR4 options, e.g. # bus widths > 32 bits, North-NW option, and Option 2. # # This net list file holds 10 pins in the Bank 0 DDR Memory Controller. # NET 'NO_CONN_U1_PIN_AC16' U1-AC16 # DQ16 for North_NW Option 1 & 2 NET 'NO_CONN_U1_PIN_AC23' U1-AC23 # DQ60 for North_NW Option 1 & 2 NET 'NO_CONN_U1_PIN_AD23' U1-AD23 # CS1_B for North-NE Option 2 NET 'NO_CONN_U1_PIN_AD26' U1-AD26 # BG1 for North_NE Option 1 & 2 # DQ66 for North-NW Option 1 & 2 NET 'NO_CONN_U1_PIN_AE27' U1-AE27 # DQS8 for North-NW Option 1 & 2 # CK1 for North-NE Option 2 NET 'NO_CONN_U1_PIN_AE28' U1-AE28 # DQS8_B for North-NW Option 1 & 2 # CK1_B for North-NE Option 2 NET 'NO_CONN_U1_PIN_AF20' U1-AF20 # DQ39 for North-NW Option 1 & 2 NET 'NO_CONN_U1_PIN_AG25' U1-AG25 # DQ48 for North-NW Option 1 & 2 # CKE1 for North-NE Option 2 NET 'NO_CONN_U1_PIN_AH24' U1-AH24 # DQ47 for North-NW Option 1 & 2 NET 'NO_CONN_U1_PIN_Y18' U1-Y18 # DQ24 for North-NW Option 1 & 2