# # FPGA DDR4 CONTROLLER TO DDR4 MEMORY CHIPS # ------ # # ADDRESS AND COMMAND SIGNALS NET LIST # ---------------------------------------------- # # # INITIAL REV. 10-MAR-2023 # CURRENT REV. 14-MAR-2023 # # # THIS NET LIST HOLDS THE CONNECTIONS BETWEEN THE FPGA'S DDR4 # CONTROLLER AND THE TWO DDR4 MEMORY CHIPS. THE FPGA'S DDR4 # CONTROLLER USES PINS IN THE FPGA HSIO BACK #0. # # THE DDR4 MEMORY CHIPS WHICH ARE ASSUMED TO BE MICRON # MT40A1G16 16 GBIT, 1 GIG ADDRESS BY 16 DATA BITS IN THE # 96 PIN BGA PACKAGE. # # U1 IS THE MPFS250T FPGA-CPU IN THE FCVG784 PACKAGE # # U301 IS THE MT40A1G16 SDRAM FOR DATA BITS 0:15 # U302 IS THE MT40A1G16 SDRAM FOR DATA BITS 16:31 # # # THE FOLLOWING SIGNALS HAVE EXTERNAL TERMINATION RESISTORS: # # ADRS0 THROUGH ADRS13, ADRS14_WE_B, ADRS15_CAS_B, # ADRS16_RAS_B, BA0, BA1, BG0, ODT, CLK_ENB, CS_B, # PAR_IN, ACT_B # # THIS IS 25 TERMINATION RESISTORS TO THE VTERM_DDR4_FPGA SUPPLY. # # # THE CLK_DIR - CLK_CMP DIFFERENTIAL PAIR CLOCK SIGNAL # HAS AN EXTERNAL DIFFERENTIAL RESISTOR TERMINATOR. # # THIS IS 2 MORE TERMINATION RESISTORS. # # # THAT MAKES FOR A TOTAL OF 27 EXTERNAL TERMINATION RESISTORS # OF 39 OHMS EACH. # # # THE ALERT_B SIGNAL HAS AN EXTERNAL PULL-UP RESISTOR # TO THE 1V2 RAIL. # # THE RESET_B AND TEN SIGNALS HAVE AN EXTERNAL PULL-DOWN # RESISTORS TO GROUND. # # # THIS NET LIST FILE DEFINES: # # 30 PINS ON EACH MEMORY CHIP # 30 PINS ON THE DDR4 MEMORY CONTROLLER BANK 0 # # # START WITH THE ADDRESS AND CONTROL BUS THAT # GOES TO BOTH U301 AND U302. # NET 'DDR4_FPGA_ADRS0' U1-AG28 U301-P3 U302-P3 R309-2 NET 'DDR4_FPGA_ADRS1' U1-Y22 U301-P7 U302-P7 R310-2 NET 'DDR4_FPGA_ADRS2' U1-AC26 U301-R3 U302-R3 R305-2 NET 'DDR4_FPGA_ADRS3' U1-Y23 U301-N7 U302-N7 R314-2 NET 'DDR4_FPGA_ADRS4' U1-AE26 U301-N3 U302-N3 R313-2 NET 'DDR4_FPGA_ADRS5' U1-AC27 U301-P8 U302-P8 R311-2 NET 'DDR4_FPGA_ADRS6' U1-AG27 U301-P2 U302-P2 R308-2 NET 'DDR4_FPGA_ADRS7' U1-AC22 U301-R8 U302-R8 R307-2 NET 'DDR4_FPGA_ADRS8' U1-Y21 U301-R2 U302-R2 R304-2 NET 'DDR4_FPGA_ADRS9' U1-AC28 U301-R7 U302-R7 R306-2 NET 'DDR4_FPGA_ADRS10' U1-AE25 U301-M3 U302-M3 R317-2 NET 'DDR4_FPGA_ADRS11' U1-W21 U301-T2 U302-T2 R301-2 NET 'DDR4_FPGA_ADRS12' U1-AA22 U301-M7 U302-M7 R318-2 NET 'DDR4_FPGA_ADRS13' U1-AB22 U301-T8 U302-T8 R303-2 NET 'DDR4_FPGA_ADRS14_WE_B' U1-AF25 U301-L2 U302-L2 R320-2 NET 'DDR4_FPGA_ADRS15_CAS_B' U1-AF28 U301-M8 U302-M8 R319-2 NET 'DDR4_FPGA_ADRS16_RAS_B' U1-AF27 U301-L8 U302-L8 R323-2 NET 'DDR4_FPGA_BA0' U1-AD24 U301-N2 U302-N2 R312-2 NET 'DDR4_FPGA_BA1' U1-AD28 U301-N8 U302-N8 R315-2 NET 'DDR4_FPGA_BG0' U1-AF24 U301-M2 U302-M2 R316-2 NET 'DDR4_FPGA_ODT' U1-AH26 U301-K3 U302-K3 R325-2 NET 'DDR4_FPGA_CLK_DIR' U1-AB25 U301-K7 U302-K7 NET 'DDR4_FPGA_CLK_CMP' U1-AB24 U301-K8 U302-K8 NET 'DDR4_FPGA_CLK_ENB' U1-AG26 U301-K2 U302-K2 R324-2 NET 'DDR4_FPGA_CS_B' U1-AH27 U301-L7 U302-L7 R322-2 NET 'DDR4_FPGA_ALERT_B' U1-W22 U301-P9 U302-P9 NET 'DDR4_FPGA_PARITY' U1-AC24 U301-T3 U302-T3 R302-2 NET 'DDR4_FPGA_ACT_B' U1-AD25 U301-L3 U302-L3 R321-2 NET 'DDR4_FPGA_RESET_B' U1-AD21 U301-P1 U302-P1 NET 'DDR4_FPGA_TEN' U1-AA23 U301-N9 U302-N9 # # NOTE: THE ALERT_B, RESET_B, AND TEN SIGNALS # DO NOT HAVE TERMINATION RESISTORS BUT THE DO HAVE # PULL-UP OR PULL-DOWN RESISTORS. THESE CONNECTIONS # ARE MADE IN THE FILE: # # DDR4_FPGA_BANK_0_POWER_AND_SUNDRY_NETS.TXT # # # NOTE: THE DDR4_FPGA_CLK SIGNALS DO HAVE # DIFFERENTIAL TERMINATION RESISTORS. THESE # CONNECTIONS ARE MADE IN THE FILE: # # DDR4_FPGA_BANK_0_POWER_AND_SUNDRY_NETS.TXT # # # NOW CONNECT THE TERMINATION RESISTORS TO THE # DDR4_VTERM_FPGA SUPPLY AND CONNECT THE # BYPASS CAPACITORS FOR THIS SUPPLY TO IT AND # TO GROUND. # NET 'DDR4_VTERM_FPGA' R301-1 R302-1 R303-1 R304-1 R305-1 NET 'DDR4_VTERM_FPGA' R306-1 R307-1 R308-1 R309-1 R310-1 NET 'DDR4_VTERM_FPGA' R311-1 R312-1 R313-1 R314-1 R315-1 NET 'DDR4_VTERM_FPGA' R316-1 R317-1 R318-1 R319-1 R320-1 NET 'DDR4_VTERM_FPGA' R321-1 R322-1 R323-1 R324-1 R325-1 NET 'DDR4_VTERM_FPGA' C371-2 C372-2 C373-2 C374-2 C375-2 NET 'DDR4_VTERM_FPGA' C376-2 C377-2 C378-2 C379-2 C380-2 NET 'DDR4_VTERM_FPGA' C381-2 C382-2 C383-2 C384-2 NET 'GROUND' C371-1 C372-1 C373-1 C374-1 C375-1 NET 'GROUND' C376-1 C377-1 C378-1 C379-1 C380-1 NET 'GROUND' C381-1 C382-1 C383-1 C384-1 # # FPGA DDR4 CONTROLLER TO DDR4 MEMORY CHIPS # ------ # # DATA PATH NET LIST # ---------------------------------------------- # # # INITIAL REV. 10-MAR-2023 # CURRENT REV. 10-MAR-2023 # # # THIS NET LIST HOLDS THE CONNECTIONS BETWEEN THE FPGA'S DDR4 # CONTROLLER AND THE TWO DDR4 MEMORY CHIPS. THE FPGA'S DDR4 # CONTROLLER USES PINS IN THE FPGA HSIO BACK #0. # # THE DDR4 MEMORY CHIPS WHICH ARE ASSUMED TO BE MICRON # MT40A1G16 16 GBIT, 1 GIG ADDRESS BY 16 DATA BITS IN THE # 96 PIN BGA PACKAGE. # # U1 IS THE MPFS250T FPGA-CPU IN THE FCVG784 PACKAGE # # U301 IS THE MT40A1G16 SDRAM FOR DATA BITS 0:15 # U302 IS THE MT40A1G16 SDRAM FOR DATA BITS 16:31 # # # THIS NET LIST FILE DEFINES: # # 22 PINS ON EACH MEMORY CHIP # 44 PINS ON THE DDR4 MEMORY CONTROLLER BANK 0 # # # NOW THE DATA PATH TYPE SIGNALS D0:D15 TO U301 # NET 'DDR4_FPGA_DQ0' U1-AG24 U301-G2 NET 'DDR4_FPGA_DQ1' U1-AE23 U301-F7 NET 'DDR4_FPGA_DQ2' U1-AF23 U301-H3 NET 'DDR4_FPGA_DQ3' U1-AH23 U301-H7 NET 'DDR4_FPGA_DQ4' U1-AH22 U301-H2 NET 'DDR4_FPGA_DQ5' U1-AG21 U301-H8 NET 'DDR4_FPGA_DQ6' U1-AH21 U301-J3 NET 'DDR4_FPGA_DQ7' U1-AF22 U301-J7 NET 'DDR4_FPGA_DQS0_DIR' U1-AE21 U301-G3 NET 'DDR4_FPGA_DQS0_CMP' U1-AE22 U301-F3 NET 'DDR4_FPGA_DM0_B' U1-AG22 U301-E7 NET 'DDR4_FPGA_DQ8' U1-AG20 U301-A3 NET 'DDR4_FPGA_DQ9' U1-AD19 U301-B8 NET 'DDR4_FPGA_DQ10' U1-AC19 U301-C3 NET 'DDR4_FPGA_DQ11' U1-AG19 U301-C7 NET 'DDR4_FPGA_DQ12' U1-AF19 U301-C2 NET 'DDR4_FPGA_DQ13' U1-AH19 U301-C8 NET 'DDR4_FPGA_DQ14' U1-AH18 U301-D3 NET 'DDR4_FPGA_DQ15' U1-AF18 U301-D7 NET 'DDR4_FPGA_DQS1_DIR' U1-AE20 U301-B7 NET 'DDR4_FPGA_DQS1_CMP' U1-AD20 U301-A7 NET 'DDR4_FPGA_DM1_B' U1-AE18 U301-E2 # # NOW THE DATA PATH TYPE SIGNALS D16:D31 TO U302 # NET 'DDR4_FPGA_DQ16' U1-AC21 U302-G2 NET 'DDR4_FPGA_DQ17' U1-AB21 U302-F7 NET 'DDR4_FPGA_DQ18' U1-Y20 U302-H3 NET 'DDR4_FPGA_DQ19' U1-W20 U302-H7 NET 'DDR4_FPGA_DQ20' U1-Y19 U302-H2 NET 'DDR4_FPGA_DQ21' U1-W19 U302-H8 NET 'DDR4_FPGA_DQ22' U1-AA19 U302-J3 NET 'DDR4_FPGA_DQ23' U1-AB19 U302-J7 NET 'DDR4_FPGA_DQS2_DIR' U1-AB20 U302-G3 NET 'DDR4_FPGA_DQS2_CMP' U1-AA20 U302-F3 NET 'DDR4_FPGA_DM2_B' U1-AA18 U302-E7 NET 'DDR4_FPGA_DQ24' U1-AE16 U302-A3 NET 'DDR4_FPGA_DQ25' U1-AD16 U302-B8 NET 'DDR4_FPGA_DQ26' U1-AC18 U302-C3 NET 'DDR4_FPGA_DQ27' U1-AD18 U302-C7 NET 'DDR4_FPGA_DQ28' U1-AH17 U302-C2 NET 'DDR4_FPGA_DQ29' U1-AG17 U302-C8 NET 'DDR4_FPGA_DQ30' U1-AH16 U302-D3 NET 'DDR4_FPGA_DQ31' U1-AG16 U302-D7 NET 'DDR4_FPGA_DQS3_DIR' U1-AE17 U302-B7 NET 'DDR4_FPGA_DQS3_CMP' U1-AF17 U302-A7 NET 'DDR4_FPGA_DM3_B' U1-AC17 U302-E2 # # FPGA FABRIC DDR4 CONTROLLER TO DDR4 MEMORY CHIPS # ------------- # # POWER SUPPLY AND SUNDRY NET LIST # ----------------------------------------------------- # # # INITIAL REV. 10-MAR-2023 # CURRENT REV. 1-MAR-2023 # # # THIS NET LIST HOLDS THE POWER AND GROUND CONNECTIONS # ON EACH MEMORY CHIP AND 2 SUNDRY PINS ON EACH OF # THESE CHIPS. # # THE DDR4 MEMORY CHIPS WHICH ARE ASSUMED TO BE MICRON # MT40A1G16 16 GBIT, 1 GIG ADDRESS BY 16 DATA BITS IN THE # 96 PIN BGA PACKAGE. # # U1 IS THE MPFS250T FPGA-CPU IN THE FCVG784 PACKAGE # # U301 IS THE MT40A1G16 SDRAM FOR DATA BITS 0:15 # U302 IS THE MT40A1G16 SDRAM FOR DATA BITS 16:31 # # # THE ZQ SIGNAL HAS AN EXTERNAL 240 OHM RESISTOR TO # GROUND - A SEPARATE RESISTOR FOR EACH OF THE 2 SDRAM CHIPS. # # # THIS FILE HAS 44 PINS ON EACH MEMORY CHIP # AND NO PINS ON THE DDR4 MEMORY CONTROLLER. # # # FOR THE 2 MEMORY CHIPS: # # THE ZQ REFERENCE RESISTORS # # THE CLOCK TERMINATION RESISTORS AND CAPACITORS # # THE ALERT_B PULL-UP RESISTOR # # THE RESET_B PULL-DOWN RESISTOR # # THE TEN PULL-DOWN RESISTOR # # THE UN-USED PIN ON EACH MEMORY CHIP # NET 'ZQ_REFERENCE_U301' U301-F9 R328-2 NET 'ZQ_REFERENCE_U302' U302-F9 R329-2 NET 'GROUND' R328-1 R329-1 NET 'DDR4_FPGA_CLK_CMP' R326-2 NET 'DDR4_FPGA_CLK_DIR' R327-2 NET 'DDR4_FPGA_CLK_TERM' R326-1 R327-1 NET 'DDR4_FPGA_CLK_TERM' C385-2 C386-2 NET 'BULK_1V2' C385-1 C386-1 NET 'DDR4_FPGA_ALERT_B' R330-2 NET 'BULK_1V2' R330-1 NET 'DDR4_FPGA_RESET_B' R331-2 NET 'GROUND' R331-1 NET 'DDR4_FPGA_TEN' R332-2 NET 'GROUND' R332-1 NET 'NO_CONN_U301_PIN_T7' U301-T7 NET 'NO_CONN_U302_PIN_T7' U302-T7 # # U301 POWER AND GROUND # NET 'BULK_1V2' U301-B3 U301-B9 U301-D1 U301-G7 U301-J1 # VDD NET 'BULK_1V2' U301-J9 U301-L1 U301-L9 U301-R1 U301-T9 NET 'BULK_1V2' U301-A1 U301-A9 U301-C1 U301-D9 U301-F2 # VDDQ NET 'BULK_1V2' U301-F8 U301-G1 U301-G9 U301-J2 U301-J8 NET 'DIGITAL_2V5' U301-B1 U301-R9 # VPP NET 'DDR4_VREF_FPGA' U301-M1 # VREF NET 'GROUND' U301-B2 U301-E1 U301-E9 U301-G8 U301-K1 # VSS NET 'GROUND' U301-K9 U301-M9 U301-N1 U301-T1 NET 'GROUND' U301-A2 U301-A8 U301-C9 U301-D2 U301-D8 # VSSQ NET 'GROUND' U301-E3 U301-E8 U301-F1 U301-H1 U301-H9 # # U302 POWER AND GROUND # NET 'BULK_1V2' U302-B3 U302-B9 U302-D1 U302-G7 U302-J1 # VDD NET 'BULK_1V2' U302-J9 U302-L1 U302-L9 U302-R1 U302-T9 NET 'BULK_1V2' U302-A1 U302-A9 U302-C1 U302-D9 U302-F2 # VDDQ NET 'BULK_1V2' U302-F8 U302-G1 U302-G9 U302-J2 U302-J8 NET 'DIGITAL_2V5' U302-B1 U302-R9 # VPP NET 'DDR4_VREF_FPGA' U302-M1 # VREF NET 'GROUND' U302-B2 U302-E1 U302-E9 U302-G8 U302-K1 # VSS NET 'GROUND' U302-K9 U302-M9 U302-N1 U302-T1 NET 'GROUND' U302-A2 U302-A8 U302-C9 U302-D2 U302-D8 # VSSQ NET 'GROUND' U302-E3 U302-E8 U302-F1 U302-H1 U302-H9 # # BYPASS CAPACITORS FOR U301 # NET 'BULK_1V2' C301-1 C302-1 C303-1 C304-1 C305-1 NET 'BULK_1V2' C306-1 C307-1 C308-1 C309-1 C310-1 NET 'BULK_1V2' C311-1 C312-1 C313-1 C314-1 C315-1 NET 'BULK_1V2' C316-1 C317-1 NET 'GROUND' C301-2 C302-2 C303-2 C304-2 C305-2 NET 'GROUND' C306-2 C307-2 C308-2 C309-2 C310-2 NET 'GROUND' C311-2 C312-2 C313-2 C314-2 C315-2 NET 'GROUND' C316-2 C317-2 NET 'DIGITAL_2V5' C320-1 C321-1 C322-1 C323-1 C324-1 NET 'DIGITAL_2V5' C325-1 NET 'GROUND' C320-2 C321-2 C322-2 C323-2 C324-2 NET 'GROUND' C325-2 NET 'DDR4_VREF_FPGA' C327-1 C328-1 C329-1 NET 'GROUND' C327-2 C328-2 C329-2 # # BYPASS CAPACITORS FOR U302 # NET 'BULK_1V2' C331-1 C332-1 C333-1 C334-1 C335-1 NET 'BULK_1V2' C336-1 C337-1 C338-1 C339-1 C340-1 NET 'BULK_1V2' C341-1 C342-1 C343-1 C344-1 C345-1 NET 'BULK_1V2' C346-1 C347-1 NET 'GROUND' C331-2 C332-2 C333-2 C334-2 C335-2 NET 'GROUND' C336-2 C337-2 C338-2 C339-2 C340-2 NET 'GROUND' C341-2 C342-2 C343-2 C344-2 C345-2 NET 'GROUND' C346-2 C347-2 NET 'DIGITAL_2V5' C350-1 C351-1 C352-1 C353-1 C354-1 NET 'DIGITAL_2V5' C355-1 NET 'GROUND' C350-2 C351-2 C352-2 C353-2 C354-2 NET 'GROUND' C355-2 NET 'DDR4_VREF_FPGA' C357-1 C358-1 C359-1 NET 'GROUND' C357-2 C358-2 C359-2 # # FPGA DDR4 CONTROLLER TO DDR4 MEMORY CHIPS # ------ # # FPGA BANK 0 NO CONNECTION NET LIST # ------------------------------------------------ # # # INITIAL REV. 10-MAR-2023 # CURRENT REV. 13-MAR-2023 # # # THIS NET LIST HOLDS THE PINS IN THE FPGA BANK 0 # DDR CONTROLLER THAT HAVE NO CONNECTION WHEN THIS # DDR CONTROLLER IS USED WITH DDR4 MEMORY CHIPS. # # # # UN-USED PINS IN THE U1 FPGA'S BANK 0 # I.E. THE DDR CONTROLLER. # # THESE PINS ARE DECLARED AS "SINGLE PIN NETS". # # WE ARE USING BANK 0 PINS FOR THE FPGA'S DDR4 CONTROLLER # WITH 32 DATA BITS AND ONE RANK. MICROCHIP MAY CALL THIS # THE NORTH-NE OPTION 1. # # THESE BANK 0 PINS ARE USED WITH SOME OTHER DDR4 OPTIONS, E.G. # BUS WIDTHS > 32 BITS, NORTH-NW OPTION, AND OPTION 2. # # THIS NET LIST FILE HOLDS 10 PINS IN THE BANK 0 DDR MEMORY CONTROLLER. # NET 'NO_CONN_U1_PIN_AC16' U1-AC16 # DQ16 FOR NORTH_NW OPTION 1 & 2 NET 'NO_CONN_U1_PIN_AC23' U1-AC23 # DQ60 FOR NORTH_NW OPTION 1 & 2 NET 'NO_CONN_U1_PIN_AD23' U1-AD23 # CS1_B FOR NORTH-NE OPTION 2 NET 'NO_CONN_U1_PIN_AD26' U1-AD26 # BG1 FOR NORTH_NE OPTION 1 & 2 # DQ66 FOR NORTH-NW OPTION 1 & 2 NET 'NO_CONN_U1_PIN_AE27' U1-AE27 # DQS8 FOR NORTH-NW OPTION 1 & 2 # CK1 FOR NORTH-NE OPTION 2 NET 'NO_CONN_U1_PIN_AE28' U1-AE28 # DQS8_B FOR NORTH-NW OPTION 1 & 2 # CK1_B FOR NORTH-NE OPTION 2 NET 'NO_CONN_U1_PIN_AF20' U1-AF20 # DQ39 FOR NORTH-NW OPTION 1 & 2 NET 'NO_CONN_U1_PIN_AG25' U1-AG25 # DQ48 FOR NORTH-NW OPTION 1 & 2 # CKE1 FOR NORTH-NE OPTION 2 NET 'NO_CONN_U1_PIN_AH24' U1-AH24 # DQ47 FOR NORTH-NW OPTION 1 & 2 NET 'NO_CONN_U1_PIN_Y18' U1-Y18 # DQ24 FOR NORTH-NW OPTION 1 & 2 # # CPU DDR4 CONTROLLER TO DDR4 MEMORY CHIPS # ----- # # ADDRESS AND COMMAND SIGNALS NET LIST # --------------------------------------------- # # # INITIAL REV. 29-DEC-2022 # CURRENT REV. 14-MAR-2023 # # # THIS NET LIST HOLDS THE CONNECTIONS BETWEEN THE CPU'S DDR4 # CONTROLLER AND THE TWO DDR4 MEMORY CHIPS. THE CPU'S DDR4 # CONTROLLER USES PINS IN THE CPU HSIO BACK #6. # # THE DDR4 MEMORY CHIPS WHICH ARE ASSUMED TO BE MICRON # MT40A1G16 16 GBIT, 1 GIG ADDRESS BY 16 DATA BITS IN THE # 96 PIN BGA PACKAGE. # # U1 IS THE MPFS250T FPGA-CPU IN THE FCVG784 PACKAGE # # U401 IS THE MT40A1G16 SDRAM FOR DATA BITS 0:15 # U402 IS THE MT40A1G16 SDRAM FOR DATA BITS 16:31 # # # THE FOLLOWING SIGNALS HAVE EXTERNAL TERMINATION RESISTORS: # # ADRS0 THROUGH ADRS13, ADRS14_WE_B, ADRS15_CAS_B, # ADRS16_RAS_B, BA0, BA1, BG0, ODT, CLK_ENB, CS_B, # PAR_IN, ACT_B # # THIS IS 25 TERMINATION RESISTORS TO THE VTERM_DDR4_CPU SUPPLY. # # # THE CLK_DIR - CLK_CMP DIFFERENTIAL PAIR CLOCK SIGNAL # HAS AN EXTERNAL DIFFERENTIAL RESISTOR TERMINATOR. # # THIS IS 2 MORE TERMINATION RESISTORS. # # # THAT MAKES FOR A TOTAL OF 27 EXTERNAL TERMINATION RESISTORS # OF 39 OHMS EACH. # # # THE ALERT_B SIGNAL HAS AN EXTERNAL PULL-UP RESISTOR # TO THE 1V2 RAIL. # # THE RESET_B AND TEN SIGNALS HAVE AN EXTERNAL PULL-DOWN # RESISTORS TO GROUND. # # # THIS NET LIST FILE DEFINES: # # 30 PINS ON EACH MEMORY CHIP # 29 PINS ON THE DDR4 MEMORY CONTROLLER BANK 6 # # # START WITH THE ADDRESS AND CONTROL BUS THAT # GOES TO BOTH U401 AND U402. # NET 'DDR4_CPU_ADRS0' U1-V1 U401-P3 U402-P3 R409-2 NET 'DDR4_CPU_ADRS1' U1-V2 U401-P7 U402-P7 R410-2 NET 'DDR4_CPU_ADRS2' U1-Y1 U401-R3 U402-R3 R405-2 NET 'DDR4_CPU_ADRS3' U1-W1 U401-N7 U402-N7 R414-2 NET 'DDR4_CPU_ADRS4' U1-W3 U401-N3 U402-N3 R413-2 NET 'DDR4_CPU_ADRS5' U1-W4 U401-P8 U402-P8 R411-2 NET 'DDR4_CPU_ADRS6' U1-W5 U401-P2 U402-P2 R408-2 NET 'DDR4_CPU_ADRS7' U1-Y6 U401-R8 U402-R8 R407-2 NET 'DDR4_CPU_ADRS8' U1-W6 U401-R2 U402-R2 R404-2 NET 'DDR4_CPU_ADRS9' U1-Y5 U401-R7 U402-R7 R406-2 NET 'DDR4_CPU_ADRS10' U1-V9 U401-M3 U402-M3 R417-2 NET 'DDR4_CPU_ADRS11' U1-U9 U401-T2 U402-T2 R401-2 NET 'DDR4_CPU_ADRS12' U1-V7 U401-M7 U402-M7 R418-2 NET 'DDR4_CPU_ADRS13' U1-V8 U401-T8 U402-T8 R403-2 NET 'DDR4_CPU_ADRS14_WE_B' U1-T7 U401-L2 U402-L2 R420-2 NET 'DDR4_CPU_ADRS15_CAS_B' U1-U7 U401-M8 U402-M8 R419-2 NET 'DDR4_CPU_ADRS16_RAS_B' U1-U10 U401-L8 U402-L8 R423-2 NET 'DDR4_CPU_BA0' U1-U11 U401-N2 U402-N2 R412-2 NET 'DDR4_CPU_BA1' U1-W10 U401-N8 U402-N8 R415-2 NET 'DDR4_CPU_BG0' U1-U2 U401-M2 U402-M2 R416-2 NET 'DDR4_CPU_ODT' U1-V3 U401-K3 U402-K3 R425-2 NET 'DDR4_CPU_CLK_DIR' U1-Y3 U401-K7 U402-K7 NET 'DDR4_CPU_CLK_CMP' U1-Y2 U401-K8 U402-K8 NET 'DDR4_CPU_CLK_ENB' U1-V4 U401-K2 U402-K2 R424-2 NET 'DDR4_CPU_CS_B' U1-T4 U401-L7 U402-L7 R422-2 NET 'DDR4_CPU_ALERT_B' U1-V6 U401-P9 U402-P9 NET 'DDR4_CPU_PARITY' U1-U6 U401-T3 U402-T3 R402-2 NET 'DDR4_CPU_ACT_B' U1-U5 U401-L3 U402-L3 R421-2 NET 'DDR4_CPU_RESET_B' U1-U1 U401-P1 U402-P1 NET 'DDR4_CPU_TEN' U401-N9 U402-N9 # NOT DRIVEN ? # # NOTE: THE CPU (MSS) DDR4 CONTROLLER IN # THE MPFS250T DOES NOT APPEAR TO GENERATE # A TEN SIGNAL. MUST VERIFY. # TEN IS THE HIGH ACTIVE TEST ENABLE SIGNAL. # # # NOTE: THE ALERT_B, RESET_B, AND TEN SIGNALS # DO NOT HAVE TERMINATION RESISTORS BUT THE DO HAVE # PULL-UP OR PULL-DOWN RESISTORS. THESE CONNECTIONS # ARE MADE IN THE FILE: # # DDR4_CPU_BANK_6_POWER_AND_SUNDRY_NETS.TXT # # # NOTE: THE DDR4_CPU_CLK SIGNALS DO HAVE # DIFFERENTIAL TERMINATION RESISTORS. THESE # CONNECTIONS ARE MADE IN THE FILE: # # DDR4_CPU_BANK_6_POWER_AND_SUNDRY_NETS.TXT # # # NOW CONNECT THE TERMINATION RESISTORS TO THE # DDR4_VTERM_CPU SUPPLY AND CONNECT THE # BYPASS CAPACITORS FOR THIS SUPPLY TO IT AND # TO GROUND. # NET 'DDR4_VTERM_CPU' R401-1 R402-1 R403-1 R404-1 R405-1 NET 'DDR4_VTERM_CPU' R406-1 R407-1 R408-1 R409-1 R410-1 NET 'DDR4_VTERM_CPU' R411-1 R412-1 R413-1 R414-1 R415-1 NET 'DDR4_VTERM_CPU' R416-1 R417-1 R418-1 R419-1 R420-1 NET 'DDR4_VTERM_CPU' R421-1 R422-1 R423-1 R424-1 R425-1 NET 'DDR4_VTERM_CPU' C471-2 C472-2 C473-2 C474-2 C475-2 NET 'DDR4_VTERM_CPU' C476-2 C477-2 C478-2 C479-2 C480-2 NET 'DDR4_VTERM_CPU' C481-2 C482-2 C483-2 C484-2 NET 'GROUND' C471-1 C472-1 C473-1 C474-1 C475-1 NET 'GROUND' C476-1 C477-1 C478-1 C479-1 C480-1 NET 'GROUND' C481-1 C482-1 C483-1 C484-1 # # CPU DDR4 CONTROLLER TO DDR4 MEMORY CHIPS # ----- # DATA PATH NET LIST # --------------------------------------------- # # # INITIAL REV. 29-DEC-2022 # CURRENT REV. 8-MAR-2023 # # # THIS NET LIST HOLDS THE CONNECTIONS BETWEEN THE CPU'S DDR4 # CONTROLLER AND THE TWO DDR4 MEMORY CHIPS. THE CPU'S DDR4 # CONTROLLER USES PINS IN THE CPU HSIO BACK #6. # # THE DDR4 MEMORY CHIPS WHICH ARE ASSUMED TO BE MICRON # MT40A1G16 16 GBIT, 1 GIG ADDRESS BY 16 DATA BITS IN THE # 96 PIN BGA PACKAGE. # # U1 IS THE MPFS250T FPGA-CPU IN THE FCVG784 PACKAGE # # U401 IS THE MT40A1G16 SDRAM FOR DATA BITS 0:15 # U402 IS THE MT40A1G16 SDRAM FOR DATA BITS 16:31 # # # THIS NET LIST FILE DEFINES: # # 22 PINS ON EACH MEMORY CHIP # 44 PINS ON THE DDR4 MEMORY CONTROLLER BANK 6 # # # NOW THE DATA PATH TYPE SIGNALS D0:D15 TO U401 # NET 'DDR4_CPU_DQ0' U1-AB5 U401-G2 NET 'DDR4_CPU_DQ1' U1-AB4 U401-F7 NET 'DDR4_CPU_DQ2' U1-AA4 U401-H3 NET 'DDR4_CPU_DQ3' U1-AA3 U401-H7 NET 'DDR4_CPU_DQ4' U1-AA2 U401-H2 NET 'DDR4_CPU_DQ5' U1-AC4 U401-H8 NET 'DDR4_CPU_DQ6' U1-AC1 U401-J3 NET 'DDR4_CPU_DQ7' U1-AC2 U401-J7 NET 'DDR4_CPU_DQS0_DIR' U1-AB2 U401-G3 NET 'DDR4_CPU_DQS0_CMP' U1-AB1 U401-F3 NET 'DDR4_CPU_DM0_B' U1-AC3 U401-E7 NET 'DDR4_CPU_DQ8' U1-AB7 U401-A3 NET 'DDR4_CPU_DQ9' U1-AC6 U401-B8 NET 'DDR4_CPU_DQ10' U1-AC7 U401-C3 NET 'DDR4_CPU_DQ11' U1-AA5 U401-C7 NET 'DDR4_CPU_DQ12' U1-AB6 U401-C2 NET 'DDR4_CPU_DQ13' U1-AC8 U401-C8 NET 'DDR4_CPU_DQ14' U1-AA9 U401-D3 NET 'DDR4_CPU_DQ15' U1-AB9 U401-D7 NET 'DDR4_CPU_DQS1_DIR' U1-AA7 U401-B7 NET 'DDR4_CPU_DQS1_CMP' U1-AA8 U401-A7 NET 'DDR4_CPU_DM1_B' U1-AC9 U401-E2 # # NOW THE DATA PATH TYPE SIGNALS D16:D31 TO U402 # NET 'DDR4_CPU_DQ16' U1-AD6 U402-G2 NET 'DDR4_CPU_DQ17' U1-AE5 U402-F7 NET 'DDR4_CPU_DQ18' U1-AD5 U402-H3 NET 'DDR4_CPU_DQ19' U1-AD4 U402-H7 NET 'DDR4_CPU_DQ20' U1-AF5 U402-H2 NET 'DDR4_CPU_DQ21' U1-AE6 U402-H8 NET 'DDR4_CPU_DQ22' U1-AE2 U402-J3 NET 'DDR4_CPU_DQ23' U1-AD1 U402-J7 NET 'DDR4_CPU_DQS2_DIR' U1-AD3 U402-G3 NET 'DDR4_CPU_DQS2_CMP' U1-AE3 U402-F3 NET 'DDR4_CPU_DM2_B' U1-AE1 U402-E7 NET 'DDR4_CPU_DQ24' U1-AF4 U402-A3 NET 'DDR4_CPU_DQ25' U1-AF3 U402-B8 NET 'DDR4_CPU_DQ26' U1-AF1 U402-C3 NET 'DDR4_CPU_DQ27' U1-AG1 U402-C7 NET 'DDR4_CPU_DQ28' U1-AH2 U402-C2 NET 'DDR4_CPU_DQ29' U1-AH3 U402-C8 NET 'DDR4_CPU_DQ30' U1-AG5 U402-D3 NET 'DDR4_CPU_DQ31' U1-AG4 U402-D7 NET 'DDR4_CPU_DQS3_DIR' U1-AF2 U402-B7 NET 'DDR4_CPU_DQS3_CMP' U1-AG2 U402-A7 NET 'DDR4_CPU_DM3_B' U1-AH4 U402-E2 # # CPU DDR4 CONTROLLER TO DDR4 MEMORY CHIPS # ----- # # POWER SUPPLY AND SUNDRY NET LIST # --------------------------------------------- # # # INITIAL REV. 29-DEC-2022 # CURRENT REV. 1-DEC-2023 # # # THIS NET LIST HOLDS THE POWER AND GROUND CONNECTIONS # ON EACH MEMORY CHIP AND 2 SUNDRY PINS ON EACH OF # THESE CHIPS. # # THE DDR4 MEMORY CHIPS WHICH ARE ASSUMED TO BE MICRON # MT40A1G16 16 GBIT, 1 GIG ADDRESS BY 16 DATA BITS IN THE # 96 PIN BGA PACKAGE. # # U1 IS THE MPFS250T FPGA-CPU IN THE FCVG784 PACKAGE # # U401 IS THE MT40A1G16 SDRAM FOR DATA BITS 0:15 # U402 IS THE MT40A1G16 SDRAM FOR DATA BITS 16:31 # # # THE ZQ SIGNAL HAS AN EXTERNAL 240 OHM RESISTOR TO # GROUND - A SEPARATE RESISTOR FOR EACH OF THE 2 SDRAM CHIPS. # # # THIS FILE HAS 44 PIN ON EACH MEMORY CHIP # AND NO PINS ON THE DDR4 MEMORY CONTROLLER. # # # FOR THE 2 MEMORY CHIPS: # # THE ZQ REFERENCE RESISTORS # # THE CLOCK TERMINATION RESISTORS AND CAPACITORS # # THE ALERT_B PULL-UP RESISTOR # # THE RESET_B PULL-DOWN RESISTOR # # THE TEN PULL-DOWN RESISTOR # # THE UN-USED PIN ON EACH MEMORY CHIP # NET 'ZQ_REFERENCE_U401' U401-F9 R428-2 NET 'ZQ_REFERENCE_U402' U402-F9 R429-2 NET 'GROUND' R428-1 R429-1 NET 'DDR4_CPU_CLK_CMP' R426-2 NET 'DDR4_CPU_CLK_DIR' R427-2 NET 'DDR4_CPU_CLK_TERM' R426-1 R427-1 NET 'DDR4_CPU_CLK_TERM' C485-2 C486-2 NET 'BULK_1V2' C485-1 C486-1 NET 'DDR4_CPU_ALERT_B' R430-2 NET 'BULK_1V2' R430-1 NET 'DDR4_CPU_RESET_B' R431-2 NET 'GROUND' R431-1 NET 'DDR4_CPU_TEN' R432-2 NET 'GROUND' R432-1 NET 'NO_CONN_U401_PIN_T7' U401-T7 NET 'NO_CONN_U402_PIN_T7' U402-T7 # # U401 POWER AND GROUND # NET 'BULK_1V2' U401-B3 U401-B9 U401-D1 U401-G7 U401-J1 # VDD NET 'BULK_1V2' U401-J9 U401-L1 U401-L9 U401-R1 U401-T9 NET 'BULK_1V2' U401-A1 U401-A9 U401-C1 U401-D9 U401-F2 # VDDQ NET 'BULK_1V2' U401-F8 U401-G1 U401-G9 U401-J2 U401-J8 NET 'DIGITAL_2V5' U401-B1 U401-R9 # VPP NET 'DDR4_VREF_CPU' U401-M1 # VREF NET 'GROUND' U401-B2 U401-E1 U401-E9 U401-G8 U401-K1 # VSS NET 'GROUND' U401-K9 U401-M9 U401-N1 U401-T1 NET 'GROUND' U401-A2 U401-A8 U401-C9 U401-D2 U401-D8 # VSSQ NET 'GROUND' U401-E3 U401-E8 U401-F1 U401-H1 U401-H9 # # U402 POWER AND GROUND # NET 'BULK_1V2' U402-B3 U402-B9 U402-D1 U402-G7 U402-J1 # VDD NET 'BULK_1V2' U402-J9 U402-L1 U402-L9 U402-R1 U402-T9 NET 'BULK_1V2' U402-A1 U402-A9 U402-C1 U402-D9 U402-F2 # VDDQ NET 'BULK_1V2' U402-F8 U402-G1 U402-G9 U402-J2 U402-J8 NET 'DIGITAL_2V5' U402-B1 U402-R9 # VPP NET 'DDR4_VREF_CPU' U402-M1 # VREF NET 'GROUND' U402-B2 U402-E1 U402-E9 U402-G8 U402-K1 # VSS NET 'GROUND' U402-K9 U402-M9 U402-N1 U402-T1 NET 'GROUND' U402-A2 U402-A8 U402-C9 U402-D2 U402-D8 # VSSQ NET 'GROUND' U402-E3 U402-E8 U402-F1 U402-H1 U402-H9 # # BYPASS CAPACITORS FOR U401 # NET 'BULK_1V2' C401-1 C402-1 C403-1 C404-1 C405-1 NET 'BULK_1V2' C406-1 C407-1 C408-1 C409-1 C410-1 NET 'BULK_1V2' C411-1 C412-1 C413-1 C414-1 C415-1 NET 'BULK_1V2' C416-1 C417-1 NET 'GROUND' C401-2 C402-2 C403-2 C404-2 C405-2 NET 'GROUND' C406-2 C407-2 C408-2 C409-2 C410-2 NET 'GROUND' C411-2 C412-2 C413-2 C414-2 C415-2 NET 'GROUND' C416-2 C417-2 NET 'DIGITAL_2V5' C420-1 C421-1 C422-1 C423-1 C424-1 NET 'DIGITAL_2V5' C425-1 NET 'GROUND' C420-2 C421-2 C422-2 C423-2 C424-2 NET 'GROUND' C425-2 NET 'DDR4_VREF_CPU' C427-1 C428-1 C429-1 NET 'GROUND' C427-2 C428-2 C429-2 # # BYPASS CAPACITORS FOR U402 # NET 'BULK_1V2' C431-1 C432-1 C433-1 C434-1 C435-1 NET 'BULK_1V2' C436-1 C437-1 C438-1 C439-1 C440-1 NET 'BULK_1V2' C441-1 C442-1 C443-1 C444-1 C445-1 NET 'BULK_1V2' C446-1 C447-1 NET 'GROUND' C431-2 C432-2 C433-2 C434-2 C435-2 NET 'GROUND' C436-2 C437-2 C438-2 C439-2 C440-2 NET 'GROUND' C441-2 C442-2 C443-2 C444-2 C445-2 NET 'GROUND' C446-2 C447-2 NET 'DIGITAL_2V5' C450-1 C451-1 C452-1 C453-1 C454-1 NET 'DIGITAL_2V5' C455-1 NET 'GROUND' C450-2 C451-2 C452-2 C453-2 C454-2 NET 'GROUND' C455-2 NET 'DDR4_VREF_CPU' C457-1 C458-1 C459-1 NET 'GROUND' C457-2 C458-2 C459-2 # # CPU DDR4 CONTROLLER TO DDR4 MEMORY CHIPS # ----- # # CPU (MSS) BANK 6 NO CONNECTION NET LIST # ----------------------------------------------- # # # INITIAL REV. 29-DEC-2022 # CURRENT REV. 8-MAR-2023 # # # THIS NET LIST HOLDS THE PINS IN THE CPU (MSS) # BANK 6 DDR CONTROLLER THAT HAVE NO CONNECTION # WHEN THIS DDR CONTROLLER IS USED WITH DDR4 MEMORY CHIPS. # # # # UN-USED PINS IN THE U1 CPU'S BANK 6 # I.E. THE DDR CONTROLLER. # # THESE PINS ARE DECLARED AS "SINGLE PIN NETS". # # THIS NET LIST FILE HOLDS 15 PINS IN THE BANK 6 DDR MEMORY CONTROLLER. # # # PINS FOR A SECOND RANK OF MEMORY CHIPS. # NET 'NO_CONN_U1_PIN_U4' U1-U4 # CPU DDR4 CONTROLLER BG1 PIN U4 NET 'NO_CONN_U1_PIN_T5' U1-T5 # CPU DDR4 CONTROLLER ODT1 PIN T5 NET 'NO_CONN_U1_PIN_W8' U1-W8 # CPU DDR4 CONTROLLER CLK1_P PIN W8 NET 'NO_CONN_U1_PIN_W9' U1-W9 # CPU DDR4 CONTROLLER CLK1_N PIN W9 NET 'NO_CONN_U1_PIN_T2' U1-T2 # CPU DDR4 CONTROLLER CKE1 PIN T2 NET 'NO_CONN_U1_PIN_T3' U1-T3 # CPU DDR4 CONTROLLER CS1_N PIN T3 # # PIN FOR A ERROR CHECKING CORRECTING MEMORY SYSTEM. # NET 'NO_CONN_U1_PIN_AB10' U1-AB10 # CPU DDR4 CONTROLLER DQ0_ECC PIN AB10 NET 'NO_CONN_U1_PIN_AB11' U1-AB11 # CPU DDR4 CONTROLLER DQ1_ECC PIN AB11 NET 'NO_CONN_U1_PIN_AA10' U1-AA10 # CPU DDR4 CONTROLLER DQ2_ECC PIN AA10 NET 'NO_CONN_U1_PIN_Y11' U1-Y11 # CPU DDR4 CONTROLLER DQ3_ECC PIN Y11 NET 'NO_CONN_U1_PIN_Y7' U1-Y7 # CPU DDR4 CONTROLLER DQSP_ECC PIN Y7 NET 'NO_CONN_U1_PIN_Y8' U1-Y8 # CPU DDR4 CONTROLLER DQSN_ECC PIN Y8 NET 'NO_CONN_U1_PIN_W11' U1-W11 # CPU DDR4 CONTROLLER DQM_ECC/DBI_ECC PIN W11 # # OTHER UN-USED PINS IN THE CPU DDR CONTROLLER BANK 6 # NET 'NO_CONN_U1_PIN_V11' U1-V11 # CPU DDR4 CONTROLLER MSS_DDR3_WE_N NET 'NO_CONN_U1_PIN_Y10' U1-Y10 # CPU DDR4 CONTROLLER MSS_DDR_VREF_IN # # FPGA DDR4 REFERENCE AND TERMINATOR # ------ # # POWER SUPPLY NET LIST # ------------------------------------------ # # # INITIAL REV. 13-MAR-2023 # CURRENT REV. 15-NOV-2023 # # # THIS NET LIST HOLDS THE REFERENCE AND TERMINATOR # POWER SUPPLY NETS FOR THE FPGA DDR4 MEMORY. # ------ # # THESE NETS INVOLVE REFERENCE DESIGNATORS STARTING AT 1921. # # # AUX POWER VIN TO THIS POWER SUPPLY CHIP: # NET 'BULK_3V3' U1921-10 C1921-1 C1922-2 NET 'BULK_3V3' U1921-7 # ENABLE PIN NET 'GROUND' C1921-2 C1922-1 # # VLD0 INPUT POWER TO THIS POWER SUPPLY CHIP: # NET 'BULK_1V2' U1921-2 C1923-1 C1924-1 NET 'GROUND' C1923-2 C1924-2 # # TERMINATOR POWER OUTPUT FROM THIS POWER SUPPLY CHIP: # AND ITS REMOTE SENSE INPUT: NET 'DDR4_VTERM_FPGA' U1921-3 C1925-1 C1926-2 # TERMINATOR OUTPUT POWER NET 'GROUND' C1925-2 C1926-1 NET 'DDR4_VTERM_FPGA' U1921-5 # REMOTE SENSE INPUT # # REFERENCE OUTPUT FROM THIS POWER SUPPLY CHIP: # NET 'DDR4_VREF_FPGA' U1921-6 C1927-1 # REFERENCE OUTPUT NET 'GROUND' C1927-2 # # REFERENCE INPUT TO THIS POWER SUPPLY CHIP: # NET 'BULK_1V2' R1921-2 NET 'REF_TO_FPGA_TERM_SUPPLY' R1921-1 R1922-2 C1928-2 U1921-1 NET 'GROUND' R1922-1 C1928-1 # # GROUND PINS ON THE FPGA DDR4 TERM REF POWER SUPPLY CHIP # NET 'GROUND' U1921-4 U1921-8 NET 'GROUND' U1921-11 U1921-12 U1921-13 U1921-14 # # VOLTAGE MONITOR FOR THE FPGA DDR4 TERM REF POWER SUPPLY # NET 'DDR4_VTERM_FPGA' R1923-2 NET 'VMON_FPGA_DDR4_TERM' R1923-1 C1929-1 NET 'GROUND' C1929-2 # # UN-USED PIN ON THE POWER SUPPLY CHIP # NET 'NO_CONN_U1921_PIN_9' U1921-9 # POWER GOOD OD OUTPUT PIN # # CPU DDR4 REFERENCE AND TERMINATOR # ----- # # POWER SUPPLY NET LIST # ----------------------------------------- # # # INITIAL REV. 13-MAR-2023 # CURRENT REV. 15-NOV-2023 # # # THIS NET LIST HOLDS THE REFERENCE AND TERMINATOR # POWER SUPPLY NETS FOR THE CPU DDR4 MEMORY. # ----- # # THESE NETS INVOLVE REFERENCE DESIGNATORS STARTING AT 1941. # # # AUX POWER VIN TO THIS POWER SUPPLY CHIP: # NET 'BULK_3V3' U1941-10 C1941-1 C1942-2 NET 'BULK_3V3' U1941-7 # ENABLE PIN NET 'GROUND' C1941-2 C1942-1 # # VLD0 INPUT POWER TO THIS POWER SUPPLY CHIP: # NET 'BULK_1V2' U1941-2 C1943-1 C1944-1 NET 'GROUND' C1943-2 C1944-2 # # TERMINATOR POWER OUTPUT FROM THIS POWER SUPPLY CHIP: # AND ITS REMOTE SENSE INPUT: NET 'DDR4_VTERM_CPU' U1941-3 C1945-1 C1946-2 # TERMINATOR OUTPUT POWER NET 'GROUND' C1945-2 C1946-1 NET 'DDR4_VTERM_CPU' U1941-5 # REMOTE SENSE INPUT # # REFERENCE OUTPUT FROM THIS POWER SUPPLY CHIP: # NET 'DDR4_VREF_CPU' U1941-6 C1947-1 # REFERENCE OUTPUT NET 'GROUND' C1947-2 # # REFERENCE INPUT TO THIS POWER SUPPLY CHIP: # NET 'BULK_1V2' R1941-2 NET 'REF_TO_CPU_TERM_SUPPLY' R1941-1 R1942-2 C1948-2 U1941-1 NET 'GROUND' R1942-1 C1948-1 # # GROUND PINS ON THE CPU DDR4 TERM REF POWER SUPPLY CHIP # NET 'GROUND' U1941-4 U1941-8 NET 'GROUND' U1941-11 U1941-12 U1941-13 U1941-14 # # VOLTAGE MONITOR FOR THE CPU DDR4 TERM REF POWER SUPPLY # NET 'DDR4_VTERM_CPU' R1943-2 NET 'VMON_CPU_DDR4_TERM' R1943-1 C1949-1 NET 'GROUND' C1949-2 # # UN-USED PIN ON THE POWER SUPPLY CHIP # NET 'NO_CONN_U1941_PIN_9' U1941-9 # POWER GOOD OD OUTPUT PIN # # PMT ADC HIGH SPEED SERIAL LINKS TO # THE FPGA HIGH SPEED SERIAL TRANSCEIVERS # ----------------------------------------- # # # ORIGINAL REV. 29-DEC-2022 # CURRENT REV. 22-FEB-2022 # # # THIS NET LIST FILE GIVES THE FOUR JESD204B LINKS FROM # THE PMT ADC TO FOUR HIGH-SPEED TRANSCEIVERS ON THE FPGA. # # # ADC HIGH-SPEED SERIAL DATA INPUT TO THE FPGA: # --------------------------------------------- # # THE HIGH-SPEED SERIAL DATA FROM THE PMT ADC IS CARRIED # ON FOUR JESD204B LINKS. THESE LINKS ARE RECEIVED BY # FOUR HIGH-SPEED SERIAL RECEIVERS IN THE FPGA-CPU. # FOR PCB ROUTING IT LOOKS BEST TO USE THE RECEIVERS IN # HIGH-SPEED TRANSCEIVER NUMBER 1. # # ADC SEROUT0_DIR D2 TO FPGA XCVR_1_RX0_DIR F26 # ADC SEROUT0_CMP D1 TO FPGA XCVR_1_RX0_CMP F25 # # ADC SEROUT1_DIR E2 TO FPGA XCVR_1_RX1_DIR H26 # ADC SEROUT1_CMP E1 TO FPGA XCVR_1_RX1_CMP H25 # # ADC SEROUT2_DIR F2 TO FPGA XCVR_1_RX2_DIR K26 # ADC SEROUT2_CMP F1 TO FPGA XCVR_1_RX2_CMP K25 # # ADC SEROUT3_DIR G2 TO FPGA XCVR_1_RX3_DIR N28 # ADC SEROUT3_CMP G1 TO FPGA XCVR_1_RX3_CMP N27 # # THIS ROUTING DOES NOT HAVE ANY LANE CROSS-OVERS # AND THE PINS OF XCVR_1 LOOK MORE ISOLATED THAN # THE PINS OF XCVR_0. # NET 'ADC_SEROUT0_DIR' C671-2 # ADC LANE 0 OUT DIR NET 'FPGA_XCVR_1_RX0_DIR' C671-1 U1-F26 # FPGA XCVR_1_RX0_DIR NET 'ADC_SEROUT0_CMP' C672-2 # ADC LANE 0 OUT CMP NET 'FPGA_XCVR_1_RX0_CMP' C672-1 U1-F25 # FPGA XCVR_1_RX0_CMP NET 'ADC_SEROUT1_DIR' C673-2 # ADC LANE 1 OUT DIR NET 'FPGA_XCVR_1_RX1_DIR' C673-1 U1-H26 # FPGA XCVR_1_RX1_DIR NET 'ADC_SEROUT1_CMP' C674-2 # ADC LANE 1 OUT CMP NET 'FPGA_XCVR_1_RX1_CMP' C674-1 U1-H25 # FPGA XCVR_1_RX1_CMP NET 'ADC_SEROUT2_DIR' C675-2 # ADC LANE 2 OUT DIR NET 'FPGA_XCVR_1_RX2_DIR' C675-1 U1-K26 # FPGA XCVR_1_RX2_DIR NET 'ADC_SEROUT2_CMP' C676-2 # ADC LANE 2 OUT CMP NET 'FPGA_XCVR_1_RX2_CMP' C676-1 U1-K25 # FPGA XCVR_1_RX2_CMP NET 'ADC_SEROUT3_DIR' C677-2 # ADC LANE 3 OUT DIR NET 'FPGA_XCVR_1_RX3_DIR' C677-1 U1-N28 # FPGA XCVR_1_RX3_DIR NET 'ADC_SEROUT3_CMP' C678-2 # ADC LANE 3 OUT CMP NET 'FPGA_XCVR_1_RX3_CMP' C678-1 U1-N27 # FPGA XCVR_1_RX3_CMP # # POWER AND GROUND CONNECTIONS TO THE U1 FPGA # WHICH IS A: MPFS250T-1FCVG784I # # # ORIGINAL REV. 17-NOV-2022 # CURRENT REV. 1-DEC-2023 # # # THIS NET LIST FILE INCLUDES: # # - ALL POWER AND GROUND CONNECTIONS TO THE U1 FPGA/CPU # # - AND THE "TIE-OFF" RESISTORS FOR THE POWER PINS OF THE UN-USED BANKS # # # # FPGA/CPU CORE POWER PINS: # --------------------------- # # # VDD CORE SUPPLY 1.00 / 1.05 V 23 PINS # NET 'CORE_1V05' U1-M15 U1-M17 U1-M19 U1-M21 U1-N16 NET 'CORE_1V05' U1-N18 U1-N20 U1-N22 U1-P15 U1-P17 NET 'CORE_1V05' U1-P19 U1-P21 U1-R14 U1-R16 U1-R20 NET 'CORE_1V05' U1-R22 U1-T15 U1-T17 U1-T19 U1-T21 NET 'CORE_1V05' U1-U14 U1-U16 U1-U20 # # VDD18 PROGRAMMING AND HSIO BANKS AUX 1.8 V 10 PINS # NET 'FPGA_1V8' U1-U18 U1-U22 U1-V13 U1-V15 U1-V17 NET 'FPGA_1V8' U1-V19 U1-V21 U1-W12 U1-W13 U1-W16 # # VDD25 PLL AND PNVM SUPPLY 2.5 V 5 PINS # NET 'ANALOG_2V5' U1-K22 U1-L12 U1-R18 U1-U12 U1-W23 # # # HIGH-SPEED SERIAL TRANSCEIVER POWER PINS: # -------------------------------------------- # # # XCVR_VREF XCVR REFERENCE SUPPLY 0.9 / 1.25 V 2 PINS # # XCVR_VREF IS NOT USED - IT IS TIED-OFF BELOW. # NET 'XCVR_VREF' U1-G24 U1-H23 # # VDD_XCVR_CLK XCVR REF CLK SUPPLY 2.5 / 3.3 V 4 PINS # NET 'ANALOG_2V5' U1-G25 U1-K23 U1-P23 U1-W25 # # VDDA25 XCVR PLL SUPPLY 2.5 V 4 PINS # NET 'ANALOG_2V5' U1-J25 U1-M23 U1-T23 U1-U25 # #VDDA XCVR TX/RX LANES SUPPLY 1.0 / 1.05 V 10 PINS # NET 'XCVR_1V05' U1-H27 U1-K27 U1-L25 U1-M27 U1-N25 NET 'XCVR_1V05' U1-P27 U1-R25 U1-T27 U1-V27 U1-Y27 # # # IO BANK POWER SUPPLY PINS: # --------------------------- # # # VDDI0 FPGA HSIO BANK 0 1.2 / 1.35 / 1.5 / 1.8 V 10 PINS # NET 'BULK_1V2' U1-AA21 U1-AB18 U1-AC25 U1-AD22 U1-AE19 NET 'BULK_1V2' U1-AF16 U1-AF26 U1-AG23 U1-AH20 U1-W18 # # VDDI1 FPGA GPIO BANK 1 1.2/1.5/1.8/2.5/3.3 V 11 PINS # NET 'BULK_3V3' U1-A1 U1-A11 U1-B8 U1-C5 U1-D12 NET 'BULK_3V3' U1-D2 U1-E9 U1-F6 U1-G13 U1-H10 NET 'BULK_3V3' U1-K14 # # VDDI2 MSS I/O BANK 2 1.2/1.5/1.8/2.5/3.3 V 3 PINS # NET 'BULK_3V3' U1-L1 U1-L11 U1-M8 # # VDDI3 JTAG BANK 1.8 / 2.5 / 3.3 V 2 PINS # NET 'BULK_3V3' U1-K11 U1-L15 # # VDDI4 MSS I/O BANK 4 1.2/1.5/1.8/2.5/3.3 V 2 PINS # # VDDI4 IS NOT USED - IT IS TIED-OFF BELOW. # NET 'FPGA_VDDI4' U1-N5 U1-P2 # # VDDI5 MSS SGMII BANK 5 2.5 / 3.3 V 2 PINS # NET 'BULK_3V3' U1-R9 U1-T11 # # VDDI6 MSS DDR BANK 6 1.2 / 1.5 / 1.6 V 11 PINS # NET 'BULK_1V2' U1-AA1 U1-AA11 U1-AB8 U1-AC5 U1-AD2 NET 'BULK_1V2' U1-AG3 U1-T6 U1-U3 U1-V10 U1-W7 NET 'BULK_1V2' U1-Y4 # # VDDI7 FPGA GPIO BANK 7 1.2/1.5/1.8/2.5/3.3 V 3 PINS # NET 'BULK_3V3' U1-G3 U1-J7 U1-K4 # # VDDI8 FPGA HSIO BANK 8 1.2 / 1.35 / 1.5 / 1.8 V 8 PINS # # VDDI8 IS NOT USED - IT IS TIED-OFF BELOW. # NET 'FPGA_VDDI8' U1-AA16 U1-AC15 U1-AD12 U1-AE9 U1-AF6 NET 'FPGA_VDDI8' U1-AG13 U1-AH10 U1-W14 # # VDDI9 FPGA GPIO BANK 9 1.2/1.5/1.8/2.5/3.3 V 10 PINS # NET 'FPGA_1V8' U1-A21 U1-B18 U1-C15 U1-C25 U1-D22 NET 'FPGA_1V8' U1-E19 U1-F16 U1-H20 U1-J17 U1-J22 # # # IO BANK AUXILIARY POWER SUPPLY PINS: # ------------------------------------- # # # VDDAUX1 FPGA GPIO BANK 1 2.5 / 3.3 V 3 PINS # NET 'BULK_3V3' U1-K13 U1-L14 U1-L16 # # VDDAUX2 MSS BANK 2 2.5 / 3.3 V 2 PINS # NET 'BULK_3V3' U1-N12 U1-P13 # # VDDAUX4 MSS BANK 4 2.5 / 3.3 V 2 PINS # # VDDAUX4 IS NOT USED - IT IS TIED-OFF BELOW. # NET 'FPGA_VDDAUX4' U1-R12 U1-T13 # # VDDAUX7 FPGA GPIO BANK 7 2.5 / 3.3 V 2 PINS # NET 'BULK_3V3' U1-M13 U1-N14 # # VDDAUX9 FPGA GPIO BANK 9 2.5 / 3.3 V 4 PINS # NET 'DIGITAL_2V5' U1-K19 U1-L18 U1-L20 U1-L22 # # # FPGA GROUND PINS: # ----------------- # NET 'GROUND' U1-AA24 U1-AA25 U1-AA26 U1-AB26 U1-AB27 NET 'GROUND' U1-AB28 U1-D26 U1-D27 U1-D28 U1-E24 NET 'GROUND' U1-E25 U1-E26 U1-F24 U1-F27 U1-F28 NET 'GROUND' U1-G26 U1-H24 U1-H28 U1-J26 U1-K24 NET 'GROUND' U1-K28 U1-L26 U1-M24 U1-M28 U1-N26 NET 'GROUND' U1-P24 U1-P28 U1-R26 U1-T24 U1-T28 NET 'GROUND' U1-U26 U1-V23 U1-V24 U1-V28 U1-W24 NET 'GROUND' U1-W26 U1-Y24 U1-Y28 U1-A16 U1-A26 NET 'GROUND' U1-A28 U1-A6 U1-AA6 U1-AB13 U1-AB23 NET 'GROUND' U1-AB3 U1-AC10 U1-AC20 U1-AD17 U1-AD27 NET 'GROUND' U1-AD7 U1-AE14 U1-AE24 U1-AE4 U1-AF11 NET 'GROUND' U1-AF21 U1-AG18 U1-AG8 U1-AH1 U1-AH15 NET 'GROUND' U1-AH25 U1-AH28 U1-AH5 U1-B13 U1-B23 NET 'GROUND' U1-B3 U1-C10 U1-C20 U1-D17 U1-D7 NET 'GROUND' U1-E14 U1-E4 U1-F1 U1-F11 U1-F21 NET 'GROUND' U1-G18 U1-G8 U1-H15 U1-H5 U1-J2 NET 'GROUND' U1-K9 U1-L13 U1-L17 U1-L19 U1-L21 NET 'GROUND' U1-L6 U1-M12 U1-M14 U1-M16 U1-M18 NET 'GROUND' U1-M20 U1-M22 U1-M3 U1-N10 U1-N13 NET 'GROUND' U1-N15 U1-N17 U1-N19 U1-N21 U1-P12 NET 'GROUND' U1-P14 U1-P16 U1-P18 U1-P20 U1-P22 NET 'GROUND' U1-P7 U1-R13 U1-R15 U1-R17 U1-R19 NET 'GROUND' U1-R21 U1-R4 U1-T1 U1-T12 U1-T14 NET 'GROUND' U1-T16 U1-T18 U1-T20 U1-T22 U1-U13 NET 'GROUND' U1-U15 U1-U17 U1-U19 U1-U21 U1-U8 NET 'GROUND' U1-V12 U1-V14 U1-V16 U1-V18 U1-V20 NET 'GROUND' U1-V22 U1-V5 U1-W2 U1-Y9 # # # UN-USED BANK TIE-OFF RESISTORS: # ------------------------------------- # #### TIE-OFF BANK #4 I/O SUPPLY AND AUX SUPPLY PINS #### NET 'FPGA_VDDI4' R1354-2 # TIE-OFF BANK #4 I/O SUPPLY NET 'FPGA_VDDAUX4' R1355-2 # TIE-OFF BANK #4 AUX SUPPLY NET 'GROUND' R1354-1 R1355-1 # GROUND ANCHOR THE TIE-OFF RESISTORS #### TIE-OFF BANK #8 I/O SUPPLY PINS #### NET 'FPGA_VDDI8' R1356-2 # TIE-OFF BANK #4 I/O SUPPLY NET 'GROUND' R1356-1 # GROUND ANCHOR THE TIE-OFF RESISTOR #### TIE-OFF XCVR REFERENCE SUPPLY PINS #### #### #### #### XCVR_REF IS ONLY USED WITH #### #### SINGLE ENDED XCVR REFERENCE CLOCKS #### #### I.E. ONLY USED BY THE FOOLISH #### NET 'XCVR_VREF' R1357-1 C1351-1 # TIE-OFF THE UNUSED XCVR_REF PINS NET 'GROUND' R1357-2 C1351-2 # GROUND ANCHOR THE TIE-OFF RES & CAP # # DISCO-KRAKEN NET LIST FILE # # FPGA BYPASS CAPS AND POWER FILTERS # --------------------------------------- # # # INITIAL REV. 16-NOV-2022 # CURRENT REV. 30-NOV-2023 # # # THIS NET LIST HOLDS THE NETS FOR: # # - FPGA LC POWER FILTERS # # - FPGA BYPASS CAPACITORS # # # CORE POWER TO THE FPGA/CPU 1V05: # ------------------------------------ # NET 'BULK_1V05' L101-1 # BULK_1V05 POWER INTO FILTER NET 'CORE_1V05' L101-2 # FILTERED CORE POWER NET 'CORE_1V05' C101-2 C102-2 # CORE TANTALUM BYPASS NET 'GROUND' C101-1 C102-1 # TANT BYPASS CAP GROUNDS NET 'CORE_1V05' C103-1 C104-1 C105-1 C106-1 # CORE 22 UFD BYPASS NET 'GROUND' C103-2 C104-2 C105-2 C106-2 # BYPASS CAP GROUNDS # # FPGA_1V8 SUPPLY FOR: PROGRAMMING, HSIO AUX, AND BANK #9 I/O # # THE FPGA_1V8 SUPPLY COMES FROM THE BULK_1V8 SUPPLY VIA L103 # ------------------------------------------------------------------ # NET 'BULK_1V8' L103-2 # BULK_1V8 POWER INTO THE FILTER NET 'FPGA_1V8' L103-1 # FILTERED POWER TO FPGA: PROG, HSIO_AUX, BANK #9 # # TRANSCEIVER 1V05 ANALOG POWER: # ---------------------------------- # NET 'BULK_1V05' L102-1 # BULK_1V05 POWER INTO FILTER NET 'XCVR_1V05' L102-2 # FILTERED TRANSCEIVER 1V05 ANALOG POWER # # 2V5 POWER TO THE FPGA/CPU AND TO THE DDR4 MEMORY: # --------------------------------------------------- # # ANALOG_2V5 FOR: FPGA_PLL_2V5, XCVR_PLL_2V5, & XCVR_CLK SUPPLIES NET 'BULK_2V5' L104-2 # BULK_2V5 POWER INTO FILTER NET 'ANALOG_2V5' L104-1 # FILTERED ANALOG_2V5 POWER # DIGITAL_2V5 FOR: DDR4 MEMORY PRECHARGE & BANK #9 AUX SUPPLIES NET 'BULK_2V5' L105-2 # BULK_2V5 POWER INTO FILTER NET 'DIGITAL_2V5' L105-1 # FILTERED ANALOG_2V5 POWER # # BANK 0 FPGA DDR4 MEMORY BULK_1V2: # --------------------------------------- # NET 'BULK_1V2' C201-1 C202-1 # BANK 0 22 UFD BYPASS NET 'GROUND' C201-2 C202-2 # BYPASS CAP GROUNDS NET 'BULK_1V2' C203-1 C204-1 # BANK 0 2.2 UFD BYPASS NET 'GROUND' C203-2 C204-2 # BYPASS CAP GROUNDS # # BANK 6 CPU DDR4 MEMORY BULK_1V2: # -------------------------------------- # NET 'BULK_1V2' C221-1 C222-1 # BANK 0 22 UFD BYPASS NET 'GROUND' C221-2 C222-2 # BYPASS CAP GROUNDS NET 'BULK_1V2' C223-1 C224-1 # BANK 0 2.2 UFD BYPASS NET 'GROUND' C223-2 C224-2 # BYPASS CAP GROUNDS # # SFP CONNECTOR & CAGE PIN NET LIST # ------------------------------------- # # # ORIGINAL REV. 23-FEB-2023 # CURRENT REV. 26-DEC-2023 # # # THIS NET LIST FILE ASSIGNS NET NAMES AND MAKES # CONNECTIONS TO ALL PINS ON THE SFP CONNECTOR AND # THE SFP CAGE. # # NOTE: CURRENTLY (11-DEC-2023) MY UNDERSTANDING IS THAT # ANY/ALL SFP MODULES THAT ARE USED WITH THE DK BOARD # DO INCLUDE THEIR OWN AC COUPLING CAPACITORS. # # THUS EXTERNAL AC COUPLING CAPS ON THE DK BOARD ITSELF # HAVE NOT BEEN INCLUDED IN THE DK DESIGN FOR EITHER # RX OR TX CHANNEL FOR EITHER THE TIMING OR ETHERNET # SFP MODULES. # # # THIS NET LIST FILE INCLUDES MOST OF THE CONNECTIONS TO THE # PCA9546A I2C BUS FAN-OUT CHIP. THIS I2C FAN-OUT IS USED # TO ALLOW THE I2C CONTROLLER #0 IN THE FPGA/CPU TO TALK TO: # BOTH OF THE SFP MODULES ON THE DK AND TO THE AD9546 # TIMING GENERATOR. THERE IS AN UN-USED 4TH PORT ON THIS # FAN-OUT (PORT #3) WHERE IT CAN BE LEFT PARKED TO PROVIDE # A LAYER OF ISOLATION AND PROTECTION TO IMPORTANT CONTROL # REGISTERS, E.G. IN THE TIMING GENERATOR. # # THIS NET LIST FILE INCLUDES MANY CONNECTIONS TO "FLOATING" # PINS ON THE FPGA/CPU. THE FLOATING PIN CONNECTIONS ARE # ALL LISTED TOGETHER AT THE END OF THIS NET LIST FILE. # THESE FLOATING PINS ON THE FPGA/CPU ARE ASSIGNED TO # SPECIFIC PHYSICAL PINS IN THE NET LIST FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # # NOTE: TWO SECTION OF THE U1602 QUAD NAND ARE USED FOR # FUNCTIONS THAT ARE NOT DIRECTLY RELATED TO THE # SFP MODULES: U1602 4,5,6 IS USED TO MAKE THE # DK_CPU_IS_SANE_B SIGNAL THAT IS USED BY THE # EMERGENCY RESCUE CIRCUITS AND U1602 8,9,10 # IS USED TO MAKE A SPARE RUN SIGNAL IN THE # STARTUP AND RESETS NET LISTS. # # # TIMING SFP J13 RX AND TX DATA CONNECTIONS WITH NO EXTERNAL AC COUPLING CAPS # ------------------------------------------------------------------------------------ # # SFP_TIME_RD_DIR J13-13 # RECEIVER DIR DATA OUTPUT TO TIME GEN REF A INPUT DIR # SFP_TIME_RD_CMP J13-12 # RECEIVER CMP DATA OUTPUT TO TIME GEN REF A INPUT CMP # # THE TIMING SFP RECEIVER OUTPUT IS CONNECTED TO THE # TIMING GENERATOR REFERENCE A INPUT. THIS CONNECTION # IS MADE IN THE TIMING_GENERATOR_NETS.TXT FILE. # SFP_TIME_TD_DIR J13-18 # TRANSMITTER DIR DATA INPUT FROM TIME GEN OUTPUT 0-C DIR # SFP_TIME_TD_CMP J13-19 # TRANSMITTER CMP DATA INPUT FROM TIME GEN OUTPUT 0-C CMP # # THE TIMING SFP TRANSMITTER INPUT IS CONNECTED TO THE # TIMING GENERATOR OUTPUT 0-C. THIS CONNECTION # IS MADE IN THE TIMING_GENERATOR_NETS.TXT FILE. # # ETHERNET SFP J14 RX AND TX DATA CONNECTIONS WITH NO EXTERNAL AC COUPLING CAPS # -------------------------------------------------------------------------------------- # NET 'SFP_ENET_RD_DIR' U1-T26 # RECEIVER DIR DATA OUTPUT TO FPGA XCVR_0_RX_1_DIR NET 'SFP_ENET_RD_CMP' U1-T25 # RECEIVER CMP DATA OUTPUT TO FPGA XCVR_0_RX_1_CMP # THE ENET SFP RECEIVER OUTPUT IS ROUTED TO THE # XCVR_0 RX_1 INPUT ON THE FPGA/CPU. # XCVR_0_RX_1_DIR IS PIN T26 # XCVR_0_RX_1_CMP IS PIN T25 NET 'SFP_ENET_TD_DIR' U1-U28 # TRANSMITTER DIR DATA INPUT FROM FPGA XCVR_0_TX_1_DIR NET 'SFP_ENET_TD_CMP' U1-U27 # TRANSMITTER CMP DATA INPUT FROM FPGA XCVR_0_TX_1_CMP # THE ENET SFP TRANSMITTER INPUT IS ROUTED FROM # THE XCVR_0 TX_1 OUTPUT OF THE FPGA/CPU. # XCVR_0_TX_1_DIR IS PIN U28 # XCVR_0_TX_1_CMP IS PIN U27 # # PULL-UP RESISTORS AND CONNECTIONS TO: TX_FAULT, MOD_PRESENT, RX_LOSS # ------------------------------------------------------------------------- # # THESE 3 PINS ARE OUTPUTS FROM EACH SFP MODULE ARE ROUTED TO # "FLOATING" GPIO INPUT PINS ON THE FPGA/CPU. ALL OF THE # CONNECTIONS IN THIS NET LIST FILES THAT ARE MADE TO FLOATING # PINS ON THE FPGA/CPU ARE SUMMERIZED IN A SECTION BELOW. # # THE ACTUAL ASSIGNMENT OF THESE SIGNALS TO A PHYSICAL PINS # ON THE FPGA/CPU IS MADE IN THE NET LIST FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # # TIMING SFP J13 CONNECTIONS FOR: TX_FAULT, MOD_PRESENT, RX_LOSS NET 'SFP_TIME_TX_FAULT' R1605-2 # MODULE TX FAULT TO FPGA/CPU GPIO 3V3 INPUT NET 'SFP_TIME_MOD_ABS' R1602-2 # MODULE ABSENT TO FPGA/CPU GPIO 3V3 INPUT NET 'SFP_TIME_RX_LOS' R1601-2 # RX SIGNAL LOSS TO FPGA/CPU GPIO 3V3 INPUT NET 'BULK_3V3' R1601-1 R1602-1 R1605-1 # PULL-UP 3V3 SOURCE # ETHERNET SFP J14 CONNECTIONS FOR: TX_FAULT, MOD_PRESENT, RX_LOSS NET 'SFP_ENET_TX_FAULT' R1610-2 # MODULE TX FAULT TO FPGA/CPU GPIO 3V3 INPUT NET 'SFP_ENET_MOD_ABS' R1607-2 # MODULE ABSENT TO FPGA/CPU GPIO 3V3 INPUT NET 'SFP_ENET_RX_LOS' R1606-2 # RX SIGNAL LOSS TO FPGA/CPU GPIO 3V3 INPUT NET 'BULK_3V3' R1606-1 R1607-1 R1610-1 # PULL-UP 3V3 SOURCE # # SFP CONNECTOR PINS: TX_DISABLE, RATE_SELECT_0, RATE_SELECT_1 # ------------------------------------------------------------------------- # # THESE 3 PINS ARE INPUTS TO EACH SFP MODULE. # # FOR OUR USE ON THE DK BOARD THE TX_DISABLE NEEDS TO BE # CONTROLLED BY A GPIO OUTPUT SIGNAL FROM THE FPGA/CPU. # I WILL INCLUDE A SERIES TERMINATOR IN THIS LINE AS IT # MAY NEED TO BE BANGED ABOUT QUITE A BIT. # # NORMALLY THE TWO RATE_SELECT PINS ARE NOT USED - BUT # BECAUSE OF THE SPECIAL TYPES OF SFP MODULES THAT MAY BE # USED ON THE DK BOARD I WILL ALSO ROUTE THE TWO RATE_SELECT # PINS FROM THE SFP CONNECTORS TO GPIO PINS ON THE FPGA/CPU. # # THE TX_DISABLE AND THE RATE_SELECT CONNECTIONS TO THE # FPGA/CPU ARE TO FLOATING GPIO PIN ASSIGNMENTS. # # THE ACTUAL ASSIGNMENT OF THESE SIGNALS TO A PHYSICAL PINS # ON THE FPGA/CPU IS MADE IN THE NET LIST FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # # # THE TX_DISABLE HAS 2 JUMPER SELECTABLE OPTIONS: # # - INSTALL THE GROUND JUMPER (JMP1601 JMP1603) # AND THE TX LASER IS FORCED ON CONTINUOUSLY. # # - INSTALL THE FPGA/CPU CONTROL JUMPER (JMP1602 # JMP1604) TO REQUIRE BOTH THE DK_CPU_IS_SANE # SIGNAL AND THE SFP_X_TRANS_ENABLE SIGNAL FROM # THE FPGA/CPU TO BOTH BE HI IN ORDER FOR THE # SFP MODULE TX LASER TO COME ON. # NOTE: THE CONTROL SIGNAL FROM THE FPGA/CPU IS # AN "ENABLE" TYPE SIGNAL (NOT A DISABLE). # # # TX DISABLE FOR THE TIMING SFP: # --------------------------======------------------ # NET 'SFP_TIME_TRANS_ENABLE' R1615-2 # TIME SFP TX ENABLE FROM FPGA/CPU GPIO OUTPUT NET 'SFP_TIME_TX_ENB_TERM' R1615-1 U1602-2 # TIME SFP TX ENABLE TO NAND GATE NET 'SFP_TIME_TX_ENB_JMPR' U1602-3 JMP1602-1 # TIME SFP TX ENABLE TO JUMPER NET 'SFP_TIME_TX_DISABLE' JMP1601-1 JMP1602-2 # TIME SFP TX DISABLED PIN #3 NET 'GROUND' JMP1601-2 # GROUND JUMPER LASER FORCED ON # # TX DISABLE FOR THE ETHERNET SFP: # --------------------------========---------------- # NET 'SFP_ENET_TRANS_ENABLE' R1616-2 # ENET SFP TX ENABLE FROM FPGA/CPU GPIO OUTPUT NET 'SFP_ENET_TX_ENB_TERM' R1616-1 U1602-12 # ENET SFP TX ENABLE TO NAND GATE NET 'SFP_ENET_TX_ENB_JMPR' U1602-11 JMP1604-1 # ENET SFP TX ENABLE TO JUMPER NET 'SFP_ENET_TX_DISABLE' JMP1603-1 JMP1604-2 # ENET SFP TX DISABLED PIN #3 NET 'GROUND' JMP1603-2 # GROUND JUMPER LASER FORCED ON # # DK_CPU_IS_SANE DISTRIBUTION TO THE TX DISABLE CIRCUITS: # ------------------------------------------------------------------ # NET 'DK_CPU_IS_SANE' U1602-1 U1602-13 # CPU_SANE TO THE TX DISABLE GATES NET 'DK_CPU_IS_SANE' U1602-4 U1602-5 # CPU_SANE TO THE INVERTER GATE NET 'DK_CPU_IS_SANE' U1602-10 # CPU_SANE TO THE TOMCAT RESET GATE NET 'DK_CPU_IS_SANE_B' U1602-6 # CPU_SANE_B TO THE EMERGENCY RESCUE CIRCUITS # # TX DISABLE NAND GATE POWER AND GROUND: # -------------------------------------------------- # NET 'BULK_3V3' C1615-2 U1602-14 # BULK_3V3 BYPASS AND POWER NET 'GROUND' C1615-1 U1602-7 # GROUND THE BYPASS AND CHIP # # PULL-UP RESISTORS AND CONNECTION FOR THE: SFP <--> I2C FAN-OUT I2C LINKS # ------------------------------------------------------------------------------- # # TIMING SFP J13 CONNECTION FOR: I2C LINK TO THE I2C FAN-OUT CH #1 NET 'SFP_TIME_SCL' R1603-2 U1601-7 # TIME SFP I2C SCLK TO FAN-OUT CHANNEL 1 NET 'SFP_TIME_SDA' R1604-2 U1601-6 # TIME SFP I2C SDATA TO FAN-OUT CHANNEL 1 NET 'BULK_3V3' R1603-1 R1604-1 # PULL-UP 3V3 SOURCE # ETHERNET SFP J14 CONNECTION FOR: I2C LINK TO THE I2C FAN-OUT CH #2 NET 'SFP_ENET_SCL' R1608-2 U1601-10 # ENET SFP I2C SCLK TO FAN-OUT CHANNEL 2 NET 'SFP_ENET_SDA' R1609-2 U1601-9 # ENET SFP I2C SDATA TO FAN-OUT CHANNEL 2 NET 'BULK_3V3' R1608-1 R1609-1 # PULL-UP 3V3 SOURCE # # I2C FAN-OUT CHANNEL CH #0 CONNECTION TO THE TIMING GENERATOR U901 # --------------------------------------------------------------------------- # # THIS NET LIST FILE JUST DEFINES THE CHANNEL #0 PINS ON THE # I2C FAN-OUT CHIP THAT PROVIDE THE I2C BUS TO SETUP AND MONITOR # THE AD9546 TIMING GENERATOR. THE PULL-UP RESISTORS FOR THIS # I2C LINK AND THE CONNECTIONS TO THE TIMING GENERATOR ARE ALL # MADE IN THE NET LIST FILE: TIMING_GENERATOR_NETS.TXT NET 'TG_I2C_SCLK' U1601-5 # I2C FAN-OUT CH #0 SCLK TO THE TIMING GENERATOR NET 'TG_I2C_SDATA' U1601-4 # I2C FAN-OUT CH #0 SDATA TO THE TIMING GENERATOR # # PULL-UP RESISTORS FOR THE UN-USED I2C FAN-OUT CHANNEL CH #3 # --------------------------------------------------------------------------- # NET 'I2C_CTRL_0_FAN_CH_3_SCL' R1613-2 U1601-12 # UN-USED I2C_FAN-OUT CHANNEL 3 SCLK NET 'I2C_CTRL_0_FAN_CH_3_SDA' R1614-2 U1601-11 # UN-USED I2C_FAN-OUT CHANNEL 3 SDATA NET 'BULK_3V3' R1613-1 R1614-1 # PULL-UP 3V3 SOURCE # # PULL-UP RESISTORS AND CONNECTION FOR THE: FPGA/CPU <--> I2C FAN-OUT I2C LINK # ----------------------------------------------------------------------------------- # NET 'CPU_I2C_CTRL_0_SCL' R1611-2 U1601-14 # FPGA/CPU CONTROLLER 0 I2C SCLK TO FAN-OUT NET 'CPU_I2C_CTRL_0_SDA' R1612-2 U1601-15 # FPGA/CPU CONTROLLER 0 I2C SDATA TO FAN-OUT NET 'BULK_3V3' R1611-1 R1612-1 # PULL-UP 3V3 SOURCE # # I2C FAN-OUT ADDRESS PINS # --------------------------------------------------------------------------- # # THE 3 ADDRESS PINS ON THE PCA9546A I2C FAN-OUT CHIP ARE # ALL TIED TO GROUND. THESE CONNECTIONS ARE MADE ON THE PCB # WITH SUFFICIENTLY LONG RUNS SO THAT THEY MAY BE CHANGED IN # AN EMERGENCY. # # THIS GIVES THE I2C FAN-OUT CHIP ITSELF AN ADDRESS OF 0X70 # WHEN WRITTEN AS 3 MS BIT AND 4 LS BIT EXPRESSED IN HEX. # NET 'GROUND' U1601-1 U1601-2 U1601-13 # GROUND ALL 3 ADDRESS PINS # # I2C FAN-OUT RESET_B PIN # --------------------------------------------------------------------------- # # THE RESET_B PIN ON THE PCA9546A IS CONTROLLED BY THE SIGNAL # FROM A GPIO PIN ON THE FPGA/CPU. THIS CONNECTION IS TO A # FLOATING PIN ON THE FPGA/CPU NET 'CPU_I2C_CTRL_0_FAN_OUT_RESET_B' U1601-3 # I2C FANOUT RESET_B FROM FPGA/CPU GPIO # # POWER AND GROUND TO THE I2C FAN-OUT: # ------------------------------------------------------------------------- # NET 'BULK_3V3' C1614-2 C1613-2 U1601-16 # BULK_3V3 BYPASS AND POWER NET 'GROUND' C1614-1 C1613-1 U1601-8 # GROUND THE BYPASS AND CHIP # # TIMING SFP J13 CONNECTOR PINS # --------------------------------- # NET 'GROUND' J13-1 # MODULE TRANSMITTER GROUND NET 'SFP_TIME_TX_FAULT' J13-2 # MODULE TRANSMITTER FAULT NET 'SFP_TIME_TX_DISABLE' J13-3 # TRANSMITTER DISABLED NET 'SFP_TIME_SDA' J13-4 # 2-WIRE SERIAL DATA NET 'SFP_TIME_SCL' J13-5 # 2-WIRE SERIAL CLOCK NET 'SFP_TIME_MOD_ABS' J13-6 # MODULE ABSENT NET 'SFP_TIME_RS_0' J13-7 # RATE SELECT 0 NET 'SFP_TIME_RX_LOS' J13-8 # RECEIVER LOSS OF SIGNAL INDICATION NET 'SFP_TIME_RS_1' J13-9 # RATE SELECT 1 NET 'GROUND' J13-10 # MODULE RECEIVER GROUND NET 'GROUND' J13-11 # MODULE RECEIVER GROUND NET 'SFP_TIME_RD_CMP' J13-12 # RECEIVER INVERTED DATA OUTPUT NET 'SFP_TIME_RD_DIR' J13-13 # RECEIVER NONINVERTED DATA OUTPUT NET 'GROUND' J13-14 # MODULE RECEIVER GROUND NET 'SFP_TIME_VCCR' J13-15 # MODULE RECEIVER 3.3 V SUPPLY NET 'SFP_TIME_VCCT' J13-16 # MODULE TRANSMITTER 3.3 V SUPPLY NET 'GROUND' J13-17 # MODULE TRANSMITTER GROUND NET 'SFP_TIME_TD_DIR' J13-18 # TRANSMITTER NONINVERTED DATA INPUT NET 'SFP_TIME_TD_CMP' J13-19 # TRANSMITTER INVERTED DATA INPUT NET 'GROUND' J13-20 # MODULE TRANSMITTER GROUND # # ETHERNET SFP J14 CONNECTOR PINS # ----------------------------------- # NET 'GROUND' J14-1 # MODULE TRANSMITTER GROUND NET 'SFP_ENET_TX_FAULT' J14-2 # MODULE TRANSMITTER FAULT NET 'SFP_ENET_TX_DISABLE' J14-3 # TRANSMITTER DISABLED NET 'SFP_ENET_SDA' J14-4 # 2-WIRE SERIAL DATA NET 'SFP_ENET_SCL' J14-5 # 2-WIRE SERIAL CLOCK NET 'SFP_ENET_MOD_ABS' J14-6 # MODULE ABSENT NET 'SFP_ENET_RS_0' J14-7 # RATE SELECT 0 NET 'SFP_ENET_RX_LOS' J14-8 # RECEIVER LOSS OF SIGNAL INDICATION NET 'SFP_ENET_RS_1' J14-9 # RATE SELECT 1 NET 'GROUND' J14-10 # MODULE RECEIVER GROUND NET 'GROUND' J14-11 # MODULE RECEIVER GROUND NET 'SFP_ENET_RD_CMP' J14-12 # RECEIVER INVERTED DATA OUTPUT NET 'SFP_ENET_RD_DIR' J14-13 # RECEIVER NONINVERTED DATA OUTPUT NET 'GROUND' J14-14 # MODULE RECEIVER GROUND NET 'SFP_ENET_VCCR' J14-15 # MODULE RECEIVER 3.3 V SUPPLY NET 'SFP_ENET_VCCT' J14-16 # MODULE TRANSMITTER 3.3 V SUPPLY NET 'GROUND' J14-17 # MODULE TRANSMITTER GROUND NET 'SFP_ENET_TD_DIR' J14-18 # TRANSMITTER NONINVERTED DATA INPUT NET 'SFP_ENET_TD_CMP' J14-19 # TRANSMITTER INVERTED DATA INPUT NET 'GROUND' J14-20 # MODULE TRANSMITTER GROUND # # POWER FEEDS TO THE SFP CONNECTORS # ------------------------------------- # # TIMING SFP J13 RECEIVER NET 'BULK_3V3' L1601-1 C1601-1 # POWER FEED TO RX FILTER NET 'GROUND' C1601-2 # GROUND THIS BYPASS CAP NET 'SFP_TIME_VCCR' L1601-2 # POWER FEED TO J13 RX NET 'SFP_TIME_VCCR' C1605-2 C1606-2 # BYPASS ON J13 RX NET 'GROUND' C1605-1 C1606-1 # GROUND THESE BYPASS CAPS # TIMING SFP J13 TRANSMITTER NET 'BULK_3V3' L1602-1 C1602-1 # POWER FEED TO TX FILTER NET 'GROUND' C1602-2 # GROUND THIS BYPASS CAP NET 'SFP_TIME_VCCT' L1602-2 # POWER FEED TO J13 TX NET 'SFP_TIME_VCCT' C1607-2 C1608-2 # BYPASS ON J13 TX NET 'GROUND' C1607-1 C1608-1 # GROUND THESE BYPASS CAPS # ETHERNET SFP J14 RECEIVER NET 'BULK_3V3' L1603-1 C1603-1 # POWER FEED TO RX FILTER NET 'GROUND' C1603-2 # GROUND THIS BYPASS CAP NET 'SFP_ENET_VCCR' L1603-2 # POWER FEED TO J14 RX NET 'SFP_ENET_VCCR' C1609-2 C1610-2 # BYPASS ON J14 RX NET 'GROUND' C1609-1 C1610-1 # GROUND THESE BYPASS CAPS # ETHERNET SFP J14 TRANSMITTER NET 'BULK_3V3' L1604-1 C1604-1 # POWER FEED TO TX FILTER NET 'GROUND' C1604-2 # GROUND THIS BYPASS CAP NET 'SFP_ENET_VCCT' L1604-2 # POWER FEED TO J14 TX NET 'SFP_ENET_VCCT' C1611-2 C1612-2 # BYPASS ON J14 TX NET 'GROUND' C1611-1 C1612-1 # GROUND THESE BYPASS CAPS # # SFP TWIN CAGE GROUND PINS # ----------------------------- # NET 'GROUND' CAGE_1-1 CAGE_1-2 CAGE_1-3 CAGE_1-4 CAGE_1-5 NET 'GROUND' CAGE_1-6 CAGE_1-7 CAGE_1-8 CAGE_1-9 CAGE_1-10 NET 'GROUND' CAGE_1-11 CAGE_1-12 CAGE_1-13 CAGE_1-14 CAGE_1-15 NET 'GROUND' CAGE_1-16 CAGE_1-17 CAGE_1-18 CAGE_1-19 CAGE_1-20 NET 'GROUND' CAGE_1-21 CAGE_1-22 CAGE_1-23 CAGE_1-24 CAGE_1-25 # # LIST THE NETNAMES OF THE SIGNALS THAT MUST BE # CONNECTED TO FPGA FLOATING PINS. HERE JUST LIST # THE NETNAMES - THE ACTUAL CONNECTIONS TO THESE # FPGA FLOATING PINS ARE MADE IN THE NETS FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # ---------------------------------------------------- # # # ALL OF THESE ARE 3V3 SIGNALS: SFP CONTROL AND MONITOR AND # FPGA/CPU I2C CONTROLLER #0 # --------------------------------------------------------------------------- # # # NET 'SFP_TIME_TX_FAULT' # TIME SFP TX FAULT TO FPGA/CPU GPIO INPUT # NET 'SFP_TIME_MOD_ABS' # TIME SFP MODULE ABSENT TO FPGA/CPU GPIO INPUT # NET 'SFP_TIME_RX_LOS' # TIME SFP RX SIGNAL LOSS TO FPGA/CPU GPIO INPUT # # NET 'SFP_TIME_TRANS_ENABLE' # TIME SFP TX ENABLE FROM FPGA/CPU GPIO OUTPUT # # NET 'SFP_TIME_RS_0' # TIME SFP RATE SELECT 0 <--> FPGA/CPU GPIO I/O # NET 'SFP_TIME_RS_1' # TIME SFP RATE SELECT 1 <--> FPGA/CPU GPIO I/O # # # NET 'SFP_ENET_TX_FAULT' # ENET SFP TX FAULT TO FPGA/CPU GPIO INPUT # NET 'SFP_ENET_MOD_ABS' # ENET SFP MODULE ABSENT TO FPGA/CPU GPIO INPUT # NET 'SFP_ENET_RX_LOS' # ENET SFP RX SIGNAL LOSS TO FPGA/CPU GPIO INPUT # # NET 'SFP_ENET_TRANS_ENABLE' # ENET SFP TX ENABLE FROM FPGA/CPU GPIO OUTPUT # # NET 'SFP_ENET_RS_0' # TIME SFP RATE SELECT 0 <--> FPGA/CPU GPIO I/O # NET 'SFP_ENET_RS_1' # TIME SFP RATE SELECT 1 <--> FPGA/CPU GPIO I/O # # # NET 'CPU_I2C_CTRL_0_SCL' # FPGA/CPU CONTROLLER 0 I2C SCLK TO FAN-OUT # NET 'CPU_I2C_CTRL_0_SDA' # FPGA/CPU CONTROLLER 0 I2C SDATA TO FAN-OUT # # NET 'CPU_I2C_CTRL_0_FAN_OUT_RESET_B' # I2C FANOUT RESET_B FROM FPGA/CPU GPIO # # # BELOW HERE IS SOME SFP REFERENCE INFORMATION # ---------------------------------------------- # # # NOTE THAT PIN #9 HAS A DIFFERENT FUNCTION # IN THE SFP VS SFP+ PINOUTS # # # SFP NETWORK PORT CONNECTOR PINOUT # --------------------------------- # # 1 VEET MODULE TRANSMITTER GROUND # 2 TX_FAULT MODULE TRANSMITTER FAULT # 3 TX_DISABLE TRANSMITTER DISABLED # 4 SDA 2-WIRE SERIAL INTERFACE DATA LINE # 5 SCL 2-WIRE SERIAL INTERFACE CLOCK # # 6 MOD_ABS MODULE ABSENT # 7 RS RATE SELECT # 8 RX_LOS RECEIVER LOSS OF SIGNAL INDICATION # 9 VEER MODULE RECEIVER GROUND # 10 VEER MODULE RECEIVER GROUND # # 11 VEER MODULE RECEIVER GROUND # 12 RD- RECEIVER INVERTED DATA OUTPUT # 13 RD+ RECEIVER NONINVERTED DATA OUTPUT # 14 VEER MODULE RECEIVER GROUND # 15 VCCR MODULE RECEIVER 3.3 V SUPPLY # # 16 VCCT MODULE TRANSMITTER 3.3 V SUPPLY # 17 VEET MODULE TRANSMITTER GROUND # 18 TD+ TRANSMITTER NONINVERTED DATA INPUT # 19 TD- TRANSMITTER INVERTED DATA INPUT # 20 VEET MODULE TRANSMITTER GROUND # # # # SFP+ NETWORK PORT CONNECTOR PINOUT # ---------------------------------- # # 1 VEET MODULE TRANSMITTER GROUND # 2 TX_FAULT MODULE TRANSMITTER FAULT # 3 TX_DISABLE TRANSMITTER DISABLED # 4 SDA 2-WIRE SERIAL INTERFACE DATA LINE # 5 SCL 2-WIRE SERIAL INTERFACE CLOCK # # 6 MOD_ABS MODULE ABSENT # 7 RS0 RATE SELECT 0, OPTIONALLY CONTROLS SFP+ MODULE RECEIVER # 8 RX_LOS RECEIVER LOSS OF SIGNAL INDICATION # 9 RS1 RATE SELECT 1, OPTIONALLY CONTROLS SFP+ TRANSMITTER # 10 VEER MODULE RECEIVER GROUND # # 11 VEER MODULE RECEIVER GROUND # 12 RD- RECEIVER INVERTED DATA OUTPUT # 13 RD+ RECEIVER NONINVERTED DATA OUTPUT # 14 VEER MODULE RECEIVER GROUND # 15 VCCR MODULE RECEIVER 3.3-V SUPPLY # # 16 VCCT MODULE TRANSMITTER 3.3-V SUPPLY # 17 VEET MODULE TRANSMITTER GROUND # 18 TD+ TRANSMITTER NONINVERTED DATA INPUT # 19 TD- TRANSMITTER INVERTED DATA INPUT # 20 VEET MODULE TRANSMITTER GROUND # # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #1/6 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # DCDC CONVERTER NET LIST TEMPLATE FILE # ----------------========--========------- # # # ORIGINAL REV. 5-FEB-2023 # MOST RECENT REV. 17-NOV-2023 # # # # THIS TEMPLATE FILE HOLDS THE NETS FOR THE DK # DC/DC POWER CONVERTERS. THESE CONVERTERS RUN # FROM THE BULK_5V0 BUS AND IT MAKE THE 6 BULK # POWER RAILS THAT ARE USED BY THE DK BOARD ITSELF. # # # FOR REFERENCE RECALL THE 6 DCDC CONVERTERS ON DK: # # OUTPUT # CONVERTER REF. POWER OUTPUT EXPECTED OUTPUT POWER TRENDS # NAME DESIG BUS VOLTAGE LOAD CAPACITY MODEL NUMBER # --------- ----- --------- ------- ----------- -------- ------------ # # DCDC1 1701 BULK_1V00 1.00 V ABOUT 1.4 A 3 A PTH04T260WAD # DCDC2 1731 BULK_1V05 1.05 V UNDER 3.0 A 6 A PTH04T230WAD # DCDC3 1761 BULK_1V2 1.20 V ABOUT 4.0 A 6 A PTH04T230WAD # DCDC4 1791 BULK_1V8 1.80 V UNDER 1.5 A 3 A PTH04T260WAD # DCDC5 1821 BULK_2V5 2.50 V ABOUT 1.4 A 3 A PTH04T260WAD # DCDC6 1851 BULK_3V3 3.30 V UNDER 1.5 A 3 A PTH04T260WAD # # # # DEFINE THE CONNECTIONS WITHIN THE DCDC POWER CONVERTER # --------------------------------------------------------- # # # INPUT POWER TO THE CONVERTER: NET 'BULK_5V0' R1701-2 # POWER TO THE CURRENT SENSE RESISTOR NET 'DCDC1_CSR_TO_L' R1701-3 # POWER FROM THE CURRENT SENSE NET 'DCDC1_CSR_TO_L' L1701-1 # RESISTOR TO THE FILTER INDUCTOR NET 'DCDC1_INPUT' L1701-2 # POWER FEED TO THE CONVERTER NET 'DCDC1_INPUT' C1701-1 C1702-1 # TANTALUM INPUT CAPS NET 'DCDC1_INPUT' C1703-1 C1704-1 # TANTALUM INPUT CAPS NET 'DCDC1_INPUT' C1705-2 C1706-1 # CERAMIC INPUT CAPS NET 'DCDC1_INPUT' C1707-2 C1708-2 # CERAMIC INPUT CAPS NET 'DCDC1_INPUT' DCDC1-2 # POWER INPUT TO THE CONVERTER - PIN #2 NET 'GROUND' C1701-2 C1702-2 # TANTALUM CAP GROUNDS NET 'GROUND' C1703-2 C1704-2 # TALTALUM CAP GROUNDS NET 'GROUND' C1705-1 C1706-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1707-1 C1708-1 # CERAMIC CAP GROUNDS # # POWER OUTPUT FROM THE CONVERTER: NET 'BULK_1V00' DCDC1-4 # OUTPUT POWER FROM THE CONVERTER - PIN #4 NET 'BULK_1V00' C1709-1 C1710-1 # CERAMIC OUTPUT CAPS NET 'BULK_1V00' C1711-2 C1712-1 # CERAMIC OUTPUT CAPS NET 'BULK_1V00' C1713-1 C1714-1 # TANTALUM OUTPUT CAPS NET 'BULK_1V00' C1715-1 C1716-1 # TANTALUM OUTPUT CAPS NET 'BULK_1V00' DZ1701-1 # OUTPUT ZENER CLAMP NET 'GROUND' C1709-2 C1710-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1711-1 C1712-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1713-2 C1714-2 # TANTALUM CAP GROUNDS NET 'GROUND' C1715-2 C1716-2 # TANTALUM CAP GROUNDS NET 'GROUND' DZ1701-2 # ZENER CLAMP GROUND # # DC/DC CONVERTER GROUND PINS NET 'GROUND' DCDC1-3 # CONVERTER GROUND PIN - PIN #3 NET 'GROUND' DCDC1-31 DCDC1-32 # CONVERTER AUXILIARY GROUND PINS # # DC/DC CONVERTER TRACKING PIN NET 'DCDC_CONV_TRACK' DCDC1-9 # TRACK PIN OF THIS DCDC CONVERTER - PIN #9 # # DC/DC CONVERTER FEEDBACK REMOTE SENSE PINS NET 'BULK_1V00' AKA1701-2 # POSITIVE SENSE REMOTE CONNECTION NET 'DCDC1_SEN_POS' AKA1701-1 DCDC1-5 # POSITIVE SENSE INPUT PIN - PIN #5 NET 'GROUND' AKA1702-2 # NEGATIVE SENSE REMOTE CONNECTION NET 'DCDC1_SEN_NEG' AKA1702-1 DCDC1-6 # NEGATIVE SENSE INPUT PIN - PIN #6 # # DC/DC CONVERTER OUTPUT VOLTAGE RSET RESISTOR # WITH CAPACITOR ACROSS THE VARIABLE PART OF THE VOUT RSET RESISTOR # # NOTE: GROUND REFERENCE NOT NEGATIVE SENSE REFERENCE NET 'GROUND' R1703-1 R1703-2 # WANT TRIM POT CW TRUNING TO: NET 'DCDC1_VAR_FIX' R1703-3 # REDUCE THE RESISTANCE AND NET 'DCDC1_VAR_FIX' R1702-2 # INCREASE THE OUTPUT VOLTAGE NET 'DCDC1_VO_ADJ' R1702-1 DCDC1-7 # CONVERTER RSET VOUT ADJ PIN - PIN #7 NET 'DCDC1_VAR_FIX' C1717-1 # CAPACITOR ACROSS THE NET 'GROUND' C1717-2 # VOUT TRIM POT RESISTOR # # DC/DC CONVERTER TRANSIENT RESPONSE CONTROL PIN NET 'DCDC1_TRC_PIN' R1704-2 DCDC1-8 # TRANSIENT RESPONSE CONTROL PIN - PIN #8 NET 'DCDC1_SEN_POS' R1704-1 # TRANSIENT RESPONSE RESISTOR # # DC/DC CONVERTER INH-UVLO PIN AND RESISTOR NET 'DCDC1_INH_UVLO' R1705-1 DCDC1-10 # INH-UVLO PIN #10 NET 'GROUND' R1705-2 # GROUND END OF UVLO RESISTOR # # DC/DC CONVERTER SYNC PIN TIED TO GROUND VIA TRACE NET 'DCDC1_SYNC' AKA1703-1 DCDC1-1 # CONVERTER'S SYNC PIN - PIN #1 NET 'GROUND' AKA1703-2 # TIE SYNC PIN TO GROUND # # CURRENT SENSE RESISTOR TO FILTER AND TO CURRENT MONITOR CONNECTOR PINS NET 'DCDC1_CS_POS' R1701-4 R1706-1 # CURRENT SENSE RES. TO FILTER RES. NET 'DCDC1_CS_NEG' R1701-1 R1707-1 # CURRENT SENSE RES. TO FILTER RES. NET 'IMON_POS_BULK_1V00' R1706-2 C1718-1 # CURRENT MONITOR FILTER RES CAP PIN NET 'IMON_NEG_BULK_1V00' R1707-2 C1720-2 # CURRENT MONITOR FILTER RES CAP PIN NET 'IMON_POS_BULK_1V00' C1719-1 # CURRENT MONITOR SHUNT CAP NET 'IMON_NEG_BULK_1V00' C1719-2 # CURRENT MONITOR SHUNT CAP NET 'GROUND' C1718-2 C1720-1 # CURRENT MONITOR FILTER CAP GROUNDS # # VOLTAGE MONITOR FILTER AND TO VOLTAGE MONITOR CONNECTOR PIN NET 'BULK_1V00' R1708-1 # VOLTAGE MONITOR FILTER RESISTOR NET 'VMON_BULK_1V00' R1708-2 C1721-1 # VOLTAGE MONITOR FILTER RES CAP PIN NET 'GROUND' C1721-2 # VOLTAGE MONITOR FILTER CAP GROUND # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #2/6 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # DCDC CONVERTER NET LIST TEMPLATE FILE # ----------------========--========------- # # # ORIGINAL REV. 5-FEB-2023 # MOST RECENT REV. 17-NOV-2023 # # # # THIS TEMPLATE FILE HOLDS THE NETS FOR THE DK # DC/DC POWER CONVERTERS. THESE CONVERTERS RUN # FROM THE BULK_5V0 BUS AND IT MAKE THE 6 BULK # POWER RAILS THAT ARE USED BY THE DK BOARD ITSELF. # # # FOR REFERENCE RECALL THE 6 DCDC CONVERTERS ON DK: # # OUTPUT # CONVERTER REF. POWER OUTPUT EXPECTED OUTPUT POWER TRENDS # NAME DESIG BUS VOLTAGE LOAD CAPACITY MODEL NUMBER # --------- ----- --------- ------- ----------- -------- ------------ # # DCDC1 1701 BULK_1V00 1.00 V ABOUT 1.4 A 3 A PTH04T260WAD # DCDC2 1731 BULK_1V05 1.05 V UNDER 3.0 A 6 A PTH04T230WAD # DCDC3 1761 BULK_1V2 1.20 V ABOUT 4.0 A 6 A PTH04T230WAD # DCDC4 1791 BULK_1V8 1.80 V UNDER 1.5 A 3 A PTH04T260WAD # DCDC5 1821 BULK_2V5 2.50 V ABOUT 1.4 A 3 A PTH04T260WAD # DCDC6 1851 BULK_3V3 3.30 V UNDER 1.5 A 3 A PTH04T260WAD # # # # DEFINE THE CONNECTIONS WITHIN THE DCDC POWER CONVERTER # --------------------------------------------------------- # # # INPUT POWER TO THE CONVERTER: NET 'BULK_5V0' R1731-2 # POWER TO THE CURRENT SENSE RESISTOR NET 'DCDC2_CSR_TO_L' R1731-3 # POWER FROM THE CURRENT SENSE NET 'DCDC2_CSR_TO_L' L1731-1 # RESISTOR TO THE FILTER INDUCTOR NET 'DCDC2_INPUT' L1731-2 # POWER FEED TO THE CONVERTER NET 'DCDC2_INPUT' C1731-1 C1732-1 # TANTALUM INPUT CAPS NET 'DCDC2_INPUT' C1733-1 C1734-1 # TANTALUM INPUT CAPS NET 'DCDC2_INPUT' C1735-2 C1736-1 # CERAMIC INPUT CAPS NET 'DCDC2_INPUT' C1737-2 C1738-2 # CERAMIC INPUT CAPS NET 'DCDC2_INPUT' DCDC2-2 # POWER INPUT TO THE CONVERTER - PIN #2 NET 'GROUND' C1731-2 C1732-2 # TANTALUM CAP GROUNDS NET 'GROUND' C1733-2 C1734-2 # TALTALUM CAP GROUNDS NET 'GROUND' C1735-1 C1736-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1737-1 C1738-1 # CERAMIC CAP GROUNDS # # POWER OUTPUT FROM THE CONVERTER: NET 'BULK_1V05' DCDC2-4 # OUTPUT POWER FROM THE CONVERTER - PIN #4 NET 'BULK_1V05' C1739-1 C1740-1 # CERAMIC OUTPUT CAPS NET 'BULK_1V05' C1741-2 C1742-1 # CERAMIC OUTPUT CAPS NET 'BULK_1V05' C1743-1 C1744-1 # TANTALUM OUTPUT CAPS NET 'BULK_1V05' C1745-1 C1746-1 # TANTALUM OUTPUT CAPS NET 'BULK_1V05' DZ1731-1 # OUTPUT ZENER CLAMP NET 'GROUND' C1739-2 C1740-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1741-1 C1742-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1743-2 C1744-2 # TANTALUM CAP GROUNDS NET 'GROUND' C1745-2 C1746-2 # TANTALUM CAP GROUNDS NET 'GROUND' DZ1731-2 # ZENER CLAMP GROUND # # DC/DC CONVERTER GROUND PINS NET 'GROUND' DCDC2-3 # CONVERTER GROUND PIN - PIN #3 NET 'GROUND' DCDC2-31 DCDC2-32 # CONVERTER AUXILIARY GROUND PINS # # DC/DC CONVERTER TRACKING PIN NET 'DCDC_CONV_TRACK' DCDC2-9 # TRACK PIN OF THIS DCDC CONVERTER - PIN #9 # # DC/DC CONVERTER FEEDBACK REMOTE SENSE PINS NET 'BULK_1V05' AKA1731-2 # POSITIVE SENSE REMOTE CONNECTION NET 'DCDC2_SEN_POS' AKA1731-1 DCDC2-5 # POSITIVE SENSE INPUT PIN - PIN #5 NET 'GROUND' AKA1732-2 # NEGATIVE SENSE REMOTE CONNECTION NET 'DCDC2_SEN_NEG' AKA1732-1 DCDC2-6 # NEGATIVE SENSE INPUT PIN - PIN #6 # # DC/DC CONVERTER OUTPUT VOLTAGE RSET RESISTOR # WITH CAPACITOR ACROSS THE VARIABLE PART OF THE VOUT RSET RESISTOR # # NOTE: GROUND REFERENCE NOT NEGATIVE SENSE REFERENCE NET 'GROUND' R1733-1 R1733-2 # WANT TRIM POT CW TRUNING TO: NET 'DCDC2_VAR_FIX' R1733-3 # REDUCE THE RESISTANCE AND NET 'DCDC2_VAR_FIX' R1732-2 # INCREASE THE OUTPUT VOLTAGE NET 'DCDC2_VO_ADJ' R1732-1 DCDC2-7 # CONVERTER RSET VOUT ADJ PIN - PIN #7 NET 'DCDC2_VAR_FIX' C1747-1 # CAPACITOR ACROSS THE NET 'GROUND' C1747-2 # VOUT TRIM POT RESISTOR # # DC/DC CONVERTER TRANSIENT RESPONSE CONTROL PIN NET 'DCDC2_TRC_PIN' R1734-2 DCDC2-8 # TRANSIENT RESPONSE CONTROL PIN - PIN #8 NET 'DCDC2_SEN_POS' R1734-1 # TRANSIENT RESPONSE RESISTOR # # DC/DC CONVERTER INH-UVLO PIN AND RESISTOR NET 'DCDC2_INH_UVLO' R1735-1 DCDC2-10 # INH-UVLO PIN #10 NET 'GROUND' R1735-2 # GROUND END OF UVLO RESISTOR # # DC/DC CONVERTER SYNC PIN TIED TO GROUND VIA TRACE NET 'DCDC2_SYNC' AKA1733-1 DCDC2-1 # CONVERTER'S SYNC PIN - PIN #1 NET 'GROUND' AKA1733-2 # TIE SYNC PIN TO GROUND # # CURRENT SENSE RESISTOR TO FILTER AND TO CURRENT MONITOR CONNECTOR PINS NET 'DCDC2_CS_POS' R1731-4 R1736-1 # CURRENT SENSE RES. TO FILTER RES. NET 'DCDC2_CS_NEG' R1731-1 R1737-1 # CURRENT SENSE RES. TO FILTER RES. NET 'IMON_POS_BULK_1V05' R1736-2 C1748-1 # CURRENT MONITOR FILTER RES CAP PIN NET 'IMON_NEG_BULK_1V05' R1737-2 C1750-2 # CURRENT MONITOR FILTER RES CAP PIN NET 'IMON_POS_BULK_1V05' C1749-1 # CURRENT MONITOR SHUNT CAP NET 'IMON_NEG_BULK_1V05' C1749-2 # CURRENT MONITOR SHUNT CAP NET 'GROUND' C1748-2 C1750-1 # CURRENT MONITOR FILTER CAP GROUNDS # # VOLTAGE MONITOR FILTER AND TO VOLTAGE MONITOR CONNECTOR PIN NET 'BULK_1V05' R1738-1 # VOLTAGE MONITOR FILTER RESISTOR NET 'VMON_BULK_1V05' R1738-2 C1751-1 # VOLTAGE MONITOR FILTER RES CAP PIN NET 'GROUND' C1751-2 # VOLTAGE MONITOR FILTER CAP GROUND # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:40 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #3/6 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # DCDC CONVERTER NET LIST TEMPLATE FILE # ----------------========--========------- # # # ORIGINAL REV. 5-FEB-2023 # MOST RECENT REV. 17-NOV-2023 # # # # THIS TEMPLATE FILE HOLDS THE NETS FOR THE DK # DC/DC POWER CONVERTERS. THESE CONVERTERS RUN # FROM THE BULK_5V0 BUS AND IT MAKE THE 6 BULK # POWER RAILS THAT ARE USED BY THE DK BOARD ITSELF. # # # FOR REFERENCE RECALL THE 6 DCDC CONVERTERS ON DK: # # OUTPUT # CONVERTER REF. POWER OUTPUT EXPECTED OUTPUT POWER TRENDS # NAME DESIG BUS VOLTAGE LOAD CAPACITY MODEL NUMBER # --------- ----- --------- ------- ----------- -------- ------------ # # DCDC1 1701 BULK_1V00 1.00 V ABOUT 1.4 A 3 A PTH04T260WAD # DCDC2 1731 BULK_1V05 1.05 V UNDER 3.0 A 6 A PTH04T230WAD # DCDC3 1761 BULK_1V2 1.20 V ABOUT 4.0 A 6 A PTH04T230WAD # DCDC4 1791 BULK_1V8 1.80 V UNDER 1.5 A 3 A PTH04T260WAD # DCDC5 1821 BULK_2V5 2.50 V ABOUT 1.4 A 3 A PTH04T260WAD # DCDC6 1851 BULK_3V3 3.30 V UNDER 1.5 A 3 A PTH04T260WAD # # # # DEFINE THE CONNECTIONS WITHIN THE DCDC POWER CONVERTER # --------------------------------------------------------- # # # INPUT POWER TO THE CONVERTER: NET 'BULK_5V0' R1761-2 # POWER TO THE CURRENT SENSE RESISTOR NET 'DCDC3_CSR_TO_L' R1761-3 # POWER FROM THE CURRENT SENSE NET 'DCDC3_CSR_TO_L' L1761-1 # RESISTOR TO THE FILTER INDUCTOR NET 'DCDC3_INPUT' L1761-2 # POWER FEED TO THE CONVERTER NET 'DCDC3_INPUT' C1761-1 C1762-1 # TANTALUM INPUT CAPS NET 'DCDC3_INPUT' C1763-1 C1764-1 # TANTALUM INPUT CAPS NET 'DCDC3_INPUT' C1765-2 C1766-1 # CERAMIC INPUT CAPS NET 'DCDC3_INPUT' C1767-2 C1768-2 # CERAMIC INPUT CAPS NET 'DCDC3_INPUT' DCDC3-2 # POWER INPUT TO THE CONVERTER - PIN #2 NET 'GROUND' C1761-2 C1762-2 # TANTALUM CAP GROUNDS NET 'GROUND' C1763-2 C1764-2 # TALTALUM CAP GROUNDS NET 'GROUND' C1765-1 C1766-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1767-1 C1768-1 # CERAMIC CAP GROUNDS # # POWER OUTPUT FROM THE CONVERTER: NET 'BULK_1V2' DCDC3-4 # OUTPUT POWER FROM THE CONVERTER - PIN #4 NET 'BULK_1V2' C1769-1 C1770-1 # CERAMIC OUTPUT CAPS NET 'BULK_1V2' C1771-2 C1772-1 # CERAMIC OUTPUT CAPS NET 'BULK_1V2' C1773-1 C1774-1 # TANTALUM OUTPUT CAPS NET 'BULK_1V2' C1775-1 C1776-1 # TANTALUM OUTPUT CAPS NET 'BULK_1V2' DZ1761-1 # OUTPUT ZENER CLAMP NET 'GROUND' C1769-2 C1770-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1771-1 C1772-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1773-2 C1774-2 # TANTALUM CAP GROUNDS NET 'GROUND' C1775-2 C1776-2 # TANTALUM CAP GROUNDS NET 'GROUND' DZ1761-2 # ZENER CLAMP GROUND # # DC/DC CONVERTER GROUND PINS NET 'GROUND' DCDC3-3 # CONVERTER GROUND PIN - PIN #3 NET 'GROUND' DCDC3-31 DCDC3-32 # CONVERTER AUXILIARY GROUND PINS # # DC/DC CONVERTER TRACKING PIN NET 'DCDC_CONV_TRACK' DCDC3-9 # TRACK PIN OF THIS DCDC CONVERTER - PIN #9 # # DC/DC CONVERTER FEEDBACK REMOTE SENSE PINS NET 'BULK_1V2' AKA1761-2 # POSITIVE SENSE REMOTE CONNECTION NET 'DCDC3_SEN_POS' AKA1761-1 DCDC3-5 # POSITIVE SENSE INPUT PIN - PIN #5 NET 'GROUND' AKA1762-2 # NEGATIVE SENSE REMOTE CONNECTION NET 'DCDC3_SEN_NEG' AKA1762-1 DCDC3-6 # NEGATIVE SENSE INPUT PIN - PIN #6 # # DC/DC CONVERTER OUTPUT VOLTAGE RSET RESISTOR # WITH CAPACITOR ACROSS THE VARIABLE PART OF THE VOUT RSET RESISTOR # # NOTE: GROUND REFERENCE NOT NEGATIVE SENSE REFERENCE NET 'GROUND' R1763-1 R1763-2 # WANT TRIM POT CW TRUNING TO: NET 'DCDC3_VAR_FIX' R1763-3 # REDUCE THE RESISTANCE AND NET 'DCDC3_VAR_FIX' R1762-2 # INCREASE THE OUTPUT VOLTAGE NET 'DCDC3_VO_ADJ' R1762-1 DCDC3-7 # CONVERTER RSET VOUT ADJ PIN - PIN #7 NET 'DCDC3_VAR_FIX' C1777-1 # CAPACITOR ACROSS THE NET 'GROUND' C1777-2 # VOUT TRIM POT RESISTOR # # DC/DC CONVERTER TRANSIENT RESPONSE CONTROL PIN NET 'DCDC3_TRC_PIN' R1764-2 DCDC3-8 # TRANSIENT RESPONSE CONTROL PIN - PIN #8 NET 'DCDC3_SEN_POS' R1764-1 # TRANSIENT RESPONSE RESISTOR # # DC/DC CONVERTER INH-UVLO PIN AND RESISTOR NET 'DCDC3_INH_UVLO' R1765-1 DCDC3-10 # INH-UVLO PIN #10 NET 'GROUND' R1765-2 # GROUND END OF UVLO RESISTOR # # DC/DC CONVERTER SYNC PIN TIED TO GROUND VIA TRACE NET 'DCDC3_SYNC' AKA1763-1 DCDC3-1 # CONVERTER'S SYNC PIN - PIN #1 NET 'GROUND' AKA1763-2 # TIE SYNC PIN TO GROUND # # CURRENT SENSE RESISTOR TO FILTER AND TO CURRENT MONITOR CONNECTOR PINS NET 'DCDC3_CS_POS' R1761-4 R1766-1 # CURRENT SENSE RES. TO FILTER RES. NET 'DCDC3_CS_NEG' R1761-1 R1767-1 # CURRENT SENSE RES. TO FILTER RES. NET 'IMON_POS_BULK_1V2' R1766-2 C1778-1 # CURRENT MONITOR FILTER RES CAP PIN NET 'IMON_NEG_BULK_1V2' R1767-2 C1780-2 # CURRENT MONITOR FILTER RES CAP PIN NET 'IMON_POS_BULK_1V2' C1779-1 # CURRENT MONITOR SHUNT CAP NET 'IMON_NEG_BULK_1V2' C1779-2 # CURRENT MONITOR SHUNT CAP NET 'GROUND' C1778-2 C1780-1 # CURRENT MONITOR FILTER CAP GROUNDS # # VOLTAGE MONITOR FILTER AND TO VOLTAGE MONITOR CONNECTOR PIN NET 'BULK_1V2' R1768-1 # VOLTAGE MONITOR FILTER RESISTOR NET 'VMON_BULK_1V2' R1768-2 C1781-1 # VOLTAGE MONITOR FILTER RES CAP PIN NET 'GROUND' C1781-2 # VOLTAGE MONITOR FILTER CAP GROUND # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:40 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #4/6 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # DCDC CONVERTER NET LIST TEMPLATE FILE # ----------------========--========------- # # # ORIGINAL REV. 5-FEB-2023 # MOST RECENT REV. 17-NOV-2023 # # # # THIS TEMPLATE FILE HOLDS THE NETS FOR THE DK # DC/DC POWER CONVERTERS. THESE CONVERTERS RUN # FROM THE BULK_5V0 BUS AND IT MAKE THE 6 BULK # POWER RAILS THAT ARE USED BY THE DK BOARD ITSELF. # # # FOR REFERENCE RECALL THE 6 DCDC CONVERTERS ON DK: # # OUTPUT # CONVERTER REF. POWER OUTPUT EXPECTED OUTPUT POWER TRENDS # NAME DESIG BUS VOLTAGE LOAD CAPACITY MODEL NUMBER # --------- ----- --------- ------- ----------- -------- ------------ # # DCDC1 1701 BULK_1V00 1.00 V ABOUT 1.4 A 3 A PTH04T260WAD # DCDC2 1731 BULK_1V05 1.05 V UNDER 3.0 A 6 A PTH04T230WAD # DCDC3 1761 BULK_1V2 1.20 V ABOUT 4.0 A 6 A PTH04T230WAD # DCDC4 1791 BULK_1V8 1.80 V UNDER 1.5 A 3 A PTH04T260WAD # DCDC5 1821 BULK_2V5 2.50 V ABOUT 1.4 A 3 A PTH04T260WAD # DCDC6 1851 BULK_3V3 3.30 V UNDER 1.5 A 3 A PTH04T260WAD # # # # DEFINE THE CONNECTIONS WITHIN THE DCDC POWER CONVERTER # --------------------------------------------------------- # # # INPUT POWER TO THE CONVERTER: NET 'BULK_5V0' R1791-2 # POWER TO THE CURRENT SENSE RESISTOR NET 'DCDC4_CSR_TO_L' R1791-3 # POWER FROM THE CURRENT SENSE NET 'DCDC4_CSR_TO_L' L1791-1 # RESISTOR TO THE FILTER INDUCTOR NET 'DCDC4_INPUT' L1791-2 # POWER FEED TO THE CONVERTER NET 'DCDC4_INPUT' C1791-1 C1792-1 # TANTALUM INPUT CAPS NET 'DCDC4_INPUT' C1793-1 C1794-1 # TANTALUM INPUT CAPS NET 'DCDC4_INPUT' C1795-2 C1796-1 # CERAMIC INPUT CAPS NET 'DCDC4_INPUT' C1797-2 C1798-2 # CERAMIC INPUT CAPS NET 'DCDC4_INPUT' DCDC4-2 # POWER INPUT TO THE CONVERTER - PIN #2 NET 'GROUND' C1791-2 C1792-2 # TANTALUM CAP GROUNDS NET 'GROUND' C1793-2 C1794-2 # TALTALUM CAP GROUNDS NET 'GROUND' C1795-1 C1796-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1797-1 C1798-1 # CERAMIC CAP GROUNDS # # POWER OUTPUT FROM THE CONVERTER: NET 'BULK_1V8' DCDC4-4 # OUTPUT POWER FROM THE CONVERTER - PIN #4 NET 'BULK_1V8' C1799-1 C1800-1 # CERAMIC OUTPUT CAPS NET 'BULK_1V8' C1801-2 C1802-1 # CERAMIC OUTPUT CAPS NET 'BULK_1V8' C1803-1 C1804-1 # TANTALUM OUTPUT CAPS NET 'BULK_1V8' C1805-1 C1806-1 # TANTALUM OUTPUT CAPS NET 'BULK_1V8' DZ1791-1 # OUTPUT ZENER CLAMP NET 'GROUND' C1799-2 C1800-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1801-1 C1802-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1803-2 C1804-2 # TANTALUM CAP GROUNDS NET 'GROUND' C1805-2 C1806-2 # TANTALUM CAP GROUNDS NET 'GROUND' DZ1791-2 # ZENER CLAMP GROUND # # DC/DC CONVERTER GROUND PINS NET 'GROUND' DCDC4-3 # CONVERTER GROUND PIN - PIN #3 NET 'GROUND' DCDC4-31 DCDC4-32 # CONVERTER AUXILIARY GROUND PINS # # DC/DC CONVERTER TRACKING PIN NET 'DCDC_CONV_TRACK' DCDC4-9 # TRACK PIN OF THIS DCDC CONVERTER - PIN #9 # # DC/DC CONVERTER FEEDBACK REMOTE SENSE PINS NET 'BULK_1V8' AKA1791-2 # POSITIVE SENSE REMOTE CONNECTION NET 'DCDC4_SEN_POS' AKA1791-1 DCDC4-5 # POSITIVE SENSE INPUT PIN - PIN #5 NET 'GROUND' AKA1792-2 # NEGATIVE SENSE REMOTE CONNECTION NET 'DCDC4_SEN_NEG' AKA1792-1 DCDC4-6 # NEGATIVE SENSE INPUT PIN - PIN #6 # # DC/DC CONVERTER OUTPUT VOLTAGE RSET RESISTOR # WITH CAPACITOR ACROSS THE VARIABLE PART OF THE VOUT RSET RESISTOR # # NOTE: GROUND REFERENCE NOT NEGATIVE SENSE REFERENCE NET 'GROUND' R1793-1 R1793-2 # WANT TRIM POT CW TRUNING TO: NET 'DCDC4_VAR_FIX' R1793-3 # REDUCE THE RESISTANCE AND NET 'DCDC4_VAR_FIX' R1792-2 # INCREASE THE OUTPUT VOLTAGE NET 'DCDC4_VO_ADJ' R1792-1 DCDC4-7 # CONVERTER RSET VOUT ADJ PIN - PIN #7 NET 'DCDC4_VAR_FIX' C1807-1 # CAPACITOR ACROSS THE NET 'GROUND' C1807-2 # VOUT TRIM POT RESISTOR # # DC/DC CONVERTER TRANSIENT RESPONSE CONTROL PIN NET 'DCDC4_TRC_PIN' R1794-2 DCDC4-8 # TRANSIENT RESPONSE CONTROL PIN - PIN #8 NET 'DCDC4_SEN_POS' R1794-1 # TRANSIENT RESPONSE RESISTOR # # DC/DC CONVERTER INH-UVLO PIN AND RESISTOR NET 'DCDC4_INH_UVLO' R1795-1 DCDC4-10 # INH-UVLO PIN #10 NET 'GROUND' R1795-2 # GROUND END OF UVLO RESISTOR # # DC/DC CONVERTER SYNC PIN TIED TO GROUND VIA TRACE NET 'DCDC4_SYNC' AKA1793-1 DCDC4-1 # CONVERTER'S SYNC PIN - PIN #1 NET 'GROUND' AKA1793-2 # TIE SYNC PIN TO GROUND # # CURRENT SENSE RESISTOR TO FILTER AND TO CURRENT MONITOR CONNECTOR PINS NET 'DCDC4_CS_POS' R1791-4 R1796-1 # CURRENT SENSE RES. TO FILTER RES. NET 'DCDC4_CS_NEG' R1791-1 R1797-1 # CURRENT SENSE RES. TO FILTER RES. NET 'IMON_POS_BULK_1V8' R1796-2 C1808-1 # CURRENT MONITOR FILTER RES CAP PIN NET 'IMON_NEG_BULK_1V8' R1797-2 C1810-2 # CURRENT MONITOR FILTER RES CAP PIN NET 'IMON_POS_BULK_1V8' C1809-1 # CURRENT MONITOR SHUNT CAP NET 'IMON_NEG_BULK_1V8' C1809-2 # CURRENT MONITOR SHUNT CAP NET 'GROUND' C1808-2 C1810-1 # CURRENT MONITOR FILTER CAP GROUNDS # # VOLTAGE MONITOR FILTER AND TO VOLTAGE MONITOR CONNECTOR PIN NET 'BULK_1V8' R1798-1 # VOLTAGE MONITOR FILTER RESISTOR NET 'VMON_BULK_1V8' R1798-2 C1811-1 # VOLTAGE MONITOR FILTER RES CAP PIN NET 'GROUND' C1811-2 # VOLTAGE MONITOR FILTER CAP GROUND # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:40 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #5/6 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # DCDC CONVERTER NET LIST TEMPLATE FILE # ----------------========--========------- # # # ORIGINAL REV. 5-FEB-2023 # MOST RECENT REV. 17-NOV-2023 # # # # THIS TEMPLATE FILE HOLDS THE NETS FOR THE DK # DC/DC POWER CONVERTERS. THESE CONVERTERS RUN # FROM THE BULK_5V0 BUS AND IT MAKE THE 6 BULK # POWER RAILS THAT ARE USED BY THE DK BOARD ITSELF. # # # FOR REFERENCE RECALL THE 6 DCDC CONVERTERS ON DK: # # OUTPUT # CONVERTER REF. POWER OUTPUT EXPECTED OUTPUT POWER TRENDS # NAME DESIG BUS VOLTAGE LOAD CAPACITY MODEL NUMBER # --------- ----- --------- ------- ----------- -------- ------------ # # DCDC1 1701 BULK_1V00 1.00 V ABOUT 1.4 A 3 A PTH04T260WAD # DCDC2 1731 BULK_1V05 1.05 V UNDER 3.0 A 6 A PTH04T230WAD # DCDC3 1761 BULK_1V2 1.20 V ABOUT 4.0 A 6 A PTH04T230WAD # DCDC4 1791 BULK_1V8 1.80 V UNDER 1.5 A 3 A PTH04T260WAD # DCDC5 1821 BULK_2V5 2.50 V ABOUT 1.4 A 3 A PTH04T260WAD # DCDC6 1851 BULK_3V3 3.30 V UNDER 1.5 A 3 A PTH04T260WAD # # # # DEFINE THE CONNECTIONS WITHIN THE DCDC POWER CONVERTER # --------------------------------------------------------- # # # INPUT POWER TO THE CONVERTER: NET 'BULK_5V0' R1821-2 # POWER TO THE CURRENT SENSE RESISTOR NET 'DCDC5_CSR_TO_L' R1821-3 # POWER FROM THE CURRENT SENSE NET 'DCDC5_CSR_TO_L' L1821-1 # RESISTOR TO THE FILTER INDUCTOR NET 'DCDC5_INPUT' L1821-2 # POWER FEED TO THE CONVERTER NET 'DCDC5_INPUT' C1821-1 C1822-1 # TANTALUM INPUT CAPS NET 'DCDC5_INPUT' C1823-1 C1824-1 # TANTALUM INPUT CAPS NET 'DCDC5_INPUT' C1825-2 C1826-1 # CERAMIC INPUT CAPS NET 'DCDC5_INPUT' C1827-2 C1828-2 # CERAMIC INPUT CAPS NET 'DCDC5_INPUT' DCDC5-2 # POWER INPUT TO THE CONVERTER - PIN #2 NET 'GROUND' C1821-2 C1822-2 # TANTALUM CAP GROUNDS NET 'GROUND' C1823-2 C1824-2 # TALTALUM CAP GROUNDS NET 'GROUND' C1825-1 C1826-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1827-1 C1828-1 # CERAMIC CAP GROUNDS # # POWER OUTPUT FROM THE CONVERTER: NET 'BULK_2V5' DCDC5-4 # OUTPUT POWER FROM THE CONVERTER - PIN #4 NET 'BULK_2V5' C1829-1 C1830-1 # CERAMIC OUTPUT CAPS NET 'BULK_2V5' C1831-2 C1832-1 # CERAMIC OUTPUT CAPS NET 'BULK_2V5' C1833-1 C1834-1 # TANTALUM OUTPUT CAPS NET 'BULK_2V5' C1835-1 C1836-1 # TANTALUM OUTPUT CAPS NET 'BULK_2V5' DZ1821-1 # OUTPUT ZENER CLAMP NET 'GROUND' C1829-2 C1830-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1831-1 C1832-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1833-2 C1834-2 # TANTALUM CAP GROUNDS NET 'GROUND' C1835-2 C1836-2 # TANTALUM CAP GROUNDS NET 'GROUND' DZ1821-2 # ZENER CLAMP GROUND # # DC/DC CONVERTER GROUND PINS NET 'GROUND' DCDC5-3 # CONVERTER GROUND PIN - PIN #3 NET 'GROUND' DCDC5-31 DCDC5-32 # CONVERTER AUXILIARY GROUND PINS # # DC/DC CONVERTER TRACKING PIN NET 'DCDC_CONV_TRACK' DCDC5-9 # TRACK PIN OF THIS DCDC CONVERTER - PIN #9 # # DC/DC CONVERTER FEEDBACK REMOTE SENSE PINS NET 'BULK_2V5' AKA1821-2 # POSITIVE SENSE REMOTE CONNECTION NET 'DCDC5_SEN_POS' AKA1821-1 DCDC5-5 # POSITIVE SENSE INPUT PIN - PIN #5 NET 'GROUND' AKA1822-2 # NEGATIVE SENSE REMOTE CONNECTION NET 'DCDC5_SEN_NEG' AKA1822-1 DCDC5-6 # NEGATIVE SENSE INPUT PIN - PIN #6 # # DC/DC CONVERTER OUTPUT VOLTAGE RSET RESISTOR # WITH CAPACITOR ACROSS THE VARIABLE PART OF THE VOUT RSET RESISTOR # # NOTE: GROUND REFERENCE NOT NEGATIVE SENSE REFERENCE NET 'GROUND' R1823-1 R1823-2 # WANT TRIM POT CW TRUNING TO: NET 'DCDC5_VAR_FIX' R1823-3 # REDUCE THE RESISTANCE AND NET 'DCDC5_VAR_FIX' R1822-2 # INCREASE THE OUTPUT VOLTAGE NET 'DCDC5_VO_ADJ' R1822-1 DCDC5-7 # CONVERTER RSET VOUT ADJ PIN - PIN #7 NET 'DCDC5_VAR_FIX' C1837-1 # CAPACITOR ACROSS THE NET 'GROUND' C1837-2 # VOUT TRIM POT RESISTOR # # DC/DC CONVERTER TRANSIENT RESPONSE CONTROL PIN NET 'DCDC5_TRC_PIN' R1824-2 DCDC5-8 # TRANSIENT RESPONSE CONTROL PIN - PIN #8 NET 'DCDC5_SEN_POS' R1824-1 # TRANSIENT RESPONSE RESISTOR # # DC/DC CONVERTER INH-UVLO PIN AND RESISTOR NET 'DCDC5_INH_UVLO' R1825-1 DCDC5-10 # INH-UVLO PIN #10 NET 'GROUND' R1825-2 # GROUND END OF UVLO RESISTOR # # DC/DC CONVERTER SYNC PIN TIED TO GROUND VIA TRACE NET 'DCDC5_SYNC' AKA1823-1 DCDC5-1 # CONVERTER'S SYNC PIN - PIN #1 NET 'GROUND' AKA1823-2 # TIE SYNC PIN TO GROUND # # CURRENT SENSE RESISTOR TO FILTER AND TO CURRENT MONITOR CONNECTOR PINS NET 'DCDC5_CS_POS' R1821-4 R1826-1 # CURRENT SENSE RES. TO FILTER RES. NET 'DCDC5_CS_NEG' R1821-1 R1827-1 # CURRENT SENSE RES. TO FILTER RES. NET 'IMON_POS_BULK_2V5' R1826-2 C1838-1 # CURRENT MONITOR FILTER RES CAP PIN NET 'IMON_NEG_BULK_2V5' R1827-2 C1840-2 # CURRENT MONITOR FILTER RES CAP PIN NET 'IMON_POS_BULK_2V5' C1839-1 # CURRENT MONITOR SHUNT CAP NET 'IMON_NEG_BULK_2V5' C1839-2 # CURRENT MONITOR SHUNT CAP NET 'GROUND' C1838-2 C1840-1 # CURRENT MONITOR FILTER CAP GROUNDS # # VOLTAGE MONITOR FILTER AND TO VOLTAGE MONITOR CONNECTOR PIN NET 'BULK_2V5' R1828-1 # VOLTAGE MONITOR FILTER RESISTOR NET 'VMON_BULK_2V5' R1828-2 C1841-1 # VOLTAGE MONITOR FILTER RES CAP PIN NET 'GROUND' C1841-2 # VOLTAGE MONITOR FILTER CAP GROUND # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:40 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #6/6 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # DCDC CONVERTER NET LIST TEMPLATE FILE # ----------------========--========------- # # # ORIGINAL REV. 5-FEB-2023 # MOST RECENT REV. 17-NOV-2023 # # # # THIS TEMPLATE FILE HOLDS THE NETS FOR THE DK # DC/DC POWER CONVERTERS. THESE CONVERTERS RUN # FROM THE BULK_5V0 BUS AND IT MAKE THE 6 BULK # POWER RAILS THAT ARE USED BY THE DK BOARD ITSELF. # # # FOR REFERENCE RECALL THE 6 DCDC CONVERTERS ON DK: # # OUTPUT # CONVERTER REF. POWER OUTPUT EXPECTED OUTPUT POWER TRENDS # NAME DESIG BUS VOLTAGE LOAD CAPACITY MODEL NUMBER # --------- ----- --------- ------- ----------- -------- ------------ # # DCDC1 1701 BULK_1V00 1.00 V ABOUT 1.4 A 3 A PTH04T260WAD # DCDC2 1731 BULK_1V05 1.05 V UNDER 3.0 A 6 A PTH04T230WAD # DCDC3 1761 BULK_1V2 1.20 V ABOUT 4.0 A 6 A PTH04T230WAD # DCDC4 1791 BULK_1V8 1.80 V UNDER 1.5 A 3 A PTH04T260WAD # DCDC5 1821 BULK_2V5 2.50 V ABOUT 1.4 A 3 A PTH04T260WAD # DCDC6 1851 BULK_3V3 3.30 V UNDER 1.5 A 3 A PTH04T260WAD # # # # DEFINE THE CONNECTIONS WITHIN THE DCDC POWER CONVERTER # --------------------------------------------------------- # # # INPUT POWER TO THE CONVERTER: NET 'BULK_5V0' R1851-2 # POWER TO THE CURRENT SENSE RESISTOR NET 'DCDC6_CSR_TO_L' R1851-3 # POWER FROM THE CURRENT SENSE NET 'DCDC6_CSR_TO_L' L1851-1 # RESISTOR TO THE FILTER INDUCTOR NET 'DCDC6_INPUT' L1851-2 # POWER FEED TO THE CONVERTER NET 'DCDC6_INPUT' C1851-1 C1852-1 # TANTALUM INPUT CAPS NET 'DCDC6_INPUT' C1853-1 C1854-1 # TANTALUM INPUT CAPS NET 'DCDC6_INPUT' C1855-2 C1856-1 # CERAMIC INPUT CAPS NET 'DCDC6_INPUT' C1857-2 C1858-2 # CERAMIC INPUT CAPS NET 'DCDC6_INPUT' DCDC6-2 # POWER INPUT TO THE CONVERTER - PIN #2 NET 'GROUND' C1851-2 C1852-2 # TANTALUM CAP GROUNDS NET 'GROUND' C1853-2 C1854-2 # TALTALUM CAP GROUNDS NET 'GROUND' C1855-1 C1856-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1857-1 C1858-1 # CERAMIC CAP GROUNDS # # POWER OUTPUT FROM THE CONVERTER: NET 'BULK_3V3' DCDC6-4 # OUTPUT POWER FROM THE CONVERTER - PIN #4 NET 'BULK_3V3' C1859-1 C1860-1 # CERAMIC OUTPUT CAPS NET 'BULK_3V3' C1861-2 C1862-1 # CERAMIC OUTPUT CAPS NET 'BULK_3V3' C1863-1 C1864-1 # TANTALUM OUTPUT CAPS NET 'BULK_3V3' C1865-1 C1866-1 # TANTALUM OUTPUT CAPS NET 'BULK_3V3' DZ1851-1 # OUTPUT ZENER CLAMP NET 'GROUND' C1859-2 C1860-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1861-1 C1862-2 # CERAMIC CAP GROUNDS NET 'GROUND' C1863-2 C1864-2 # TANTALUM CAP GROUNDS NET 'GROUND' C1865-2 C1866-2 # TANTALUM CAP GROUNDS NET 'GROUND' DZ1851-2 # ZENER CLAMP GROUND # # DC/DC CONVERTER GROUND PINS NET 'GROUND' DCDC6-3 # CONVERTER GROUND PIN - PIN #3 NET 'GROUND' DCDC6-31 DCDC6-32 # CONVERTER AUXILIARY GROUND PINS # # DC/DC CONVERTER TRACKING PIN NET 'DCDC_CONV_TRACK' DCDC6-9 # TRACK PIN OF THIS DCDC CONVERTER - PIN #9 # # DC/DC CONVERTER FEEDBACK REMOTE SENSE PINS NET 'BULK_3V3' AKA1851-2 # POSITIVE SENSE REMOTE CONNECTION NET 'DCDC6_SEN_POS' AKA1851-1 DCDC6-5 # POSITIVE SENSE INPUT PIN - PIN #5 NET 'GROUND' AKA1852-2 # NEGATIVE SENSE REMOTE CONNECTION NET 'DCDC6_SEN_NEG' AKA1852-1 DCDC6-6 # NEGATIVE SENSE INPUT PIN - PIN #6 # # DC/DC CONVERTER OUTPUT VOLTAGE RSET RESISTOR # WITH CAPACITOR ACROSS THE VARIABLE PART OF THE VOUT RSET RESISTOR # # NOTE: GROUND REFERENCE NOT NEGATIVE SENSE REFERENCE NET 'GROUND' R1853-1 R1853-2 # WANT TRIM POT CW TRUNING TO: NET 'DCDC6_VAR_FIX' R1853-3 # REDUCE THE RESISTANCE AND NET 'DCDC6_VAR_FIX' R1852-2 # INCREASE THE OUTPUT VOLTAGE NET 'DCDC6_VO_ADJ' R1852-1 DCDC6-7 # CONVERTER RSET VOUT ADJ PIN - PIN #7 NET 'DCDC6_VAR_FIX' C1867-1 # CAPACITOR ACROSS THE NET 'GROUND' C1867-2 # VOUT TRIM POT RESISTOR # # DC/DC CONVERTER TRANSIENT RESPONSE CONTROL PIN NET 'DCDC6_TRC_PIN' R1854-2 DCDC6-8 # TRANSIENT RESPONSE CONTROL PIN - PIN #8 NET 'DCDC6_SEN_POS' R1854-1 # TRANSIENT RESPONSE RESISTOR # # DC/DC CONVERTER INH-UVLO PIN AND RESISTOR NET 'DCDC6_INH_UVLO' R1855-1 DCDC6-10 # INH-UVLO PIN #10 NET 'GROUND' R1855-2 # GROUND END OF UVLO RESISTOR # # DC/DC CONVERTER SYNC PIN TIED TO GROUND VIA TRACE NET 'DCDC6_SYNC' AKA1853-1 DCDC6-1 # CONVERTER'S SYNC PIN - PIN #1 NET 'GROUND' AKA1853-2 # TIE SYNC PIN TO GROUND # # CURRENT SENSE RESISTOR TO FILTER AND TO CURRENT MONITOR CONNECTOR PINS NET 'DCDC6_CS_POS' R1851-4 R1856-1 # CURRENT SENSE RES. TO FILTER RES. NET 'DCDC6_CS_NEG' R1851-1 R1857-1 # CURRENT SENSE RES. TO FILTER RES. NET 'IMON_POS_BULK_3V3' R1856-2 C1868-1 # CURRENT MONITOR FILTER RES CAP PIN NET 'IMON_NEG_BULK_3V3' R1857-2 C1870-2 # CURRENT MONITOR FILTER RES CAP PIN NET 'IMON_POS_BULK_3V3' C1869-1 # CURRENT MONITOR SHUNT CAP NET 'IMON_NEG_BULK_3V3' C1869-2 # CURRENT MONITOR SHUNT CAP NET 'GROUND' C1868-2 C1870-1 # CURRENT MONITOR FILTER CAP GROUNDS # # VOLTAGE MONITOR FILTER AND TO VOLTAGE MONITOR CONNECTOR PIN NET 'BULK_3V3' R1858-1 # VOLTAGE MONITOR FILTER RESISTOR NET 'VMON_BULK_3V3' R1858-2 C1871-1 # VOLTAGE MONITOR FILTER RES CAP PIN NET 'GROUND' C1871-2 # VOLTAGE MONITOR FILTER CAP GROUND # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # # POWER INPUT NET LIST # ----------------------- # # INITIAL REV. 7-FEB-2023 # CURRENT REV. 25-NOV-2023 # # THIS NET LIST FILE CONTAINS ALL OF THE CONNECTIONS WITHIN # THE POWER INPUT FILTER AND WITHIN THE +100 V TO +5 V # CONVERTER. # # THIS NET LIST FILE ALSO ASSIGNS NET NAMES TO ALL # 26 PINS IN THE MAIN CABLE CONNECTOR J1. # # # POWER INPUT FILTER NETS # NET 'POWER_INPUT' C1651-2 C1652-2 L1651-1 # INPUT TO THE NET 'POWER RETURN' C1651-1 C1652-1 L1651-4 # COMMON MODE CHOKE NET 'INTER_CHOKE_POS' L1651-2 C1653-1 # INTER CHOKE NET 'INTER_CHOKE_POS' C1654-2 C1655-2 L1652-2 # POSITIVE NET 'FLTRD_POWER_POS' L1652-1 C1656-2 # FILTERED NET 'FLTRD_POWER_POS' C1657-2 C1658-2 # +100 V POWER NET 'FLTRD_RTN_POWER' L1651-3 C1653-2 # FILTERED NET 'FLTRD_RTN_POWER' C1654-1 C1655-1 # RETURN NET 'FLTRD_RTN_POWER' C1656-1 # POWER NET 'FLTRD_RTN_POWER' C1657-1 C1658-1 # # # INPUT POWER RETURN TO SIGNAL GROUND LINK (IF WANTED) # # IF NEEDED, NET 'POWER RETURN' R1651-1 # CONTROL THE POTENTIAL DIFFERENCE NET 'GROUND' R1651-2 # BETWEEN POWER RETURN & SIGNAL GROUND # # POWER INTO THE 100 V TO 5 V CONVERTER # NET 'FLTRD_POWER_POS' DCDC20-1 # POSITIVE 100V TO CONVERTER NET 'FLTRD_RTN_POWER' DCDC20-2 # POWER RETURN FROM CONVERTER # # REMOTE ON/OFF CONTROL OF THE 100 V TO 5 V CONVERTER # NET 'NO_CONN_DCDC20_PIN_6' DCDC20-6 # FLOAT THIS PIN FOR ALWAYS ON # # OUTPUT FROM THE 100 V TO 5 V CONVERTER # NET 'BULK_5V0' DCDC20-3 # CONVERTER'S POSITIVE NET 'BULK_5V0' C1659-2 C1660-2 # OUTPUT AND CERAMIC NET 'BULK_5V0' C1661-2 C1662-2 # FILTER CAPACITORS NET 'GROUND' DCDC20-5 # CONVERTER'S NEGATIVE NET 'GROUND' C1659-1 C1660-1 # OUTPUT AND CERAMIC NET 'GROUND' C1661-1 C1662-1 # FILTER CAPACITORS # # VOLTAGE TRIM RESISTORS ON THE 100 V TO 5 V CONVERTER # NET 'BULK_5V0' R1652-2 # RESISTORS TO NET 'TRIM_BULK_5V0' R1652-1 DCDC20-4 # TRIM THE NET 'TRIM_BULK_5V0' R1653-2 # BULK_5V0 NET 'GROUND' R1653-1 # VOLTAGE # # VOLTAGE MONITOR FILTER ON THE 100 V TO 5 V CONVERTER # NET 'BULK_5V0' R1654-1 # VOLTAGE MONITOR NET 'VMON_BULK_5V0' R1654-2 C1663-2 # FILTER ON THE NET 'GROUND' C1663-1 # BULK_5V0 # # ASSIGN NET_NAMES TO ALL PIN ON THE MAIN CABLE J1 CONNECTOR # NET 'GROUND' J1-1 # MODULE SIGNAL GROUND NET 'GROUND' J1-2 # MODULE SIGNAL GROUND NET 'NO_CONN_J1_PIN_3' J1-3 # OPEN GUARD AROUND 100V NET 'NO_CONN_J1_PIN_4' J1-4 # OPEN GUARD AROUND 100V NET 'POWER_INPUT' J1-5 # +100 VOLT INPUT POWER NET 'NO_CONN_J1_PIN_6' J1-6 # OPEN GUARD AROUND 100V NET 'NO_CONN_J1_PIN_7' J1-7 # OPEN GUARD AROUND 100V NET 'POWER RETURN' J1-8 # RETURN CONDUCTOR FOR INPUT POWER NET 'NO_CONN_J1_PIN_9' J1-9 # OPEN GUARD AROUND 100V NET 'NO_CONN_J1_PIN_10' J1-10 # OPEN GUARD AROUND 100V NET 'GROUND' J1-11 # MODULE SIGNAL GROUND NET 'GROUND' J1-12 # MODULE SIGNAL GROUND NET 'RS485_DOWN_DIR' J1-13 # RE-PROGRAMM RS-485 NET 'RS485_DOWN_CMP' J1-14 # DOWN NET 'NO_CONN_J1_PIN_15' J1-15 # SPARE PIN - NO CONNECTION NET 'NO_CONN_J1_PIN_16' J1-16 # SPARE PIN - NO CONNECTION NET 'NO_CONN_J1_PIN_17' J1-17 # SPARE PIN - NO CONNECTION NET 'NO_CONN_J1_PIN_18' J1-18 # SPARE PIN - NO CONNECTION NET 'NO_CONN_J1_PIN_19' J1-19 # SPARE PIN - NO CONNECTION NET 'NO_CONN_J1_PIN_20' J1-20 # SPARE PIN - NO CONNECTION NET 'GROUND' J1-21 # MODULE SIGNAL GROUND NET 'GROUND' J1-22 # MODULE SIGNAL GROUND NET 'RS485_UP_DIR' J1-23 # RE-PROGRAMM RS-485 NET 'RS485_UP_CMP' J1-24 # UP NET 'GROUND' J1-25 # MODULE SIGNAL GROUND NET 'GROUND' J1-26 # MODULE SIGNAL GROUND NET 'GROUND' J1-27 # MOUNTING SCREW GROUND NET 'GROUND' J1-28 # MOUNTING SCREW GROUND # # ALWAYS ON 3V3 POWER SUPPLY NET LIST # --------------------------------------------- # # # INITIAL REV. 14-NOV-2022 # CURRENT REV. 15-NOV-2023 # # # THIS NET LIST HOLDS THE ALWAYS ON 3V3 POWER SUPPLY # NET LIST. # # # THE COMPONENTS FOR THE ALWAYS ON 3V3 POWER SUPPLY # ARE IN THE RANGE 1971 TO 1976. # # # BULK_5V0 POWER INTO THE ALWAYS ON 3V3 POWER SUPPLY # NET 'BULK_5V0' L1971-2 # BULK POWER INTO FILTER NET 'CNST_FLTR_POW' L1971-1 # FILTERED BULK POWER NET 'CNST_FLTR_POW' C1971-2 C1972-1 U1971-5 # FILTERED POWER INTO REGULATOR NET 'GROUND' C1971-1 C1972-2 # GROUND SIDE OF FILTER CAPS NET 'GROUND' U1971-2 U1971-3 U1971-4 # REGULATOR GROUNDS AND THERMALS NET 'CNST_FLTR_POW' U1971-1 # ENABLE REGULATOR # # ALWAYS_ON_3V3 POWER OUTPUT # NET 'CNST_3V3' C1973-1 C1974-2 U1971-6 # POWER OUTPUT NET 'GROUND' C1973-2 C1974-1 # # ALWAYS_ON_3V3 FEEDBACK RESISTORS # NET 'CNST_3V3' R1971-2 NET 'CNST_3V3_FB' R1971-1 R1972-1 U1971-7 # FEEDBACK TO REGULATOR NET 'GROUND' R1972-2 # # REGULATOR START-UP TIMING # NET 'CNST_3V3_START' C1975-1 U1971-8 # REGULATOR START-UP TIMING CAP NET 'GROUND' C1975-2 # # MONITOR FOR THE ALWAYS ON 3V3 POWER SUPPLY # NET 'CNST_3V3' R1973-2 NET 'VMON_CNST_3V3' R1973-1 C1976-1 NET 'GROUND' C1976-2 # # POWER SUPPLY MONITOR NET LIST # --------------------------------------------- # # # INITIAL REV. 8-NOV-2022 # CURRENT REV. 17-NOV-2023 # # # THIS NET LIST HOLDS THE POWER SUPPLY MONITOR NETS # (BOTH VOLTAGE AND CURRENT) THAT RUN TO THE J11 # POWER SUPPLY MONITOR CONNECTOR. # # PINOUT OF THE J11 POWER SUPPLY MONITOR CONNECTOR: # # # CURRENTLY PINS 33:40 ARE NOT ASSIGNED TO # TO A MONITOR FUNCTION OR HAVE AN ASSIGNED NET. # # # # NOW THE NETS THAT RUN TO J11: # # # MONITOR FOR THE 100 V TO 5 V COMVERTER OUTPUT: # NET 'VMON_BULK_5V0' J11-1 NET 'GROUND' J11-2 # # NOW MONITOR THE VOLTAGE OUTPUT AND THE CURRENT INPUT # OF THE 6 DCDC CONVERTERS: # NET 'VMON_BULK_1V00' J11-3 NET 'GROUND' J11-4 NET 'IMON_POS_BULK_1V00' J11-5 NET 'IMON_NEG_BULK_1V00' J11-6 NET 'VMON_BULK_1V05' J11-7 NET 'GROUND' J11-8 NET 'IMON_POS_BULK_1V05' J11-9 NET 'IMON_NEG_BULK_1V05' J11-10 NET 'VMON_BULK_1V2' J11-11 NET 'GROUND' J11-12 NET 'IMON_POS_BULK_1V2' J11-13 NET 'IMON_NEG_BULK_1V2' J11-14 NET 'VMON_BULK_1V8' J11-15 NET 'GROUND' J11-16 NET 'IMON_POS_BULK_1V8' J11-17 NET 'IMON_NEG_BULK_1V8' J11-18 NET 'VMON_BULK_2V5' J11-19 NET 'GROUND' J11-20 NET 'IMON_POS_BULK_2V5' J11-21 NET 'IMON_NEG_BULK_2V5' J11-22 NET 'VMON_BULK_3V3' J11-23 NET 'GROUND' J11-24 NET 'IMON_POS_BULK_3V3' J11-25 NET 'IMON_NEG_BULK_3V3' J11-26 # # NOW MONITOR THE VOLTAGE OUTPUT OF THE # - CONSTANT ON 3V3 REGULATOR # - TERMINATION SUPPLY FOR THE FPGA DDR4 REFERENCE # - TERMINATION SUPPLY FOR THE CPU DDR4 REFERENCE # NET 'VMON_CNST_3V3' J11-27 NET 'GROUND' J11-28 NET 'VMON_FPGA_DDR4_TERM' J11-29 NET 'GROUND' J11-30 NET 'VMON_CPU_DDR4_TERM' J11-31 NET 'GROUND' J11-32 # # FOR NOW THE REST OF THE J11 PINS # ARE NO CONNECT NETS. # NET 'NO_CONN_J11_PIN_33' J11-33 NET 'NO_CONN_J11_PIN_34' J11-34 NET 'NO_CONN_J11_PIN_35' J11-35 NET 'NO_CONN_J11_PIN_36' J11-36 NET 'NO_CONN_J11_PIN_37' J11-37 NET 'NO_CONN_J11_PIN_38' J11-38 NET 'NO_CONN_J11_PIN_39' J11-39 NET 'NO_CONN_J11_PIN_40' J11-40 # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #1/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH1_INPUT_DIR' TRN1-6 # COAX INPUT CENTER CONDUCTOR NET 'CH1_INPUT_CMP' TRN1-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH1_INPUT_CMP' JMP1-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP1-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH1_IN_SPLIT_DIR' TRN1-1 TVS1-1 # INPUT SEC TO ESD DIODE DIR NET 'CH1_IN_SPLIT_CMP' TRN1-3 TVS1-2 # INPUT SEC TO ESD DIODE CMP NET 'CH1_IN_SPLIT_DIR' TRN17-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH1_IN_SPLIT_CMP' TRN17-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN1-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH1_ADC_IN_DIR' TRN17-5 # TERM AND ADC IN DIR NET 'CH1_ADC_IN_DIR' R683-1 # TERM AND ADC IN DIR NET 'CH1_TERM_DIR' R683-2 # TERMINATOR DIR NET 'CH1_TERM_DIR' C685-1 # TERMINATOR DIR NET 'CH1_TERM_DIR' C686-2 # TERMINATOR DIR NET 'GROUND' C685-2 C686-1 # GROUND NET 'CH1_ADC_IN_CMP' TRN17-3 # TERM AND ADC IN CMP NET 'CH1_ADC_IN_CMP' R684-1 # TERM AND ADC IN CMP NET 'CH1_TERM_CMP' R684-2 # TERMINATOR CMP NET 'CH1_TERM_CMP' C687-1 # TERMINATOR CMP NET 'CH1_TERM_CMP' C688-2 # TERMINATOR CMP NET 'GROUND' C687-2 C688-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH1_BIAS_DIR' TRN17-2 # WINDING LOW NET 'CH1_BIAS_DIR' R682-2 # WINDING LOW TO RES NET 'CH1_BIAS_DIR' C683-2 # WINDING LOW TO CAP NET 'CH1_BIAS_DIR' C684-2 # WINDING LOW TO CAP NET 'GROUND' R682-1 # GROUND RES NET 'GROUND' C683-1 # GROUND CAP NET 'GROUND' C684-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH1_BIAS_CMP' TRN17-4 # WINDING LOW NET 'CH1_BIAS_CMP' C681-1 # WINDING LOW TO CAP NET 'CH1_BIAS_CMP' C682-1 # WINDING LOW TO CAP NET 'CH1_BIAS_CMP' R681-1 # WINDING LOW TO RES NET 'GROUND' C681-2 # GROUND CAP NET 'GROUND' C682-2 # GROUND CAP NET 'GROUND' R681-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #2/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH2_INPUT_DIR' TRN2-6 # COAX INPUT CENTER CONDUCTOR NET 'CH2_INPUT_CMP' TRN2-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH2_INPUT_CMP' JMP2-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP2-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH2_IN_SPLIT_DIR' TRN2-1 TVS2-1 # INPUT SEC TO ESD DIODE DIR NET 'CH2_IN_SPLIT_CMP' TRN2-3 TVS2-2 # INPUT SEC TO ESD DIODE CMP NET 'CH2_IN_SPLIT_DIR' TRN18-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH2_IN_SPLIT_CMP' TRN18-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN2-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH2_ADC_IN_DIR' TRN18-5 # TERM AND ADC IN DIR NET 'CH2_ADC_IN_DIR' R693-1 # TERM AND ADC IN DIR NET 'CH2_TERM_DIR' R693-2 # TERMINATOR DIR NET 'CH2_TERM_DIR' C695-1 # TERMINATOR DIR NET 'CH2_TERM_DIR' C696-2 # TERMINATOR DIR NET 'GROUND' C695-2 C696-1 # GROUND NET 'CH2_ADC_IN_CMP' TRN18-3 # TERM AND ADC IN CMP NET 'CH2_ADC_IN_CMP' R694-1 # TERM AND ADC IN CMP NET 'CH2_TERM_CMP' R694-2 # TERMINATOR CMP NET 'CH2_TERM_CMP' C697-1 # TERMINATOR CMP NET 'CH2_TERM_CMP' C698-2 # TERMINATOR CMP NET 'GROUND' C697-2 C698-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH2_BIAS_DIR' TRN18-2 # WINDING LOW NET 'CH2_BIAS_DIR' R692-2 # WINDING LOW TO RES NET 'CH2_BIAS_DIR' C693-2 # WINDING LOW TO CAP NET 'CH2_BIAS_DIR' C694-2 # WINDING LOW TO CAP NET 'GROUND' R692-1 # GROUND RES NET 'GROUND' C693-1 # GROUND CAP NET 'GROUND' C694-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH2_BIAS_CMP' TRN18-4 # WINDING LOW NET 'CH2_BIAS_CMP' C691-1 # WINDING LOW TO CAP NET 'CH2_BIAS_CMP' C692-1 # WINDING LOW TO CAP NET 'CH2_BIAS_CMP' R691-1 # WINDING LOW TO RES NET 'GROUND' C691-2 # GROUND CAP NET 'GROUND' C692-2 # GROUND CAP NET 'GROUND' R691-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #3/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH3_INPUT_DIR' TRN3-6 # COAX INPUT CENTER CONDUCTOR NET 'CH3_INPUT_CMP' TRN3-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH3_INPUT_CMP' JMP3-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP3-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH3_IN_SPLIT_DIR' TRN3-1 TVS3-1 # INPUT SEC TO ESD DIODE DIR NET 'CH3_IN_SPLIT_CMP' TRN3-3 TVS3-2 # INPUT SEC TO ESD DIODE CMP NET 'CH3_IN_SPLIT_DIR' TRN19-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH3_IN_SPLIT_CMP' TRN19-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN3-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH3_ADC_IN_DIR' TRN19-5 # TERM AND ADC IN DIR NET 'CH3_ADC_IN_DIR' R703-1 # TERM AND ADC IN DIR NET 'CH3_TERM_DIR' R703-2 # TERMINATOR DIR NET 'CH3_TERM_DIR' C705-1 # TERMINATOR DIR NET 'CH3_TERM_DIR' C706-2 # TERMINATOR DIR NET 'GROUND' C705-2 C706-1 # GROUND NET 'CH3_ADC_IN_CMP' TRN19-3 # TERM AND ADC IN CMP NET 'CH3_ADC_IN_CMP' R704-1 # TERM AND ADC IN CMP NET 'CH3_TERM_CMP' R704-2 # TERMINATOR CMP NET 'CH3_TERM_CMP' C707-1 # TERMINATOR CMP NET 'CH3_TERM_CMP' C708-2 # TERMINATOR CMP NET 'GROUND' C707-2 C708-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH3_BIAS_DIR' TRN19-2 # WINDING LOW NET 'CH3_BIAS_DIR' R702-2 # WINDING LOW TO RES NET 'CH3_BIAS_DIR' C703-2 # WINDING LOW TO CAP NET 'CH3_BIAS_DIR' C704-2 # WINDING LOW TO CAP NET 'GROUND' R702-1 # GROUND RES NET 'GROUND' C703-1 # GROUND CAP NET 'GROUND' C704-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH3_BIAS_CMP' TRN19-4 # WINDING LOW NET 'CH3_BIAS_CMP' C701-1 # WINDING LOW TO CAP NET 'CH3_BIAS_CMP' C702-1 # WINDING LOW TO CAP NET 'CH3_BIAS_CMP' R701-1 # WINDING LOW TO RES NET 'GROUND' C701-2 # GROUND CAP NET 'GROUND' C702-2 # GROUND CAP NET 'GROUND' R701-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #4/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH4_INPUT_DIR' TRN4-6 # COAX INPUT CENTER CONDUCTOR NET 'CH4_INPUT_CMP' TRN4-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH4_INPUT_CMP' JMP4-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP4-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH4_IN_SPLIT_DIR' TRN4-1 TVS4-1 # INPUT SEC TO ESD DIODE DIR NET 'CH4_IN_SPLIT_CMP' TRN4-3 TVS4-2 # INPUT SEC TO ESD DIODE CMP NET 'CH4_IN_SPLIT_DIR' TRN20-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH4_IN_SPLIT_CMP' TRN20-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN4-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH4_ADC_IN_DIR' TRN20-5 # TERM AND ADC IN DIR NET 'CH4_ADC_IN_DIR' R713-1 # TERM AND ADC IN DIR NET 'CH4_TERM_DIR' R713-2 # TERMINATOR DIR NET 'CH4_TERM_DIR' C715-1 # TERMINATOR DIR NET 'CH4_TERM_DIR' C716-2 # TERMINATOR DIR NET 'GROUND' C715-2 C716-1 # GROUND NET 'CH4_ADC_IN_CMP' TRN20-3 # TERM AND ADC IN CMP NET 'CH4_ADC_IN_CMP' R714-1 # TERM AND ADC IN CMP NET 'CH4_TERM_CMP' R714-2 # TERMINATOR CMP NET 'CH4_TERM_CMP' C717-1 # TERMINATOR CMP NET 'CH4_TERM_CMP' C718-2 # TERMINATOR CMP NET 'GROUND' C717-2 C718-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH4_BIAS_DIR' TRN20-2 # WINDING LOW NET 'CH4_BIAS_DIR' R712-2 # WINDING LOW TO RES NET 'CH4_BIAS_DIR' C713-2 # WINDING LOW TO CAP NET 'CH4_BIAS_DIR' C714-2 # WINDING LOW TO CAP NET 'GROUND' R712-1 # GROUND RES NET 'GROUND' C713-1 # GROUND CAP NET 'GROUND' C714-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH4_BIAS_CMP' TRN20-4 # WINDING LOW NET 'CH4_BIAS_CMP' C711-1 # WINDING LOW TO CAP NET 'CH4_BIAS_CMP' C712-1 # WINDING LOW TO CAP NET 'CH4_BIAS_CMP' R711-1 # WINDING LOW TO RES NET 'GROUND' C711-2 # GROUND CAP NET 'GROUND' C712-2 # GROUND CAP NET 'GROUND' R711-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #5/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH5_INPUT_DIR' TRN5-6 # COAX INPUT CENTER CONDUCTOR NET 'CH5_INPUT_CMP' TRN5-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH5_INPUT_CMP' JMP5-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP5-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH5_IN_SPLIT_DIR' TRN5-1 TVS5-1 # INPUT SEC TO ESD DIODE DIR NET 'CH5_IN_SPLIT_CMP' TRN5-3 TVS5-2 # INPUT SEC TO ESD DIODE CMP NET 'CH5_IN_SPLIT_DIR' TRN21-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH5_IN_SPLIT_CMP' TRN21-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN5-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH5_ADC_IN_DIR' TRN21-5 # TERM AND ADC IN DIR NET 'CH5_ADC_IN_DIR' R723-1 # TERM AND ADC IN DIR NET 'CH5_TERM_DIR' R723-2 # TERMINATOR DIR NET 'CH5_TERM_DIR' C725-1 # TERMINATOR DIR NET 'CH5_TERM_DIR' C726-2 # TERMINATOR DIR NET 'GROUND' C725-2 C726-1 # GROUND NET 'CH5_ADC_IN_CMP' TRN21-3 # TERM AND ADC IN CMP NET 'CH5_ADC_IN_CMP' R724-1 # TERM AND ADC IN CMP NET 'CH5_TERM_CMP' R724-2 # TERMINATOR CMP NET 'CH5_TERM_CMP' C727-1 # TERMINATOR CMP NET 'CH5_TERM_CMP' C728-2 # TERMINATOR CMP NET 'GROUND' C727-2 C728-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH5_BIAS_DIR' TRN21-2 # WINDING LOW NET 'CH5_BIAS_DIR' R722-2 # WINDING LOW TO RES NET 'CH5_BIAS_DIR' C723-2 # WINDING LOW TO CAP NET 'CH5_BIAS_DIR' C724-2 # WINDING LOW TO CAP NET 'GROUND' R722-1 # GROUND RES NET 'GROUND' C723-1 # GROUND CAP NET 'GROUND' C724-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH5_BIAS_CMP' TRN21-4 # WINDING LOW NET 'CH5_BIAS_CMP' C721-1 # WINDING LOW TO CAP NET 'CH5_BIAS_CMP' C722-1 # WINDING LOW TO CAP NET 'CH5_BIAS_CMP' R721-1 # WINDING LOW TO RES NET 'GROUND' C721-2 # GROUND CAP NET 'GROUND' C722-2 # GROUND CAP NET 'GROUND' R721-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #6/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH6_INPUT_DIR' TRN6-6 # COAX INPUT CENTER CONDUCTOR NET 'CH6_INPUT_CMP' TRN6-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH6_INPUT_CMP' JMP6-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP6-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH6_IN_SPLIT_DIR' TRN6-1 TVS6-1 # INPUT SEC TO ESD DIODE DIR NET 'CH6_IN_SPLIT_CMP' TRN6-3 TVS6-2 # INPUT SEC TO ESD DIODE CMP NET 'CH6_IN_SPLIT_DIR' TRN22-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH6_IN_SPLIT_CMP' TRN22-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN6-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH6_ADC_IN_DIR' TRN22-5 # TERM AND ADC IN DIR NET 'CH6_ADC_IN_DIR' R733-1 # TERM AND ADC IN DIR NET 'CH6_TERM_DIR' R733-2 # TERMINATOR DIR NET 'CH6_TERM_DIR' C735-1 # TERMINATOR DIR NET 'CH6_TERM_DIR' C736-2 # TERMINATOR DIR NET 'GROUND' C735-2 C736-1 # GROUND NET 'CH6_ADC_IN_CMP' TRN22-3 # TERM AND ADC IN CMP NET 'CH6_ADC_IN_CMP' R734-1 # TERM AND ADC IN CMP NET 'CH6_TERM_CMP' R734-2 # TERMINATOR CMP NET 'CH6_TERM_CMP' C737-1 # TERMINATOR CMP NET 'CH6_TERM_CMP' C738-2 # TERMINATOR CMP NET 'GROUND' C737-2 C738-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH6_BIAS_DIR' TRN22-2 # WINDING LOW NET 'CH6_BIAS_DIR' R732-2 # WINDING LOW TO RES NET 'CH6_BIAS_DIR' C733-2 # WINDING LOW TO CAP NET 'CH6_BIAS_DIR' C734-2 # WINDING LOW TO CAP NET 'GROUND' R732-1 # GROUND RES NET 'GROUND' C733-1 # GROUND CAP NET 'GROUND' C734-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH6_BIAS_CMP' TRN22-4 # WINDING LOW NET 'CH6_BIAS_CMP' C731-1 # WINDING LOW TO CAP NET 'CH6_BIAS_CMP' C732-1 # WINDING LOW TO CAP NET 'CH6_BIAS_CMP' R731-1 # WINDING LOW TO RES NET 'GROUND' C731-2 # GROUND CAP NET 'GROUND' C732-2 # GROUND CAP NET 'GROUND' R731-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #7/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH7_INPUT_DIR' TRN7-6 # COAX INPUT CENTER CONDUCTOR NET 'CH7_INPUT_CMP' TRN7-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH7_INPUT_CMP' JMP7-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP7-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH7_IN_SPLIT_DIR' TRN7-1 TVS7-1 # INPUT SEC TO ESD DIODE DIR NET 'CH7_IN_SPLIT_CMP' TRN7-3 TVS7-2 # INPUT SEC TO ESD DIODE CMP NET 'CH7_IN_SPLIT_DIR' TRN23-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH7_IN_SPLIT_CMP' TRN23-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN7-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH7_ADC_IN_DIR' TRN23-5 # TERM AND ADC IN DIR NET 'CH7_ADC_IN_DIR' R743-1 # TERM AND ADC IN DIR NET 'CH7_TERM_DIR' R743-2 # TERMINATOR DIR NET 'CH7_TERM_DIR' C745-1 # TERMINATOR DIR NET 'CH7_TERM_DIR' C746-2 # TERMINATOR DIR NET 'GROUND' C745-2 C746-1 # GROUND NET 'CH7_ADC_IN_CMP' TRN23-3 # TERM AND ADC IN CMP NET 'CH7_ADC_IN_CMP' R744-1 # TERM AND ADC IN CMP NET 'CH7_TERM_CMP' R744-2 # TERMINATOR CMP NET 'CH7_TERM_CMP' C747-1 # TERMINATOR CMP NET 'CH7_TERM_CMP' C748-2 # TERMINATOR CMP NET 'GROUND' C747-2 C748-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH7_BIAS_DIR' TRN23-2 # WINDING LOW NET 'CH7_BIAS_DIR' R742-2 # WINDING LOW TO RES NET 'CH7_BIAS_DIR' C743-2 # WINDING LOW TO CAP NET 'CH7_BIAS_DIR' C744-2 # WINDING LOW TO CAP NET 'GROUND' R742-1 # GROUND RES NET 'GROUND' C743-1 # GROUND CAP NET 'GROUND' C744-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH7_BIAS_CMP' TRN23-4 # WINDING LOW NET 'CH7_BIAS_CMP' C741-1 # WINDING LOW TO CAP NET 'CH7_BIAS_CMP' C742-1 # WINDING LOW TO CAP NET 'CH7_BIAS_CMP' R741-1 # WINDING LOW TO RES NET 'GROUND' C741-2 # GROUND CAP NET 'GROUND' C742-2 # GROUND CAP NET 'GROUND' R741-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #8/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH8_INPUT_DIR' TRN8-6 # COAX INPUT CENTER CONDUCTOR NET 'CH8_INPUT_CMP' TRN8-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH8_INPUT_CMP' JMP8-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP8-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH8_IN_SPLIT_DIR' TRN8-1 TVS8-1 # INPUT SEC TO ESD DIODE DIR NET 'CH8_IN_SPLIT_CMP' TRN8-3 TVS8-2 # INPUT SEC TO ESD DIODE CMP NET 'CH8_IN_SPLIT_DIR' TRN24-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH8_IN_SPLIT_CMP' TRN24-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN8-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH8_ADC_IN_DIR' TRN24-5 # TERM AND ADC IN DIR NET 'CH8_ADC_IN_DIR' R753-1 # TERM AND ADC IN DIR NET 'CH8_TERM_DIR' R753-2 # TERMINATOR DIR NET 'CH8_TERM_DIR' C755-1 # TERMINATOR DIR NET 'CH8_TERM_DIR' C756-2 # TERMINATOR DIR NET 'GROUND' C755-2 C756-1 # GROUND NET 'CH8_ADC_IN_CMP' TRN24-3 # TERM AND ADC IN CMP NET 'CH8_ADC_IN_CMP' R754-1 # TERM AND ADC IN CMP NET 'CH8_TERM_CMP' R754-2 # TERMINATOR CMP NET 'CH8_TERM_CMP' C757-1 # TERMINATOR CMP NET 'CH8_TERM_CMP' C758-2 # TERMINATOR CMP NET 'GROUND' C757-2 C758-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH8_BIAS_DIR' TRN24-2 # WINDING LOW NET 'CH8_BIAS_DIR' R752-2 # WINDING LOW TO RES NET 'CH8_BIAS_DIR' C753-2 # WINDING LOW TO CAP NET 'CH8_BIAS_DIR' C754-2 # WINDING LOW TO CAP NET 'GROUND' R752-1 # GROUND RES NET 'GROUND' C753-1 # GROUND CAP NET 'GROUND' C754-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH8_BIAS_CMP' TRN24-4 # WINDING LOW NET 'CH8_BIAS_CMP' C751-1 # WINDING LOW TO CAP NET 'CH8_BIAS_CMP' C752-1 # WINDING LOW TO CAP NET 'CH8_BIAS_CMP' R751-1 # WINDING LOW TO RES NET 'GROUND' C751-2 # GROUND CAP NET 'GROUND' C752-2 # GROUND CAP NET 'GROUND' R751-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #9/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH9_INPUT_DIR' TRN9-6 # COAX INPUT CENTER CONDUCTOR NET 'CH9_INPUT_CMP' TRN9-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH9_INPUT_CMP' JMP9-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP9-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH9_IN_SPLIT_DIR' TRN9-1 TVS9-1 # INPUT SEC TO ESD DIODE DIR NET 'CH9_IN_SPLIT_CMP' TRN9-3 TVS9-2 # INPUT SEC TO ESD DIODE CMP NET 'CH9_IN_SPLIT_DIR' TRN25-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH9_IN_SPLIT_CMP' TRN25-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN9-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH9_ADC_IN_DIR' TRN25-5 # TERM AND ADC IN DIR NET 'CH9_ADC_IN_DIR' R763-1 # TERM AND ADC IN DIR NET 'CH9_TERM_DIR' R763-2 # TERMINATOR DIR NET 'CH9_TERM_DIR' C765-1 # TERMINATOR DIR NET 'CH9_TERM_DIR' C766-2 # TERMINATOR DIR NET 'GROUND' C765-2 C766-1 # GROUND NET 'CH9_ADC_IN_CMP' TRN25-3 # TERM AND ADC IN CMP NET 'CH9_ADC_IN_CMP' R764-1 # TERM AND ADC IN CMP NET 'CH9_TERM_CMP' R764-2 # TERMINATOR CMP NET 'CH9_TERM_CMP' C767-1 # TERMINATOR CMP NET 'CH9_TERM_CMP' C768-2 # TERMINATOR CMP NET 'GROUND' C767-2 C768-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH9_BIAS_DIR' TRN25-2 # WINDING LOW NET 'CH9_BIAS_DIR' R762-2 # WINDING LOW TO RES NET 'CH9_BIAS_DIR' C763-2 # WINDING LOW TO CAP NET 'CH9_BIAS_DIR' C764-2 # WINDING LOW TO CAP NET 'GROUND' R762-1 # GROUND RES NET 'GROUND' C763-1 # GROUND CAP NET 'GROUND' C764-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH9_BIAS_CMP' TRN25-4 # WINDING LOW NET 'CH9_BIAS_CMP' C761-1 # WINDING LOW TO CAP NET 'CH9_BIAS_CMP' C762-1 # WINDING LOW TO CAP NET 'CH9_BIAS_CMP' R761-1 # WINDING LOW TO RES NET 'GROUND' C761-2 # GROUND CAP NET 'GROUND' C762-2 # GROUND CAP NET 'GROUND' R761-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #10/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH10_INPUT_DIR' TRN10-6 # COAX INPUT CENTER CONDUCTOR NET 'CH10_INPUT_CMP' TRN10-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH10_INPUT_CMP' JMP10-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP10-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH10_IN_SPLIT_DIR' TRN10-1 TVS10-1 # INPUT SEC TO ESD DIODE DIR NET 'CH10_IN_SPLIT_CMP' TRN10-3 TVS10-2 # INPUT SEC TO ESD DIODE CMP NET 'CH10_IN_SPLIT_DIR' TRN26-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH10_IN_SPLIT_CMP' TRN26-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN10-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH10_ADC_IN_DIR' TRN26-5 # TERM AND ADC IN DIR NET 'CH10_ADC_IN_DIR' R773-1 # TERM AND ADC IN DIR NET 'CH10_TERM_DIR' R773-2 # TERMINATOR DIR NET 'CH10_TERM_DIR' C775-1 # TERMINATOR DIR NET 'CH10_TERM_DIR' C776-2 # TERMINATOR DIR NET 'GROUND' C775-2 C776-1 # GROUND NET 'CH10_ADC_IN_CMP' TRN26-3 # TERM AND ADC IN CMP NET 'CH10_ADC_IN_CMP' R774-1 # TERM AND ADC IN CMP NET 'CH10_TERM_CMP' R774-2 # TERMINATOR CMP NET 'CH10_TERM_CMP' C777-1 # TERMINATOR CMP NET 'CH10_TERM_CMP' C778-2 # TERMINATOR CMP NET 'GROUND' C777-2 C778-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH10_BIAS_DIR' TRN26-2 # WINDING LOW NET 'CH10_BIAS_DIR' R772-2 # WINDING LOW TO RES NET 'CH10_BIAS_DIR' C773-2 # WINDING LOW TO CAP NET 'CH10_BIAS_DIR' C774-2 # WINDING LOW TO CAP NET 'GROUND' R772-1 # GROUND RES NET 'GROUND' C773-1 # GROUND CAP NET 'GROUND' C774-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH10_BIAS_CMP' TRN26-4 # WINDING LOW NET 'CH10_BIAS_CMP' C771-1 # WINDING LOW TO CAP NET 'CH10_BIAS_CMP' C772-1 # WINDING LOW TO CAP NET 'CH10_BIAS_CMP' R771-1 # WINDING LOW TO RES NET 'GROUND' C771-2 # GROUND CAP NET 'GROUND' C772-2 # GROUND CAP NET 'GROUND' R771-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #11/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH11_INPUT_DIR' TRN11-6 # COAX INPUT CENTER CONDUCTOR NET 'CH11_INPUT_CMP' TRN11-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH11_INPUT_CMP' JMP11-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP11-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH11_IN_SPLIT_DIR' TRN11-1 TVS11-1 # INPUT SEC TO ESD DIODE DIR NET 'CH11_IN_SPLIT_CMP' TRN11-3 TVS11-2 # INPUT SEC TO ESD DIODE CMP NET 'CH11_IN_SPLIT_DIR' TRN27-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH11_IN_SPLIT_CMP' TRN27-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN11-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH11_ADC_IN_DIR' TRN27-5 # TERM AND ADC IN DIR NET 'CH11_ADC_IN_DIR' R783-1 # TERM AND ADC IN DIR NET 'CH11_TERM_DIR' R783-2 # TERMINATOR DIR NET 'CH11_TERM_DIR' C785-1 # TERMINATOR DIR NET 'CH11_TERM_DIR' C786-2 # TERMINATOR DIR NET 'GROUND' C785-2 C786-1 # GROUND NET 'CH11_ADC_IN_CMP' TRN27-3 # TERM AND ADC IN CMP NET 'CH11_ADC_IN_CMP' R784-1 # TERM AND ADC IN CMP NET 'CH11_TERM_CMP' R784-2 # TERMINATOR CMP NET 'CH11_TERM_CMP' C787-1 # TERMINATOR CMP NET 'CH11_TERM_CMP' C788-2 # TERMINATOR CMP NET 'GROUND' C787-2 C788-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH11_BIAS_DIR' TRN27-2 # WINDING LOW NET 'CH11_BIAS_DIR' R782-2 # WINDING LOW TO RES NET 'CH11_BIAS_DIR' C783-2 # WINDING LOW TO CAP NET 'CH11_BIAS_DIR' C784-2 # WINDING LOW TO CAP NET 'GROUND' R782-1 # GROUND RES NET 'GROUND' C783-1 # GROUND CAP NET 'GROUND' C784-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH11_BIAS_CMP' TRN27-4 # WINDING LOW NET 'CH11_BIAS_CMP' C781-1 # WINDING LOW TO CAP NET 'CH11_BIAS_CMP' C782-1 # WINDING LOW TO CAP NET 'CH11_BIAS_CMP' R781-1 # WINDING LOW TO RES NET 'GROUND' C781-2 # GROUND CAP NET 'GROUND' C782-2 # GROUND CAP NET 'GROUND' R781-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #12/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH12_INPUT_DIR' TRN12-6 # COAX INPUT CENTER CONDUCTOR NET 'CH12_INPUT_CMP' TRN12-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH12_INPUT_CMP' JMP12-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP12-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH12_IN_SPLIT_DIR' TRN12-1 TVS12-1 # INPUT SEC TO ESD DIODE DIR NET 'CH12_IN_SPLIT_CMP' TRN12-3 TVS12-2 # INPUT SEC TO ESD DIODE CMP NET 'CH12_IN_SPLIT_DIR' TRN28-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH12_IN_SPLIT_CMP' TRN28-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN12-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH12_ADC_IN_DIR' TRN28-5 # TERM AND ADC IN DIR NET 'CH12_ADC_IN_DIR' R793-1 # TERM AND ADC IN DIR NET 'CH12_TERM_DIR' R793-2 # TERMINATOR DIR NET 'CH12_TERM_DIR' C795-1 # TERMINATOR DIR NET 'CH12_TERM_DIR' C796-2 # TERMINATOR DIR NET 'GROUND' C795-2 C796-1 # GROUND NET 'CH12_ADC_IN_CMP' TRN28-3 # TERM AND ADC IN CMP NET 'CH12_ADC_IN_CMP' R794-1 # TERM AND ADC IN CMP NET 'CH12_TERM_CMP' R794-2 # TERMINATOR CMP NET 'CH12_TERM_CMP' C797-1 # TERMINATOR CMP NET 'CH12_TERM_CMP' C798-2 # TERMINATOR CMP NET 'GROUND' C797-2 C798-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH12_BIAS_DIR' TRN28-2 # WINDING LOW NET 'CH12_BIAS_DIR' R792-2 # WINDING LOW TO RES NET 'CH12_BIAS_DIR' C793-2 # WINDING LOW TO CAP NET 'CH12_BIAS_DIR' C794-2 # WINDING LOW TO CAP NET 'GROUND' R792-1 # GROUND RES NET 'GROUND' C793-1 # GROUND CAP NET 'GROUND' C794-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH12_BIAS_CMP' TRN28-4 # WINDING LOW NET 'CH12_BIAS_CMP' C791-1 # WINDING LOW TO CAP NET 'CH12_BIAS_CMP' C792-1 # WINDING LOW TO CAP NET 'CH12_BIAS_CMP' R791-1 # WINDING LOW TO RES NET 'GROUND' C791-2 # GROUND CAP NET 'GROUND' C792-2 # GROUND CAP NET 'GROUND' R791-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #13/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH13_INPUT_DIR' TRN13-6 # COAX INPUT CENTER CONDUCTOR NET 'CH13_INPUT_CMP' TRN13-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH13_INPUT_CMP' JMP13-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP13-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH13_IN_SPLIT_DIR' TRN13-1 TVS13-1 # INPUT SEC TO ESD DIODE DIR NET 'CH13_IN_SPLIT_CMP' TRN13-3 TVS13-2 # INPUT SEC TO ESD DIODE CMP NET 'CH13_IN_SPLIT_DIR' TRN29-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH13_IN_SPLIT_CMP' TRN29-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN13-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH13_ADC_IN_DIR' TRN29-5 # TERM AND ADC IN DIR NET 'CH13_ADC_IN_DIR' R803-1 # TERM AND ADC IN DIR NET 'CH13_TERM_DIR' R803-2 # TERMINATOR DIR NET 'CH13_TERM_DIR' C805-1 # TERMINATOR DIR NET 'CH13_TERM_DIR' C806-2 # TERMINATOR DIR NET 'GROUND' C805-2 C806-1 # GROUND NET 'CH13_ADC_IN_CMP' TRN29-3 # TERM AND ADC IN CMP NET 'CH13_ADC_IN_CMP' R804-1 # TERM AND ADC IN CMP NET 'CH13_TERM_CMP' R804-2 # TERMINATOR CMP NET 'CH13_TERM_CMP' C807-1 # TERMINATOR CMP NET 'CH13_TERM_CMP' C808-2 # TERMINATOR CMP NET 'GROUND' C807-2 C808-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH13_BIAS_DIR' TRN29-2 # WINDING LOW NET 'CH13_BIAS_DIR' R802-2 # WINDING LOW TO RES NET 'CH13_BIAS_DIR' C803-2 # WINDING LOW TO CAP NET 'CH13_BIAS_DIR' C804-2 # WINDING LOW TO CAP NET 'GROUND' R802-1 # GROUND RES NET 'GROUND' C803-1 # GROUND CAP NET 'GROUND' C804-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH13_BIAS_CMP' TRN29-4 # WINDING LOW NET 'CH13_BIAS_CMP' C801-1 # WINDING LOW TO CAP NET 'CH13_BIAS_CMP' C802-1 # WINDING LOW TO CAP NET 'CH13_BIAS_CMP' R801-1 # WINDING LOW TO RES NET 'GROUND' C801-2 # GROUND CAP NET 'GROUND' C802-2 # GROUND CAP NET 'GROUND' R801-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #14/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH14_INPUT_DIR' TRN14-6 # COAX INPUT CENTER CONDUCTOR NET 'CH14_INPUT_CMP' TRN14-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH14_INPUT_CMP' JMP14-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP14-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH14_IN_SPLIT_DIR' TRN14-1 TVS14-1 # INPUT SEC TO ESD DIODE DIR NET 'CH14_IN_SPLIT_CMP' TRN14-3 TVS14-2 # INPUT SEC TO ESD DIODE CMP NET 'CH14_IN_SPLIT_DIR' TRN30-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH14_IN_SPLIT_CMP' TRN30-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN14-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH14_ADC_IN_DIR' TRN30-5 # TERM AND ADC IN DIR NET 'CH14_ADC_IN_DIR' R813-1 # TERM AND ADC IN DIR NET 'CH14_TERM_DIR' R813-2 # TERMINATOR DIR NET 'CH14_TERM_DIR' C815-1 # TERMINATOR DIR NET 'CH14_TERM_DIR' C816-2 # TERMINATOR DIR NET 'GROUND' C815-2 C816-1 # GROUND NET 'CH14_ADC_IN_CMP' TRN30-3 # TERM AND ADC IN CMP NET 'CH14_ADC_IN_CMP' R814-1 # TERM AND ADC IN CMP NET 'CH14_TERM_CMP' R814-2 # TERMINATOR CMP NET 'CH14_TERM_CMP' C817-1 # TERMINATOR CMP NET 'CH14_TERM_CMP' C818-2 # TERMINATOR CMP NET 'GROUND' C817-2 C818-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH14_BIAS_DIR' TRN30-2 # WINDING LOW NET 'CH14_BIAS_DIR' R812-2 # WINDING LOW TO RES NET 'CH14_BIAS_DIR' C813-2 # WINDING LOW TO CAP NET 'CH14_BIAS_DIR' C814-2 # WINDING LOW TO CAP NET 'GROUND' R812-1 # GROUND RES NET 'GROUND' C813-1 # GROUND CAP NET 'GROUND' C814-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH14_BIAS_CMP' TRN30-4 # WINDING LOW NET 'CH14_BIAS_CMP' C811-1 # WINDING LOW TO CAP NET 'CH14_BIAS_CMP' C812-1 # WINDING LOW TO CAP NET 'CH14_BIAS_CMP' R811-1 # WINDING LOW TO RES NET 'GROUND' C811-2 # GROUND CAP NET 'GROUND' C812-2 # GROUND CAP NET 'GROUND' R811-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #15/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH15_INPUT_DIR' TRN15-6 # COAX INPUT CENTER CONDUCTOR NET 'CH15_INPUT_CMP' TRN15-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH15_INPUT_CMP' JMP15-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP15-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH15_IN_SPLIT_DIR' TRN15-1 TVS15-1 # INPUT SEC TO ESD DIODE DIR NET 'CH15_IN_SPLIT_CMP' TRN15-3 TVS15-2 # INPUT SEC TO ESD DIODE CMP NET 'CH15_IN_SPLIT_DIR' TRN31-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH15_IN_SPLIT_CMP' TRN31-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN15-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH15_ADC_IN_DIR' TRN31-5 # TERM AND ADC IN DIR NET 'CH15_ADC_IN_DIR' R823-1 # TERM AND ADC IN DIR NET 'CH15_TERM_DIR' R823-2 # TERMINATOR DIR NET 'CH15_TERM_DIR' C825-1 # TERMINATOR DIR NET 'CH15_TERM_DIR' C826-2 # TERMINATOR DIR NET 'GROUND' C825-2 C826-1 # GROUND NET 'CH15_ADC_IN_CMP' TRN31-3 # TERM AND ADC IN CMP NET 'CH15_ADC_IN_CMP' R824-1 # TERM AND ADC IN CMP NET 'CH15_TERM_CMP' R824-2 # TERMINATOR CMP NET 'CH15_TERM_CMP' C827-1 # TERMINATOR CMP NET 'CH15_TERM_CMP' C828-2 # TERMINATOR CMP NET 'GROUND' C827-2 C828-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH15_BIAS_DIR' TRN31-2 # WINDING LOW NET 'CH15_BIAS_DIR' R822-2 # WINDING LOW TO RES NET 'CH15_BIAS_DIR' C823-2 # WINDING LOW TO CAP NET 'CH15_BIAS_DIR' C824-2 # WINDING LOW TO CAP NET 'GROUND' R822-1 # GROUND RES NET 'GROUND' C823-1 # GROUND CAP NET 'GROUND' C824-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH15_BIAS_CMP' TRN31-4 # WINDING LOW NET 'CH15_BIAS_CMP' C821-1 # WINDING LOW TO CAP NET 'CH15_BIAS_CMP' C822-1 # WINDING LOW TO CAP NET 'CH15_BIAS_CMP' R821-1 # WINDING LOW TO RES NET 'GROUND' C821-2 # GROUND CAP NET 'GROUND' C822-2 # GROUND CAP NET 'GROUND' R821-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # MIGT>---------------------------------------------- # MIGT> V1.0 -- SUN JAN 12 14:40:39 2020 # MIGT> BEGIN SUBSTITUTING FROM -- INSTANCE #16/16 # MIGT>---------------------------------------------- # # DISCO-KRAKEN MODULE # # PMT ANALOG INPUT NET LIST TEMPLATE FILE # --------------------========--========-------- # # # ORIGINAL REV. 21-FEB-2023 # MOST RECENT REV. 14-NOV-2023 # # # THIS FILE INCLUDES THE TRANSFORMER AND DC BIAS COMPONENTS # FOR THE PMT SIGNAL ANALOG INPUT COMPONENTS IN A CHANNEL PAIR. # # NET LIST # # INPUT CONNECTOR TO INPUT TRANSFORMER PRIMARY NET 'CH16_INPUT_DIR' TRN16-6 # COAX INPUT CENTER CONDUCTOR NET 'CH16_INPUT_CMP' TRN16-4 # COAX INPUT SHIELD # ZERO OHM JUMPER TO CONNECT THE COAX INPUT SHIELD TO GROUND NET 'CH16_INPUT_CMP' JMP16-1 # COAX INPUT SHIELD TO JUMPER NET 'GROUND' JMP16-2 # GROUND # INPUT TRANSFORMER SECONDARY TO ESD DIODE THEN TO SPLIT TRANSFORMER PRIMARY NET 'CH16_IN_SPLIT_DIR' TRN16-1 TVS16-1 # INPUT SEC TO ESD DIODE DIR NET 'CH16_IN_SPLIT_CMP' TRN16-3 TVS16-2 # INPUT SEC TO ESD DIODE CMP NET 'CH16_IN_SPLIT_DIR' TRN32-1 # INPUT SEC TO SPLIT PRI DIR NET 'CH16_IN_SPLIT_CMP' TRN32-6 # INPUT SEC TO SPLIT PRI CMP NET 'GROUND' TRN16-2 # GROUND INPUT SEC CENTER TAP # SPLIT TRANSFORMER SECONDARY TO TERMINATOR AND TO ADC INPUT NET 'CH16_ADC_IN_DIR' TRN32-5 # TERM AND ADC IN DIR NET 'CH16_ADC_IN_DIR' R833-1 # TERM AND ADC IN DIR NET 'CH16_TERM_DIR' R833-2 # TERMINATOR DIR NET 'CH16_TERM_DIR' C835-1 # TERMINATOR DIR NET 'CH16_TERM_DIR' C836-2 # TERMINATOR DIR NET 'GROUND' C835-2 C836-1 # GROUND NET 'CH16_ADC_IN_CMP' TRN32-3 # TERM AND ADC IN CMP NET 'CH16_ADC_IN_CMP' R834-1 # TERM AND ADC IN CMP NET 'CH16_TERM_CMP' R834-2 # TERMINATOR CMP NET 'CH16_TERM_CMP' C837-1 # TERMINATOR CMP NET 'CH16_TERM_CMP' C838-2 # TERMINATOR CMP NET 'GROUND' C837-2 C838-1 # GROUND # SPLIT TRANSFORMER SECONDARY DIR WINDING BIAS AND AC GROUND NET 'CH16_BIAS_DIR' TRN32-2 # WINDING LOW NET 'CH16_BIAS_DIR' R832-2 # WINDING LOW TO RES NET 'CH16_BIAS_DIR' C833-2 # WINDING LOW TO CAP NET 'CH16_BIAS_DIR' C834-2 # WINDING LOW TO CAP NET 'GROUND' R832-1 # GROUND RES NET 'GROUND' C833-1 # GROUND CAP NET 'GROUND' C834-1 # GROUND CAP # SPLIT TRANSFORMER SECONDARY CMP WINDING BIAS AND AC GROUND NET 'CH16_BIAS_CMP' TRN32-4 # WINDING LOW NET 'CH16_BIAS_CMP' C831-1 # WINDING LOW TO CAP NET 'CH16_BIAS_CMP' C832-1 # WINDING LOW TO CAP NET 'CH16_BIAS_CMP' R831-1 # WINDING LOW TO RES NET 'GROUND' C831-2 # GROUND CAP NET 'GROUND' C832-2 # GROUND CAP NET 'GROUND' R831-2 # GROUND CAP AND RES # MIGT>---------------------------------------------- # MIGT> DONE SUBSTITUTING FROM # # PMT ADC NET LIST # ---------------------- # # # ORIGINAL REV. 19-FEB-2023 # CURRENT REV. 6-DEC-2023 # # # THIS NET LIST FILE ASSIGNS NET NAMES TO ALL 100 # OF THE AD9083 ADC PINS. # # # ANALOG SIGNAL INPUT PINS # -------------------------- # NET 'CH1_ADC_IN_DIR' U601-A5 NET 'CH1_ADC_IN_CMP' U601-B5 NET 'CH2_ADC_IN_DIR' U601-A6 NET 'CH2_ADC_IN_CMP' U601-B6 NET 'CH3_ADC_IN_DIR' U601-A7 NET 'CH3_ADC_IN_CMP' U601-B7 NET 'CH4_ADC_IN_DIR' U601-A8 NET 'CH4_ADC_IN_CMP' U601-B8 NET 'CH5_ADC_IN_DIR' U601-A9 NET 'CH5_ADC_IN_CMP' U601-B9 NET 'CH6_ADC_IN_DIR' U601-C10 NET 'CH6_ADC_IN_CMP' U601-C9 NET 'CH7_ADC_IN_DIR' U601-D10 NET 'CH7_ADC_IN_CMP' U601-D9 NET 'CH8_ADC_IN_DIR' U601-E10 NET 'CH8_ADC_IN_CMP' U601-E9 NET 'CH9_ADC_IN_DIR' U601-F10 NET 'CH9_ADC_IN_CMP' U601-F9 NET 'CH10_ADC_IN_DIR' U601-G10 NET 'CH10_ADC_IN_CMP' U601-G9 NET 'CH11_ADC_IN_DIR' U601-H10 NET 'CH11_ADC_IN_CMP' U601-H9 NET 'CH12_ADC_IN_DIR' U601-K9 NET 'CH12_ADC_IN_CMP' U601-J9 NET 'CH13_ADC_IN_DIR' U601-K8 NET 'CH13_ADC_IN_CMP' U601-J8 NET 'CH14_ADC_IN_DIR' U601-K7 NET 'CH14_ADC_IN_CMP' U601-J7 NET 'CH15_ADC_IN_DIR' U601-K6 NET 'CH15_ADC_IN_CMP' U601-J6 NET 'CH16_ADC_IN_DIR' U601-K5 NET 'CH16_ADC_IN_CMP' U601-J5 # # POWER SUPPLY PINS # ------------------- # # ANALOG 1V0 NET 'ADC_ANALOG_1V0' U601-D6 U601-E6 U601-E7 NET 'ADC_ANALOG_1V0' U601-F6 U601-F7 U601-G6 # ANALOG CLOCK 1V0 NET 'ADC_ANALOG_1V0' U601-F5 # ANALOG PLL 1V0 NET 'ADC_ANALOG_1V0' U601-J4 # ANALOG 1V8 NET 'ADC_ANALOG_1V8' U601-C8 U601-D8 U601-G8 NET 'ADC_ANALOG_1V8' U601-H6 U601-H8 # DIGITAL 1V0 NET 'ADC_DIGITAL_1V0' U601-D3 U601-E3 U601-F3 U601-G3 # DIGITAL DRIVER 1V0 NET 'ADC_DIGITAL_1V0' U601-B3 U601-C3 U601-H3 # DIGITAL DRIVER 1V8 NET 'ADC_DIGITAL_1V8' U601-B1 # DIGITAL SPI AND I/O 1V8 NET 'ADC_DIGITAL_1V8' U601-B2 # # GROUND PINS # ------------- # # ANALOG GROUND PINS 9X NET 'GROUND' U601-C6 U601-C7 U601-D7 U601-E8 U601-F8 NET 'GROUND' U601-G7 U601-H5 U601-H7 U601-K10 # ANALOG AVDD GROUND REFERENCE PINS 2X NET 'GROUND' U601-E5 U601-K4 # DIGITAL GROUND PINS 4X NET 'GROUND' U601-D4 U601-E4 U601-F4 U601-G4 # DIGITAL DRIVER GROUND PINS 4X NET 'GROUND' U601-A1 U601-C1 U601-C2 U601-H2 # # THE FOUR JESD204B ADC SERIAL DATA LINKS # NET 'ADC_SEROUT0_DIR' U601-D2 # FPGA XCVR_1_RX0_DIR NET 'ADC_SEROUT0_CMP' U601-D1 # FPGA XCVR_1_RX0_CMP NET 'ADC_SEROUT1_DIR' U601-E2 # FPGA XCVR_1_RX1_DIR NET 'ADC_SEROUT1_CMP' U601-E1 # FPGA XCVR_1_RX1_CMP NET 'ADC_SEROUT2_DIR' U601-F2 # FPGA XCVR_1_RX2_DIR NET 'ADC_SEROUT2_CMP' U601-F1 # FPGA XCVR_1_RX2_CMP NET 'ADC_SEROUT3_DIR' U601-G2 # FPGA XCVR_1_RX3_DIR NET 'ADC_SEROUT3_CMP' U601-G1 # FPGA XCVR_1_RX3_CMP # # FOUR CLOCK AND TIMING SIGNAL INPUTS # NET 'PMT_ADC_CLOCK_DIR' U601-K3 # ADC CONVERTER CLOCK DIR NET 'PMT_ADC_CLOCK_CMP' U601-J3 # ADC CONVERTER CLOCK CMP ##NET 'PMT_ADC_SYS_REF_DIR' U601-K2 # ADC SYSTEM REFERENCE DIR NET 'TG_OUTPUT_0B_DIR' U601-K2 # CONNECT SYSTEM REFERENCE DIR TO TIME GENERATOR ##NET 'PMT_ADC_SYS_REF_CMP' U601-J2 # ADC SYSTEM REFERENCE CMP NET 'TG_OUTPUT_0B_CMP' U601-J2 # CONNECT SYSTEM REFERENCE CMP TO TIME GENERATOR NET 'PMT_ADC_SYNC_ENB_B_DIR' U601-A2 # ADC JESD204B SYNC ENB B DIR NET 'PMT_ADC_SYNC_ENB_B_CMP' U601-A3 # ADC JESD204B SYNC ENB B CMP NET 'PMT_ADC_TRIGGER_DIR' U601-H1 # ADC TRIGGER DIR INPUT FLOAT IF NOT USED NET 'PMT_ADC_TRIGGER_CMP' U601-J1 # ADC TRIGGER CMP INPUT FLOAT IF NOT USED # # FIVE ADC DIGITAL CONTROLS MOSTLY INPUTS AND ONE I/O # ##NET 'ADC_POW_DWN_STBY' U601-C5 # ADC POWER DOWN - STANDBY ACTIVE HI NET 'GROUND' U601-C5 # GROUND THE ADC_POW_DWN_STBY SIGNAL NET 'PMT_ADC_RESET_B' U601-D5 # ADC RESET ACTIVE LOW NET 'PMT_ADC_CHIP_SELECT_B' U601-A4 # ADC SPI CHIP SELECT ACTIVE LOW NET 'PMT_ADC_SPI_CLOCK' U601-B4 # ADC SPI CLOCK NET 'PMT_ADC_SPI_DATA_IO' U601-C4 # ADC SPI DATA I/O # # SIX ADC STATIC CONTROL PINS # NET 'PMT_ADC_TEMP_DIODE' U601-B10 # ADC TEMPERATURE DIODE NET 'ADC_CURRENT_REFERENCE' U601-J10 # ADC CURRENT REFERENCE RESISTOR NET 'ADC_PLL_REG_BYPASS' U601-H4 # ADC PLL VCO VOLTAGE REGULATOR BYPASS CAP NET 'ADC_PLL_COARSE_FILTER' U601-G5 # ADC PLL COARSE FILTER CAPACITOR NET 'NO_CONN_U601_PIN_A10' U601-A10 # ADC DO NOT CONNECT PIN NET 'NO_CONN_U601_PIN_K1' U601-K1 # ADC DO NOT CONNECT PIN # # DIDSCO-KRAKEN PMT INPUT CONNECTOR3 NETS FILE # -----------------====================------------- # # # ORIGINAL REV. 14-FEB-2023 # MOST RECENT REV. 7-AUG-2023 # # PMT INPUT CONNECTORS PIN NETS # # NOW USING HARWIN M80-MH313M5-08 CONNECTORS. # # # PMT SIGNAL INPUT CONNECTOR J2 PMT CHANNELS 1:8 # NET 'CH1_INPUT_DIR' J2-1 # COAX INPUT CENTER CONDUCTOR NET 'CH1_INPUT_CMP' J2-9 J2-10 # COAX INPUT SHIELD NET 'CH2_INPUT_DIR' J2-2 # COAX INPUT CENTER CONDUCTOR NET 'CH2_INPUT_CMP' J2-11 J2-12 # COAX INPUT SHIELD NET 'CH3_INPUT_DIR' J2-3 # COAX INPUT CENTER CONDUCTOR NET 'CH3_INPUT_CMP' J2-13 J2-14 # COAX INPUT SHIELD NET 'CH4_INPUT_DIR' J2-4 # COAX INPUT CENTER CONDUCTOR NET 'CH4_INPUT_CMP' J2-15 J2-16 # COAX INPUT SHIELD NET 'CH5_INPUT_DIR' J2-5 # COAX INPUT CENTER CONDUCTOR NET 'CH5_INPUT_CMP' J2-17 J2-18 # COAX INPUT SHIELD NET 'CH6_INPUT_DIR' J2-6 # COAX INPUT CENTER CONDUCTOR NET 'CH6_INPUT_CMP' J2-19 J2-20 # COAX INPUT SHIELD NET 'CH7_INPUT_DIR' J2-7 # COAX INPUT CENTER CONDUCTOR NET 'CH7_INPUT_CMP' J2-21 J2-22 # COAX INPUT SHIELD NET 'CH8_INPUT_DIR' J2-8 # COAX INPUT CENTER CONDUCTOR NET 'CH8_INPUT_CMP' J2-23 J2-24 # COAX INPUT SHIELD # # PMT SIGNAL INPUT CONNECTOR J3 PMT CHANNELS 9:16 # NET 'CH9_INPUT_DIR' J3-1 # COAX INPUT CENTER CONDUCTOR NET 'CH9_INPUT_CMP' J3-9 J3-10 # COAX INPUT SHIELD NET 'CH10_INPUT_DIR' J3-2 # COAX INPUT CENTER CONDUCTOR NET 'CH10_INPUT_CMP' J3-11 J3-12 # COAX INPUT SHIELD NET 'CH11_INPUT_DIR' J3-3 # COAX INPUT CENTER CONDUCTOR NET 'CH11_INPUT_CMP' J3-13 J3-14 # COAX INPUT SHIELD NET 'CH12_INPUT_DIR' J3-4 # COAX INPUT CENTER CONDUCTOR NET 'CH12_INPUT_CMP' J3-15 J3-16 # COAX INPUT SHIELD NET 'CH13_INPUT_DIR' J3-5 # COAX INPUT CENTER CONDUCTOR NET 'CH13_INPUT_CMP' J3-17 J3-18 # COAX INPUT SHIELD NET 'CH14_INPUT_DIR' J3-6 # COAX INPUT CENTER CONDUCTOR NET 'CH14_INPUT_CMP' J3-19 J3-20 # COAX INPUT SHIELD NET 'CH15_INPUT_DIR' J3-7 # COAX INPUT CENTER CONDUCTOR NET 'CH15_INPUT_CMP' J3-21 J3-22 # COAX INPUT SHIELD NET 'CH16_INPUT_DIR' J3-8 # COAX INPUT CENTER CONDUCTOR NET 'CH16_INPUT_CMP' J3-23 J3-24 # COAX INPUT SHIELD # # FINALLY GROUND THE MOUNTING SCREWS ON BOTH J2 AND J3 # NET 'GROUND' J2-25 J2-26 # J2 MOUNTING SCREWS NET 'GROUND' J3-25 J3-26 # J3 MOUNTING SCREWS # # PMT ADC POWER FILTER & BYPASS CAPACITOR NET LIST # ---------------------------------------------------- # # # ORIGINAL REV. 22-FEB-2023 # CURRENT REV. 16-NOV-2023 # # # THIS NET LIST FILE COVERS THE ADC POWER FILTERS # AND THE ADC BYPASS CAPACITORS. # # # ADC_ANALOG_1V0 POWER FILTER & BYPASS CAPS AKA AVDD # NET 'BULK_1V00' L601-1 NET 'ADC_ANALOG_1V0' L601-2 NET 'ADC_ANALOG_1V0' C601-1 C602-1 C603-1 C604-1 C605-1 NET 'GROUND' C601-2 C602-2 C603-2 C604-2 C605-2 NET 'ADC_ANALOG_1V0' C606-1 C607-1 C608-1 C609-1 C610-1 NET 'GROUND' C606-2 C607-2 C608-2 C609-2 C610-2 NET 'ADC_ANALOG_1V0' C611-1 C612-1 C613-1 C614-1 C615-1 NET 'GROUND' C611-2 C612-2 C613-2 C614-2 C615-2 NET 'ADC_ANALOG_1V0' C616-1 C617-1 NET 'GROUND' C616-2 C617-2 # ADC_ANALOG_1V8 POWER FILTER & BYPASS CAPS AKA AVDD1P8V NET 'BULK_1V8' L602-2 NET 'ADC_ANALOG_1V8' L602-1 NET 'ADC_ANALOG_1V8' C618-1 C619-1 C620-1 C621-1 C622-1 NET 'GROUND' C618-2 C619-2 C620-2 C621-2 C622-2 NET 'ADC_ANALOG_1V8' C623-1 C624-1 C625-1 C626-1 C627-1 NET 'GROUND' C623-2 C624-2 C625-2 C626-2 C627-2 NET 'ADC_ANALOG_1V8' C628-1 C629-1 C630-1 C631-1 C632-1 NET 'GROUND' C628-2 C629-2 C630-2 C631-2 C632-2 NET 'ADC_ANALOG_1V8' C633-1 NET 'GROUND' C633-2 # ADC_DIGITAL_1V0 POWER FILTER & BYPASS CAPS AKA DVDD NET 'BULK_1V00' L603-1 NET 'ADC_DIGITAL_1V0' L603-2 NET 'ADC_DIGITAL_1V0' C634-1 C635-1 C636-1 C637-1 C638-1 NET 'GROUND' C634-2 C635-2 C636-2 C637-2 C638-2 NET 'ADC_DIGITAL_1V0' C639-1 C640-1 C641-1 C642-1 C643-1 NET 'GROUND' C639-2 C640-2 C641-2 C642-2 C643-2 NET 'ADC_DIGITAL_1V0' C644-1 C645-1 C646-1 C647-1 C648-1 NET 'GROUND' C644-2 C645-2 C646-2 C647-2 C648-2 NET 'ADC_DIGITAL_1V0' C649-1 C650-1 C651-1 C652-1 C653-1 NET 'GROUND' C649-2 C650-2 C651-2 C652-2 C653-2 NET 'ADC_DIGITAL_1V0' C654-1 C655-1 NET 'GROUND' C654-2 C655-2 # ADC_DIGITAL_1V8 POWER FILTER & BYPASS CAPS AKA DVDD1P8V NET 'BULK_1V8' L604-2 NET 'ADC_DIGITAL_1V8' L604-1 NET 'ADC_DIGITAL_1V8' C658-1 C659-1 C660-1 C661-1 C662-1 NET 'GROUND' C658-2 C659-2 C660-2 C661-2 C662-2 NET 'ADC_DIGITAL_1V8' C663-1 C664-1 C665-1 C666-1 C667-1 NET 'GROUND' C663-2 C664-2 C665-2 C666-2 C667-2 NET 'ADC_DIGITAL_1V8' C668-1 NET 'GROUND' C668-2 # # PMT ADC SUNDRY NET LIST # --------------------------- # # # ORIGINAL REV. 23-FEB-2023 # CURRENT REV. 6-DEC-2023 # # PMT ADC SUNDRY NETS # # # PMT ADC TEMPERATURE DIODE AND POWER DOWN / STANDBY # --------------------------------------------------------- # NET 'PMT_ADC_TEMP_DIODE' TP601-1 # TEMP DIODE SIGNAL TO SINGLE SMD PAD # THE HI ACTIVE PMT ADC POWER_DOWN/STANDBY PIN # IS GROUNDED IN THE NET LIST FILE FOR THE ADC ITSELF. # # SPI BUS CONNECTION BETWEEN FPGA/CPU AND PMT ADC 3-WIRE SPI # ----------------------------------------------------------------- # # LIST THE NETNAMES OF THE SIGNALS THAT MUST BE # CONNECTED TO FPGA FLOATING PINS. HERE JUST LIST # THE NETNAMES - THE ACTUAL CONNECTIONS TO THESE # FPGA FLOATING PINS ARE MADE IN THE NETS FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # ---------------------------------------------------- # # # ALL OF THESE ARE 1V8 SIGNALS: PMT ADC SPI BUS # -------------------------------------------------- # # NET 'PMT_ADC_CHIP_SELECT_B' # ADC SPI CHIP SELECT ACTIVE LOW # NET 'PMT_ADC_SPI_CLOCK' # ADC SPI CLOCK # NET 'PMT_ADC_SPI_DATA_IO' # ADC SPI DATA I/O # # # CLOCK TYPE SIGNALS THAT ARE SENT TO THE PMT ADC FROM TIMING GENERATOR & FPGA # ----------------------------------------------------------------------------------- # # # REVIEW OF THE CLOCK TYPE SIGNALS THAT ARE INPUTS TO THE AD9083 # # SEE PAGES: 10, 15, 25, 26 OF THE AD9083 DATASHEET # # CLOCK IS 100 OHM INTERNALLY TERMINATED, CLAMP IS 1 DIODE ABOVE AVDD, # ------- THE INPUT HAS A WEAK SELF DC BIASED OF 0.5 VOLTS, # THE INPUT SHOULD BE AC COUPLED, # THE INPUT AMPLITUDE SHOULD BE 800 TO 1800 MV PK-PK # # SYSTEM_REFERENCE IS 100 OHM INTERNALLY TERMINATED, CLAMP IS 1 DIODE ABOVE AVDD, # ---------------- THE INPUT HAS A WEAK SELF DC BIASED OF 0.5 VOLTS, # THE INPUT COMMON MODE SHOULD BE 0.5 V # THE INPUT AMPLITUDE SHOULD BE 700 TO 1100 MV PK-PK # AD SAYS THIS INPUT IS LVDS COMPATABLE # # TRIGGER IS 100 OHM INTERNALLY TERMINATED, CLAMP IS 1 DIODE ABOVE AVDD, # ------- THE INPUT HAS A WEAK SELF DC BIASED OF 0.5 VOLTS, # THE INPUT COMMON MODE SHOULD BE 0.5 V # THE INPUT AMPLITUDE SHOULD BE 700 TO 1100 MV PK-PK # AD SAYS THIS INPUT IS LVDS COMPATABLE # # SYNC_ENB_B IS 100K OHM INTERNALLY TERMINATED, CLAMP IS 2 DIODES ABOVE DVDD1P8, # ---------- THE INPUT COMMON MODE SHOULD BE 0.45 V # IN ITS THE INPUT AMPLITUDE SHOULD BE 700 TO 1900 MV PK-PK # DIFF MODE AD SAYS THIS INPUT IS LVDS COMPATABLE # # # CONCERNS: AD CALLS THE SYSTEM_REFERENCE AND TRIGGER INPUTS "LVDS" # BUT THEY ARE NOT NORMAL LVDS BECAUSE THEIR COMMON MODE IS # TOO LOW. CONCERN - ARE THE 3V3 LVDS OUTPUTS FROM THE FPGA/CPU # REALLY TRUE 3 MA CURRENT MODE OUTPUTS OR ARE THEY SOME # LVDS LIKE VOLLTAGE MODE THING THAT WILL OVER DRIVE THESE # AD9083 INPUTS ? E.G. SHOULD I USE SERIES RESISTORS ? # # SYNC_ENB_B NEEDS AN EXTERNAL 100 OHM TERMINATOR - R602. # # THE PMT ADC CLOCK SIGNAL IS AC COUPLED AND # COMES FROM THE TIMING GENERATOR OUTPUT 0-A NET 'PMT_ADC_CLOCK_DIR' C941-2 # ADC CONVERTER CLOCK DIR TIMING GENERATOR OUTPUT NET 'PMT_ADC_CLOCK_CMP' C942-2 # ADC CONVERTER CLOCK CMP 0-A AC COOUPLING CAPS # THE PMT ADC SYSTEM REFERENCE SIGNAL IS DC COUPLED # AND COMES FROM THE TIMING GENERATOR OUTPUT 0-B # # THIS CONNECTION IS MADE IN THE NET LIST FILE FOR THE ADC ITSELF. # # 'ADC SYSTEM REFERENCE DIR' U601-K2 # DC COUPLED SIGNAL FROM THE # 'ADC SYSTEM REFERENCE CMP' U601-J2 # TIMING GENERATOR OUTPUT 0-B # THE PMT ADC SYNC_ENB_B SIGNAL IS DC COUPLED # AND COMES FROM A LVDS OUTPUT ON THE FPGA/CPU. # # NOTE THAT SYNC_ENB_B NEEDS AN EXTERNAL 100 OHM TERMINATOR # WHEN THIS INPUT IS USED IN ITS LVDS MODE. THIS 100 OHM # TERMINATOR, R602, IS CONNECTED HERE. # # 'PMT_ADC_SYNC_ENB_B_DIR' U601-A2 # ADC JESD204B SYNC ENB B DIR # 'PMT_ADC_SYNC_ENB_B_CMP' U601-A3 # ADC JESD204B SYNC ENB B CMP # NET 'PMT_ADC_SYNC_ENB_B_DIR' R602-1 # TERMINATOR ON SYNC_ENB_B NET 'PMT_ADC_SYNC_ENB_B_CMP' R602-2 # TERMINATOR ON SYNC_ENB_B # THE PMT ADC TRIGGER SIGNAL IS DC COUPLED AND # COMES FROM A LVDS OUTPUT ON THE FPGA/CPU. # # 'PMT_ADC_TRIGGER_DIR' U601-H1 # ADC TRIGGER DIR INPUT # 'PMT_ADC_TRIGGER_CMP' U601-J1 # ADC TRIGGER CMP INPUT # # CLOCK TYPE SIGNALS FROM THE FPGA/CPU TO THE PMT ADC # ----------------------------------------------------------- # # LIST THE NETNAMES OF THE SIGNALS THAT MUST BE # CONNECTED TO FPGA FLOATING PINS. HERE JUST LIST # THE NETNAMES - THE ACTUAL CONNECTIONS TO THESE # FPGA FLOATING PINS ARE MADE IN THE NETS FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # ---------------------------------------------------- # # # ALL OF THESE ARE LVDS SIGNALS: PMT ADC CLOCK TYPE SIGNALS # -------------------------------------------------------------- # # NET 'PMT_ADC_SYNC_ENB_B_DIR' # ADC JESD204B SYNC ENB B DIR # NET 'PMT_ADC_SYNC_ENB_B_CMP' # ADC JESD204B SYNC ENB B CMP # # NET 'PMT_ADC_TRIGGER_DIR' # ADC TRIGGER DIR INPUT # NET 'PMT_ADC_TRIGGER_CMP' # ADC TRIGGER CMP INPUT # # # END OF THIS BIG SECTION ABOUT CLOCK TYPE SIGNALS # ----------------------------------------------------- # # # CLOCK MULTIPLIER PLL VOLTAGE REGULATOR BYPASS CAPACITORS # NET 'ADC_PLL_REG_BYPASS' C689-1 C699-1 # CLOCK MULTIPLIER PLL NET 'GROUND' C689-2 C699-2 # VOLTAGE REGULATOR # BYPASS CAPACITORS # # CLOCK MULTIPLIER PLL COARSE TUNING LOOP FILTER CAPACITOR # NET 'ADC_PLL_COARSE_FILTER' C709-1 # CLOCK MULTIPLIER PLL NET 'GROUND' C709-2 # COARSE TUNING LOOP # FILTER CAPACITOR # # CURRENT REFERENCE RESISTOR # NET 'ADC_CURRENT_REFERENCE' R601-1 # ADC CURRENT REFERENCE NET 'GROUND' R601-2 # RESISTOR # # ENVIRONMENT SENSORS NET LIST # ------------------------------------ # # # INITIAL REV. 15-NOV-2022 # CURRENT REV. 12-JAN-2024 # # # THIS NET LIST HOLDS THE ENVIRONMENT SENSORS # NET LIST. # # # THE COMPONENTS FOR THE ENVIRONMENT SENSORS # ARE IN THE RANGE 851 TO 856. # # # POWER AND GROUND TO THE 2X ENVIRONMENT SENSORS # NET 'BULK_1V8' L851-2 # BULK POWER INTO FILTER NET 'SENSOR_1V8' L851-1 # FILTERED SENSOR POWER NET 'SENSOR_1V8' C851-1 C852-2 C853-2 # FILTER CAPS ON TPH SENSOR NET 'GROUND' C851-2 C852-1 C853-1 # GROUND SIDE OF FILTER CAPS NET 'SENSOR_1V8' U851-2 U851-6 U851-8 # FILTERED POWER TO TPH SENSOR NET 'GROUND' U851-1 U851-7 # GROUNDS TO TPH SENSOR NET 'SENSOR_1V8' C854-2 C855-1 C856-1 # FILTER CAPS ON ACCEL-MAG SENSOR NET 'GROUND' C854-1 C855-2 C856-2 # GROUND SIDE OF FILTER CAPS NET 'SENSOR_1V8' U852-2 U852-9 U852-10 # FILTERED POWER TO ACCEL-MAG SENSOR NET 'GROUND' U852-3 U852-6 U852-8 # GROUNDS TO ACCEL-MAG SENSOR # # CAP ON THE ACCELERATION - MAGNETIC FIELD SENSOR # NET 'ACC_SENSOR_CAP' U852-5 C857-1 NET 'GROUND' C857-2 # # GROUND JUMPER ON THE TPH SENSOR'S SDO PIN #5 # NET 'JMP_SENSOR' U851-5 JMP851-2 NET 'GROUND' JMP851-1 # # I2C BUS AND PULL-UP RESISTORS FOR # THE 2X SENSORS AND THE BB AUDIO ADC # NET 'I2C_DATA_SENSOR_BB_ADC' U851-3 U852-4 R851-1 # SENSOR & BB ADC I2C BUS DATA NET 'I2C_SCLK_SENSOR_BB_ADC' U851-4 U852-1 R852-1 # SENSOR & BB ADC I2C BUS CLOCK NET 'SENSOR_1V8' R851-2 R852-2 # # NO CONNECT PINS ON THE ACCELERATION - MAGNETIC FIELD SENSOR # NET 'NO_CONN_ACC_SENSOR_7' U852-7 NET 'NO_CONN_ACC_SENSOR_11' U852-11 NET 'NO_CONN_ACC_SENSOR_12' U852-12 # # LIST THE NETNAMES OF THE SIGNALS THAT MUST BE # CONNECTED TO FPGA FLOATING PINS. HERE JUST LIST # THE NETNAMES - THE ACTUAL CONNECTIONS TO THESE # FPGA FLOATING PINS ARE MADE IN THE NETS FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # ---------------------------------------------------- # # # ALL OF THESE ARE 1V8 SIGNALS: SENSOR & BB AUDIO ADC I2C BUS # --------------------------------------------------------------------- # # # NET 'I2C_DATA_SENSOR_BB_ADC' # SENSOR & BB ADC I2C BUS DATA # # NET 'I2C_SCLK_SENSOR_BB_ADC' # SENSOR & BB ADC I2C BUS CLOCK # # # # TIMING GENERATOR NET LIST # --------------------------------- # # # INITIAL REV. 15-NOV-2022 # CURRENT REV. 12-JAN-2024 # # # THIS NET LIST HOLDS THE TIMING GENERATOR # NET LIST. # # # THE COMPONENTS FOR THE TIMING GENERATOR # ARE IN THE RANGE 901 TO 949. # # # TIMING GENERATOR: MAIN TIMING INPUTS: # ------------------------------------------ # # REFERENCE INPUT "A" DIFFERENTIAL IS # DK DESIGN PIN NAMES: TG_REF_IN_A_DIR AND TG_REF_IN_A_CMP # # TIMING GENERATOR REFERENCE INPUT A IS DRIVEN BY THE # OUTPUT OF THE TIMING SFP RECEIVER IN SFP CONNECTOR J13. # # AN EXTERNAL 100 OHM TERMINATOR IS REQUIRED # AT THIS TIMING GENERATOR INPUT (R921) AND THIS # TIMING GENERATOR INPUT MUST BE SET FOR AC COUPLED # SO THAT IT SUPPLIES ITS OWN COMMON MODE VOLTAGE. # NO EXTERNAL AC COUPLING CAPACITORS ARE USED. NET 'SFP_TIME_RD_DIR' R921-1 U901-47 # INPUT TG_REF_IN_A_DIR NET 'SFP_TIME_RD_CMP' R921-2 U901-46 # INPUT TG_REF_IN_A_CMP NET 'TG_REF_IN_B_DIR' U901-38 R925-1 # UNUSED REFB INPUT - TIE IT OFF NET 'TG_REF_IN_B_CMP' U901-39 R926-1 # UNUSED REFBB INPUT - TIE IT OFF # # THE TIMING GENERATOR REFERENCE INPUT B IS NOT USED. # TIE IT OFF SO THAT THIS DIFFERENTIAL INPUT IS A VALID LOW. # NET 'TIME_GEN_1V8' R925-2 # 1V8 SOURCE FOR THE TIE OFF PULL-UP NET 'GROUND' R926-2 # GROUND ANCHOR ON THE TIE OFF PULL-DOWN # # TIMING GENERATOR: AUXILIARY INPUTS: # ---------------------------------------- # # THE VDDIOA AND VDDIOB POWER FEEDS TO THE AD9546 TIMING GENERATOR # ARE 3V3 SO THESE SINGLE ENDED INPUTS ARE 3V3 CMOS LOGIC LEVEL. # # M0 IS NOT USED AND IS TIED OFF LOW # M1 IS FOR TIMING THE FPGA "FLASH NOW" SIGNAL # M2 IS FOR TIMING THE "FLASH SEEN" SIGNAL FROM INTERPOSER #1 # M3 IS FOR TIMING THE "FLASH SEEN" SIGNAL FROM INTERPOSER #2 NET 'TG_AUX_IN_M0' U901-32 R924-1 # TIE OFF PULL-DOWN CONNECTION TO M0 NET 'TG_AUX_IN_M1' U901-33 NET 'TG_AUX_IN_M2' U901-35 NET 'TG_AUX_IN_M3' U901-36 NET 'GROUND' R924-2 # GROUND ANCHOR ON THE TIE OFF PULL-DOWN # # TIMING GENERATOR: CRYSTAL OSCILLATOR: # -------------------------------------- # NET 'TG_CRYSTAL_XOA' U901-42 Y901-1 C951-1 # TG XOA PIN NET 'TG_CRYSTAL_XOB' U901-43 Y901-3 C952-1 # TG XOA PIN NET 'GROUND' Y901-2 Y901-4 # GROUND XTAL PKG PINS NET 'GROUND' C951-2 C952-2 # GROUND TUNING CAPS # # TIMING GENERATOR: I2C CONTROL BUS AND PULL-UPS: # ------------------------------------------------------ # # THE I2C BUS FOR THE TIMING GENERATOR COMES FROM # THE FPGA/CPU I2C CONTROLLER #0 FAN-OUT (U1601) # AND IT IS CHANNEL #0 ON THIS I2C FAN-OUT CHIP. # NET 'TG_I2C_SCLK' U901-2 R922-1 # SCLK WITH I2C CONTROLLER #0 FAN-OUT CH #0 NET 'TG_I2C_SDATA' U901-4 R923-1 # SDATA WITH I2C CONTROLLER #0 FAN-OUT CH #0 NET 'BULK_3V3' R922-2 R923-2 # PULL-UP 3V3 SOURCE # # TIMING GENERATOR: RESET PIN # ---------------------------- NET 'CLOCK_GEN_RESET_B' U901-48 # # TIMING GENERATOR: DO NOT CONNECT PINS: # --------------------------------------- NET 'NO_CONN_TG_DNC_16' U901-16 NET 'NO_CONN_TG_DNC_21' U901-21 NET 'NO_CONN_TG_DNC_44' U901-44 # # TIMING GENERATOR: OUTPUTS, PULL-UP RS, AND AC COUPLING CS: # -------------------------------------------------------------- # NET 'TG_OUTPUT_0A_DIR' U901-11 R911-1 C941-1 # OUTPUT 0A DIR NET 'TG_OUTPUT_0A_CMP' U901-12 R912-1 C942-1 # OUTPUT 0A CMP NET 'TG_OUTPUT_0B_DIR' U901-14 R913-1 # OUTPUT 0B DIR NET 'TG_OUTPUT_0B_CMP' U901-15 R914-1 # OUTPUT 0B CMP # TIMING GENERATOR OUTPUT 0-C IS CONNECTED TO THE # TIMING SFP TRANSMITTER. THIS IS THE RETURN SIGNAL # TO THE SOURCE OF TIMING FOR THE AD9546 TIMING GENERATOR. # NO EXTERNAL AC COUPLING CAPACITORS ARE USED, NO C945, C946. NET 'SFP_TIME_TD_DIR' U901-17 R915-1 # OUTPUT 0C DIR TG_OUTPUT_0C_DIR NET 'SFP_TIME_TD_CMP' U901-18 R916-1 # OUTPUT 0C CMP TG_OUTPUT_0C_CMP NET 'TG_OUTPUT_1A_DIR' U901-25 R917-1 C947-1 # OUTPUT 1A DIR NET 'TG_OUTPUT_1A_CMP' U901-26 R918-1 C948-1 # OUTPUT 1A CMP NET 'TG_OUTPUT_1B_DIR' U901-22 R919-1 C949-1 # OUTPUT 1B DIR NET 'TG_OUTPUT_1B_CMP' U901-23 R920-1 C950-1 # OUTPUT 1B CMP # # CONNECT THE TIMING GENERATOR OUTPUTS 1A AND 1B TO: AC COUPLED # # TIME GEN OUTPUT 1A TO XCVR_1A_REF_CLK_IN L23, L24 JESD CLOCK # # TIME GEN OUTPUT 1B TO CCC_SE_CLK_IN_S_9 J14, H14 A SPARE CLK # GPIO11PB1/CLKIN_S_9 BANK #1 # NET 'XCVR_1A_REF_CLK_IN_DIR' C947-2 U1-L23 # XCVR_1A_REF_CLK_IN_DIR JESD CLOCK NET 'XCVR_1A_REF_CLK_IN_CMP' C948-2 U1-L24 # XCVR_1A_REF_CLK_IN_CMP JESD CLOCK NET 'FPGA_CCC_SE_CLK_IN_S_9_DIR' C949-2 U1-J14 # SPARE CLOCK TIME GEN TO FPGA DIR NET 'FPGA_CCC_SE_CLK_IN_S_9_CMP' C950-2 U1-H14 # SPARE CLOCK TIME GEN TO FPGA CMP NET 'TIME_GEN_1V8' R911-2 R912-2 # CONNECT THE NET 'TIME_GEN_1V8' R913-2 R914-2 # OUTPUT PULL-UP NET 'TIME_GEN_1V8' R915-2 R916-2 # RESISTORS TO THE NET 'TIME_GEN_1V8' R917-2 R918-2 # TIMING_GENERATOR NET 'TIME_GEN_1V8' R919-2 R920-2 # 1V8 POWER RAIL # # RS AND CS FOR: SETUP, INTERNAL SUPPLIES, AND LOOP FILTERS: # ---------------------------------------------------------- # NET 'TIME_GEN_M4_PULL_UP' R901-1 U901-37 # PULL-UP THE M4 PIN NET 'TIME_GEN_M5_PULL_DN' R902-1 U901-1 # PULL-DOWN THE M5 PIN NET 'TIME_GEN_M6_PULL_DN' R903-1 U901-5 # PULL-DOWN THE M6 PIN NET 'TIME_GEN_3V3' R901-2 # PULL-UO 3V3 POWER NET 'GROUND' R902-2 R903-2 # PULL-DOWN GROUND NET 'TIME_GEN_LF_0' C932-1 U901-8 # 3.9 NFD CAP TO LF_0 NET 'TIME_GEN_LDO_0' C931-1 C932-2 U901-7 # BOTH CAPS TO LDO_0 NET 'GROUND' C931-2 # 220 NFD CAP TO GROUND NET 'TIME_GEN_LF_1' C934-1 U901-29 # 3.9 NFD CAP TO LF_1 NET 'TIME_GEN_LDO_1' C933-1 C934-2 U901-30 # BOTH CAPS TO LDO_1 NET 'GROUND' C933-2 # 220 NFD CAP TO GROUND # # 1.8 VOLT POWER TO THE AD9546: # NET 'BULK_1V8' L901-2 # BULK_1V8 POWER TO FILTER NET 'TIME_GEN_1V8' L901-1 # FILTERED TIMING GEN 1V8 POWER NET 'TIME_GEN_1V8' C901-1 C902-1 C903-1 C904-1 # 1V8 BYPASS CAPS NET 'GROUND' C901-2 C902-2 C903-2 C904-2 # GROUND SIDE OF FILTER CAPS NET 'TIME_GEN_1V8' C905-1 C906-1 C907-1 C908-1 # 1V8 BYPASS CAPS NET 'GROUND' C905-2 C906-2 C907-2 C908-2 # GROUND SIDE OF FILTER CAPS NET 'TIME_GEN_1V8' C909-1 C910-1 C911-1 C912-1 # 1V8 BYPASS CAPS NET 'GROUND' C909-2 C910-2 C911-2 C912-2 # GROUND SIDE OF FILTER CAPS NET 'TIME_GEN_1V8' C913-1 C914-1 C915-1 C916-1 # 1V8 BYPASS CAPS NET 'GROUND' C913-2 C914-2 C915-2 C916-2 # GROUND SIDE OF FILTER CAPS NET 'TIME_GEN_1V8' U901-6 U901-9 U901-20 U901-28 # 1V8 TO THE TIMING GENERATOR NET 'TIME_GEN_1V8' U901-31 U901-40 U901-41 U901-45 # 1V8 TO THE TIMING GENERATOR # # 1.8 VOLT POWER TO THE AD9546'S DIFFERENTIAL OUTPUT DRIVERS: # NET 'TIME_GEN_1V8' L903-1 L904-1 L905-1 # 1V8 POWER TO DIFF OUTPUT INDUCTORS NET 'TIME_GEN_1V8' L906-1 L907-1 # 1V8 POWER TO DIFF OUTPUT INDUCTORS NET 'DIFF_OUT_0A_POWER' L903-2 U901-10 # 1V8 POWER TO DIFF OUTPUT 0A NET 'DIFF_OUT_0B_POWER' L904-2 U901-13 # 1V8 POWER TO DIFF OUTPUT 0B NET 'DIFF_OUT_0C_POWER' L905-2 U901-19 # 1V8 POWER TO DIFF OUTPUT 0C NET 'DIFF_OUT_1A_POWER' L906-2 U901-27 # 1V8 POWER TO DIFF OUTPUT 1A NET 'DIFF_OUT_1B_POWER' L907-2 U901-24 # 1V8 POWER TO DIFF OUTPUT 1B # # 3.3 VOLT POWER TO THE AD9546: # NET 'BULK_3V3' L902-2 # BULK_3V3 POWER TO FILTER NET 'TIME_GEN_3V3' L902-1 # FILTERED TIMING GEN 1V8 POWER NET 'TIME_GEN_3V3' C921-1 C922-1 C923-1 C924-1 # 3V3 BYPASS CAPS NET 'GROUND' C921-2 C922-2 C923-2 C924-2 # GROUND SIDE OF FILTER CAPS NET 'TIME_GEN_3V3' C925-1 # 3V3 BYPASS CAPS NET 'GROUND' C925-2 # GROUND SIDE OF FILTER CAPS NET 'TIME_GEN_3V3' U901-3 U901-34 # 3V3 TO THE TIMING GENERATOR # # GROUNDS TO THE AD9546'S THERMAL PAD 25 GROUND CONNECTIONS: # NET 'GROUND' U901-51 U901-52 U901-53 U901-54 # GROUNDS TO THE AD9546 NET 'GROUND' U901-55 U901-56 U901-57 U901-58 # GROUNDS TO THE AD9546 NET 'GROUND' U901-59 U901-60 U901-61 U901-62 # GROUNDS TO THE AD9546 NET 'GROUND' U901-63 U901-64 U901-65 U901-66 # GROUNDS TO THE AD9546 NET 'GROUND' U901-67 U901-68 U901-69 U901-70 # GROUNDS TO THE AD9546 NET 'GROUND' U901-71 U901-72 U901-73 U901-74 # GROUNDS TO THE AD9546 NET 'GROUND' U901-75 # GROUNDS TO THE AD9546 # # EMERGENCY RESCUE UPROCESSOR & RS-485 TRANSCEIVER # --------------------------------------------------- # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # INITIAL REV. 20-NOV-2022 # CURRENT REV. 22-DEC-2023 # # # THIS NET LIST HOLDS THE RESCUE UPROC & RS-485 TRANSCEIVER # NET LIST. # # # THE COMPONENTS FOR THE RESCUE UPROC & RS-485 TRANSCEIVER # ARE IN THE RANGE 1001 TO 1049. # # # NOTE: THESE EMERGENCY RESCUE FUNCTIONS USE 1 SECTION # OF THE U1551 HEX INVERTER THAT IS OFFICIALLY # PART OF THE BARNACLE INTERFACE CIRCUIT. # # # CONNECT THE RS-485 TRANSCEIVER TO THE DOWN MAIN CABLE: # -------------------------------------------------------- # NET 'RS485_DOWN_DIR' U1002-6 # TRANSCEIVER DIR TO DOWN CABLE NET 'RS485_DOWN_CMP' U1002-7 # TRANSCEIVER CMP TO DOWN CABLE # # JUMPERS TO CONNECT THE RS-485 UP & DOWN MAIN CABLES: # -------------------------------------------------------- # NET 'RS485_DOWN_DIR' JMP1001-1 # JUMPER TO CONNECT UP & DOWN DIR NET 'RS485_UP_DIR' JMP1001-2 # NET 'RS485_DOWN_CMP' JMP1002-1 # JUMPER TO CONNECT UP & DOWN CMP NET 'RS485_UP_CMP' JMP1002-2 # # # JUMPERS TO CONNECT THE RS-485 DOWN CABLE TO THE BIASED TERMINATOR: # ------------------------------------------------------------------------ # NET 'RS485_DOWN_DIR' JMP1003-2 # JUMPER FOR DOWN DIR TO TERMINATOR NET 'RS485_DOWN_CMP' JMP1004-2 # JUMPER FOR DOWN CMP TO TERMINATOR NET 'RS485_TERM_DIR' JMP1003-1 R1005-2 R1006-2 # TERMINATOR DIR NET 'RS485_TERM_CMP' JMP1004-1 R1007-2 R1008-2 # TERMINATOR CMP NET 'RS485_TERM_MID' R1006-1 R1007-1 C1011-2 # TERMINATOR MIDDLE WITH # COMMON MODE CLAMP CAPACITOR NET 'RESCUE_3V3' R1005-1 C1012-1 # BIAS UP SUPPLY NET 'GROUND' R1008-1 # BIAS DOWN ANCHOR NET 'GROUND' C1011-1 C1012-2 # GROUND THE CAPS # # CONNECT THE RS-485 TRANSCEIVER TO THE ER UPROCESSOR: # ----------------------------------------------------- # NET 'GROUND' U1002-2 # TRANSCEIVER RECEIVER ENABLE_B NET 'RESCUE_UART_0_RX' U1002-1 U1001-14 R1002-2 # RECEIVED DATA FROM RS-485 NET 'RESCUE_3V3' R1002-1 # PULL-UP SUPPLY NET 'RESCUE_UART_0_TX' U1001-13 U1002-4 # TRANSMITED DATA TO RS-485 NET 'RESCUE_RS_485_TX_ENB' U1002-3 R1004-2 # TRANSCEIVER TRANSMITTER ENABLE NET 'GROUND' R1004-1 # PULL-DOWN ANCHOR # # CONNECT THE J8 DEBUG CONNECTOR TO THE ER UPROCESSOR: # ------------------------------------------------------- # NET 'RESCUE_PIO_0_0_TDO' U1001-24 J8-6 # TDO CONNECTION TO THE ER UPROCESSOR NET 'RESCUE_PIO_0_1_TDI' U1001-16 J8-8 # TDI CONNECTION TO THE ER UPROCESSOR NET 'RESCUE_PIO_0_2_TMS_SWDIO' U1001-7 J8-2 # TMS SWDIO CONNECTION TO THE ER UPROCESSOR NET 'RESCUE_PIO_0_3_TCK_SWCLK' U1001-6 J8-4 # TCK SWCLK CONNECTION TO THE ER UPROCESSOR NET 'RESCUE_PIO_0_4_TRST' U1001-4 J8-7 # TRST CONNECTION TO THE ER UPROCESSOR NET 'RESCUE_PIO_0_5_RESET' U1001-3 J8-10 # RESET CONNECTION TO THE ER UPROCESSOR NET 'RESCUE_PIO_0_0_TDO' R1009-2 # PULL-UP ON THE TDO JTAG NET 'RESCUE_3V3' R1009-1 # SIGNAL FOR THE ER UPROCESSOR NET 'RESCUE_PIO_0_1_TDI' R1010-2 # PULL-UP ON THE TDI JTAG NET 'RESCUE_3V3' R1010-1 # SIGNAL FOR THE ER UPROCESSOR NET 'RESCUE_PIO_0_2_TMS_SWDIO' R1011-2 # PULL-UP ON THE TMS JTAG NET 'RESCUE_3V3' R1011-1 # SWDIO SIGNAL FOR THE ER UPROCESSOR NET 'RESCUE_PIO_0_3_TCK_SWCLK' R1012-2 # PULL-UP ON THE TCK JTAG NET 'RESCUE_3V3' R1012-1 # SWCLK SIGNAL FOR THE ER UPROCESSOR NET 'RESCUE_PIO_0_4_TRST' R1013-2 # PULL-UP ON THE TRST JTAG NET 'RESCUE_3V3' R1013-1 # SIGNAL FOR THE ER UPROCESSOR NET 'RESCUE_PIO_0_5_RESET' R1001-2 # PULL-UP ON THE RESET NET 'RESCUE_3V3' R1001-1 # FOR THE ER UPROCESSOR NET 'BULK_3V3' F1001-1 # FUSED 3V3 POWER FOR THE RESCUE NET 'FUSED_RESCUE_DEBUG_3V3' F1001-2 J8-1 # UPROCESSOR DEBUG CONNECTOR PIN 1 NET 'GROUND' J8-3 J8-5 J8-9 # GROUND PINS IN THE DEBUG CONNECTOR # # ER UPROCESSOR ISP_MODE_B JUMPER AND ITS DEFAULT PULL-UP RESISTOR: # --------------------------------------------------------------------- # NET 'RESCUE_PIO_0_12_ISP_MODE_B' U1001-2 JMP1005-2 # ER UPROCESSOR ISP MODE B JUMPER NET 'GROUND' JMP1005-1 # JUMPER TO GROUND NET 'RESCUE_PIO_0_12_ISP_MODE_B' R1014-2 # PULL-UP ON THE ISP MODE PIN NET 'RESCUE_3V3' R1014-1 # PULL-UP SUPPLY # # ER UPROCESSOR INTERFACE SIGNALS TO THE DK BOARD: # ------------------------------------------------- # NET 'RESCUE_PIO_0_16_UART_0_RST' U1001-10 # UART 0 RST - REQUEST TO ENABLE THE RS485 # DRIVER. SPECIAL HIGH DRIVE OUTPUT PIN NET 'RESCUE_PIO_0_27_TAKE_OVER_CMD' U1001-11 # COMMAND TO TAKE CONTROL OF THE SPI BUS # TO THE DK'S FPGA/CPU BOOT MEMORY NET 'RESCUE_PIO_0_26_AWAKE' U1001-12 # ASSERTED HIGH AWAKE NET 'RESCUE_PIO_0_15_AWAKE_B' U1001-15 # ASSERTED LOW AWAKE NET 'RESCUE_PIO_0_14_SPI_SCK' U1001-25 # SERIAL CLOCK \ # | SPI BUS TO NET 'RESCUE_PIO_0_23_SPI_MOSI' U1001-26 # MASTER DATA TO SLAVE | THE DK'S # | FPGA/CPU NET 'RESCUE_PIO_0_22_SPI_MISO' U1001-27 # SLAVE DATA TO MASTER | BOOT # | MEMORY NET 'RESCUE_PIO_0_21_SPI_SSEL0' U1001-28 # SLAVE SELECT 0 / NET 'RESCUE_PIO_0_7_UART_1_TX' U1001-22 # ER UART 1 DATA TO HEADER PINS NET 'RESCUE_PIO_0_6_UART_1_RX' U1001-23 # HEADER PIN DATA TO ER UART 1 NET 'RESCUE_PIO_0_20_UART_2_TX' U1001-29 # ER UART 2 DATA TO DK'S FPGA/CPU UART NET 'RESCUE_PIO_0_19_UART_2_RX' U1001-30 # DK'S FPGA/CPU UART DATA TO ER UART 2 NET 'RESCUE_PIO_0_18_UART_3_TX' U1001-31 # ER UART 3 DATA TO (TOMCAT ?) NET 'RESCUE_PIO_0_13_UART_3_RX' U1001-1 # (TOMCAT ?) DATA TO THE ER UART 3 # # ER UPROCESSOR NO CONNECT PINS: # ------------------------------- # NET 'NO_CONN_RESCUE_PIN_5' U1001-5 # ER UPROCESSOR NO CONNECT WKTCLKIN NET 'NO_CONN_RESCUE_PIN_8' U1001-8 # ER UPROCESSOR NO CONNECT I2C0_SDA NET 'NO_CONN_RESCUE_PIN_9' U1001-9 # ER UPROCESSOR NO CONNECT I2C0_SCL NET 'NO_CONN_RESCUE_PIN_17' U1001-17 # ER UPROCESSOR NO CONNECT XTAL_OUT NET 'NO_CONN_RESCUE_PIN_18' U1001-18 # ER UPROCESSOR NO CONNECT XTAL_IN NET 'NO_CONN_RESCUE_PIN_32' U1001-32 # ER UPROCESSOR NO CONNECT DACOUT_0 # # HARDWIRED LOGIC TO ENABLE "TAKE OVER" AND ENABLE RS-485 TRANSMITTER: # ---------------------------------------------------------------------------- # # NOTE: THESE FUNCTIONS USE 1 SECTION OF THE U1551 # HEX INVERTER THAT IS OFFICIALLY PART OF THE # BARNACLE INTERFACE CIRCUIT. # # DO NOT GET CONFUSED - THERE ARE SEPARATE SANE SIGNALS # FOR THE DK'S CPU AND FOR THE EMERGENCY RESCUE UPROCESSOR. # # # GENERATE THE RESCUE UPROCESSOR IS SANE SIGNAL # NET 'RESCUE_PIO_0_15_AWAKE_B' U1551-1 R1017-1 # ER AWAKE_B SIGNAL TO INVERTER NET 'RESCUE_3V3' R1017-2 # DEFAULT PULL-UP SUPPLY NET 'ER_UPROC_AWAKE_B_INV' U1551-2 U1003-4 # INVERTED ER UPROC AWAKE_B NET 'RESCUE_PIO_0_26_AWAKE' U1003-5 R1018-1 # ER AWAKE SIGNAL NET 'GROUND' R1018-2 # DEFAULT PULL-DOWN ANCHOR NET 'ER_UPROC_IS_SANE' U1003-6 # ER UPROCESSOR IS SANE # # GENERATE THE RS-485 DRIVER ENABLE SIGNAL RST AND ER_SANE --> DRV_ENB # NET 'RESCUE_PIO_0_16_UART_0_RST' U1003-1 R1003-1 # ER UPROC UART 0 RTS SIGNAL NET 'GROUND' R1003-2 # DEFAULT PULL-DOWN ANCHOR NET 'ER_UPROC_IS_SANE' U1003-2 # ER UPROCESSOR IS SANE NET 'RESCUE_RS_485_TX_ENB' U1003-3 # RESCUE RS-485 DRIVER ENABLE # # GENERATE THE EMERGENCY RESCUE TAKES CONTROL OF THE BOOT MEMORY SPI BUS SIGNAL # NET 'RESCUE_PIO_0_27_TAKE_OVER_CMD' U1003-13 R1016-1 # COMMAND TAKE CONTROL OF THE SPI BUS # FOR THE DK'S FPGA/CPU BOOT MEMORY NET 'GROUND' R1016-2 # ITS DEFAULT PULL-DOWN ANCHOR NET 'DK_CPU_IS_SANE_B' JMP1011-1 # DK_CPU_IS_SANE_B TO JUMPER # DK_CPU_IS_SANE_B COMES FROM # U1602 IN THE SFP MODULE CIRCUITS NET 'RESCUE_3V3' JMP1012-1 # JUMPER USED TO FORCE THE ER HW LOGIC # TO IGNORE THE SANE/NOT_SANE STATE # OF THE DK'S CPU NET 'SEL_DK_CPU_STATE_OR_HW' JMP1011-2 JMP1012-2 # JUMPER COMMON - USED TO SELECT: NET 'SEL_DK_CPU_STATE_OR_HW' U1003-12 # DK CPU'S REAL STATE OR # IGNORE THE DK'S CPU STATE NET 'ER_COMMAND_AND_CPU_STATE' U1003-11 # TAKE OVER COMMAND AND DK CPU'S STATE # ITS REAL STATE OR IGNORE ITS STATE NET 'ER_UPROC_IS_SANE' U1003-9 # ER UPROCESSOR IS SANE NET 'ER_COMMAND_AND_CPU_STATE' U1003-10 # THIS STEP MAKES THE AND OF: # TAKE OVER COMMAND # AND ER_UPROC_IS_SANE # AND DK CPU'S STATE - # ITS REAL STATE OR IGNORE ITS STATE NET 'ER_CONTROLS_BOOT_SPI' U1003-8 # CONTROL SIGNAL TO THE BOOT # MEMORY SPI BUS MULTIPLEXER # # 3.3 VOLT POWER AND GROUNDS TO U1001 ER UPROCESSOR: # ---------------------------------------------------- # NET 'BULK_3V3' L1001-2 # BULK_3V3 POWER TO FILTER NET 'RESCUE_3V3' L1001-1 # FILTERED RESCUE 3V3 POWER NET 'RESCUE_3V3' C1001-1 C1002-1 C1003-1 # 3V3 BYPASS CAPS NET 'GROUND' C1001-2 C1002-2 C1003-2 # GROUND SIDE OF FILTER CAPS NET 'RESCUE_3V3' U1001-19 U1001-21 # 3V3 POWER TO THE RESCUE UPROCESSOR NET 'GROUND' U1001-33 U1001-20 # GROUNDS TO THE RESCUE UPROCESSSOR # # 3V3 POWER TO THE VDD AND VREFP PINS # GROUNDS TO THE GND AND VREFN PINS # # # NOW GROUNDS TO THE OTHER 3 CENTER PAD THERMAL VIAS # NET 'GROUND' U1001-34 U1001-35 U1001-36 # GROUND THE OTHER 3 THERMAL VIAS # # 3.3 VOLT POWER AND GROUNDS TO U1002 RS-485 TRANSCEIVER: # --------------------------------------------------------- # NET 'BULK_3V3' C1004-2 C1005-2 # 3V3 BYPASS CAPS NET 'GROUND' C1004-1 C1005-1 # GROUND SIDE OF FILTER CAPS NET 'BULK_3V3' U1002-8 # 3V3 POWER TO THE RS-485 TRANSCEIVER NET 'GROUND' U1002-5 # GROUND TO THE RS-485 TRANSCEIVER # # 3.3 VOLT POWER AND GROUNDS TO U1003 HARDWIRED LOGIC: # -------------------------------------------------------------- # NET 'BULK_3V3' U1003-14 C1006-2 # 3V3 POWER TO THE HARDWIRED LOGIC NET 'GROUND' U1003-7 C1006-1 # GROUND TO THE HARDWIRED LOGIC # # USB PHY NETS AND CONNECTION TO THE DK'S CPU # ----------------------------------------------- # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # INITIAL REV. 24-NOV-2022 # CURRENT REV. 5-DEC-2023 # # # THIS NET LIST HOLDS THE USB PHY AND ITS CONNECTION # TO THE DK'S CPU AND THE USB POWER NETS. # # # THE COMPONENTS FOR THE USB PHY AND ITS POWER AND # CONNECTION TO THE DK'S CPU ARE IN THE RANGE 1051 TO 1099. # # # USB PHY TO/FROM DK CPU CONNECTIONS THIS IS THE ULPI INTERFACE: # ---------------------------------------------------------------------- # NET 'CPU_USB_CLK' U1-N2 R1051-2 # CPU USB_CLK TO TERM RESISTOR NET 'USB_PHY_CLK' U1051-1 R1051-1 # PHY USB_CLK FROM TERM RESISTOR NET 'CPU_USB_DIR' U1-N3 R1052-2 # CPU USB_DIR TO TERM RESISTOR NET 'USB_PHY_DIR' U1051-31 R1052-1 # PHY USB_RIR FROM TERM RESISTOR NET 'CPU_USB_NXT' U1-M4 R1053-2 # CPU USB_NXT TO TERM RESISTOR NET 'USB_PHY_NXT' U1051-2 R1053-1 # PHY USB_NXT FROM TERM RESISTOR NET 'CPU_USB_STP' U1-M5 R1054-2 # CPU USB_STP TO TERM RESISTOR NET 'USB_PHY_STP' U1051-29 R1054-1 # PHY USB_STP FROM TERM RESISTOR NET 'CPU_USB_DATA_0' U1-N1 R1055-2 # CPU USB_DATA_0 TO TERM RESISTOR NET 'USB_PHY_DATA_0' U1051-3 R1055-1 # PHY USB_DATA_0 FROM TERM RESISTOR NET 'CPU_USB_DATA_1' U1-M1 R1056-2 # CPU USB_DATA_1 TO TERM RESISTOR NET 'USB_PHY_DATA_1' U1051-4 R1056-1 # PHY USB_DATA_1 FROM TERM RESISTOR NET 'CPU_USB_DATA_2' U1-L3 R1057-2 # CPU USB_DATA_2 TO TERM RESISTOR NET 'USB_PHY_DATA_2' U1051-5 R1057-1 # PHY USB_DATA_2 FROM TERM RESISTOR NET 'CPU_USB_DATA_3' U1-L4 R1058-2 # CPU USB_DATA_3 TO TERM RESISTOR NET 'USB_PHY_DATA_3' U1051-6 R1058-1 # PHY USB_DATA_3 FROM TERM RESISTOR NET 'CPU_USB_DATA_4' U1-M2 R1059-2 # CPU USB_DATA_4 TO TERM RESISTOR NET 'USB_PHY_DATA_4' U1051-7 R1059-1 # PHY USB_DATA_4 FROM TERM RESISTOR NET 'CPU_USB_DATA_5' U1-L2 R1060-2 # CPU USB_DATA_5 TO TERM RESISTOR NET 'USB_PHY_DATA_5' U1051-9 R1060-1 # PHY USB_DATA_5 FROM TERM RESISTOR NET 'CPU_USB_DATA_6' U1-L5 R1061-2 # CPU USB_DATA_6 TO TERM RESISTOR NET 'USB_PHY_DATA_6' U1051-10 R1061-1 # PHY USB_DATA_6 FROM TERM RESISTOR NET 'CPU_USB_DATA_7' U1-M6 R1062-2 # CPU USB_DATA_7 TO TERM RESISTOR NET 'USB_PHY_DATA_7' U1051-13 R1062-1 # PHY USB_DATA_7 FROM TERM RESISTOR # # REFERENCE CLOCK FROM A PLL IN THE FPGA TO THE USB PHY REFERENCE CLOCK INPUT PIN: # ------------------------------------------------------------------------------------ NET 'FPGA_REF_CLK_TO_USB_PHY' R1063-2 # FPGA USB PHY REF CLK TO SERIES TERM NET 'USB_PHY_REF_CLK_INPUT' U1051-26 R1063-1 # SERIES TERM TO USB PHY REF CLK INPUT # # USB RESET SIGNAL: # ------------------- # NET 'USB_RESET_B' U1051-27 # USB_RESET_B SIGNAL TO USB PHY CHIP NET 'USB_RESET_B' U1052-1 # USB_RESET_B SIGNAL TO USB HIGH SIDE SWITCH # # USB PHY CHIP - NO_CONN AND PAD PINS: # -------------------------------------- # NET 'NO_CONN_USB_PIN_12' U1051-12 # USB NO_CONN PIN 12 NC NET 'NO_CONN_USB_PIN_15' U1051-15 # USB NO_CONN PIN 15 SPK_L NET 'NO_CONN_USB_PIN_16' U1051-16 # USB NO_CONN PIN 16 SPK_R NET 'NO_CONN_USB_PIN_25' U1051-25 # USB NO_CONN PIN 25 XO NET 'NO_CONN_USB_PIN_30' U1051-30 # USB NO_CONN PIN 30 NC NET 'USB_PHY_CPEN_OUTPUT' U1051-17 TP1051-1 # USB PHY PIN 17 CPEN OUTPUT # ROUTED TO A TEST POINT PAD # # USB PHY CHIP - JUMPER SETUP AND CONTROL PINS: # ----------------------------------------------- # # USB PHY REFERENCE FREQUENCY SELECT JUMPERS NET 'USB_PHY_REF_SEL_0' U1051-8 # USB PHY REF SELECT 0 PIN NET 'USB_PHY_REF_SEL_1' U1051-11 # USB PHY REF SELECT 1 PIN NET 'USB_PHY_REF_SEL_2' U1051-14 # USB PHY REF SELECT 2 PIN NET 'USB_PHY_REF_SEL_0' JMP1051-1 JMP1052-2 # USB PHY REFERENCE FREQUENCY SELECT 0 NET 'USB_PHY_REF_SEL_1' JMP1053-1 JMP1054-2 # USB PHY REFERENCE FREQUENCY SELECT 1 NET 'USB_PHY_REF_SEL_2' JMP1055-1 JMP1056-2 # USB PHY REFERENCE FREQUENCY SELECT 2 NET 'USB_PHY_3V3' JMP1051-2 JMP1053-2 JMP1055-2 # PULL-UP SOURCE TO JUMPERS NET 'GROUND' JMP1052-1 JMP1054-1 JMP1056-1 # GROUND ANCHOR TO JUMPERS # USB PHY ID SELECT JUMPERS NET 'USB_PHY_ID_SEL' U1051-23 # USB PHY ID PIN NET 'USB_PHY_ID_SEL' JMP1057-1 JMP1058-2 # USB PHY ID SELECT JUMPERS NET 'USB_PHY_3V3' JMP1057-2 # PULL-UP SOURCE TO JUMPERS NET 'GROUND' JMP1058-1 # GROUND ANCHOR TO JUMPERS # USB PHY VBUS SELECT RESISTORS NET 'USB_PHY_VBUS_SEL' U1051-22 # USB PHY VBUS SELECT PIN NET 'USB_PHY_VBUS_SEL' R1065-1 R1066-2 # USB PHY VBUS SELECT RESISTORS NET 'USB_PHY_3V3' R1065-2 # PULL-UP SOURCE TO RESISTOR NET 'GROUND' R1066-1 # GROUND ANCHOR TO RESISTOR # # USB CONNECTOR PIN CONNECTIONS: # -------------------------------- # NET 'USB_DATA_DIR' J15-3 # USB DATA DIRECT NET 'USB_DATA_CMP' J15-2 # USB DATA COMPLEMENT NET 'USB_SWITCHED_POS_POWER' J15-1 # USB SWITCHED POSITIVE POWER NET 'GROUND' J15-4 # USB POWER RETURN NET 'GROUND' J15-5 J15-6 # USB CONNECTOR SHIELD NET 'GROUND' J15-7 J15-8 # USB CONNECTOR SHIELD # # USB PHY CHIP DATA TO/FROM USB CONNECTOR: # -------------------------------------------- # NET 'USB_DATA_DIR' U1051-18 TVS1052-1 # USB DIRECT DATA NET 'USB_DATA_CMP' U1051-19 TVS1051-1 # USB COMPLEMENT DATA NET 'GROUND' TVS1051-2 TVS1052-2 # GROUND THE ESD SUPPRESSORS # # USB HIGH SIDE SWITCH INPUT POWER & CONTROL: # ---------------------------------------------- # NET 'BULK_5V0' F1051-1 # BULK POWER FUSE TO HIGH-SIDE SWCH NET 'USB_HS_5V0' F1051-2 L1052-2 # FUSED POWER TO HIGH-SIDE SWCH FILTER NET 'USB_FLTR_5V0' C1057-1 L1052-1 U1052-7 # FILTERED POWER TO HIGH-SIDE SWCH NET 'GROUND' C1057-2 # GND THE FILTER BYPASS CAP FOR HS SWCH NET 'GROUND' U1052-3 # GND OF THE USB HIGH-SIDE SWITCH NET 'USB_HS_SWCH_FLAG' R1068-2 U1052-2 # USB HIGH-SIDE SWCH FLAG PIN NET 'USB_FLTR_5V0' R1068-1 # PULL-UP SOURCE FOR FLAG PU RESISTOR NET 'USB_HS_SWCH_ILIM' R1067-2 U1052-4 # USB HS SWCH I_LIMIT RESISTOR NET 'GROUND' R1067-1 # GROUND THE I_LIMIT RESISTOR NET 'NO_CONN_USB_HS_SWCH_5' U1052-5 # NO_CONN PIN 5 ON THE USB HS SWCH # # USB HIGH SIDE SWITCH POWER TO USB CONNECTOR: # ------------------------------------------------ # NET 'USB_SWITCHED_POS_POWER' U1052-6 U1052-8 # SWITCHED USB POWER TO CONNECTOR NET 'USB_SWITCHED_POS_POWER' C1058-1 # SWITCHED USB POWER TO CONNECTOR NET 'GROUND' C1058-2 # GROUND THE USB CONN POWER CAP # # INTERNAL PS AND BIAS CONNECTIONS FOR THE USB PHY CHIP: # --------------------------------------------------------- # NET 'USB_PHY_INT_3V3' U1051-20 C1055-1 # BYPASS USB PHY INTERNAL 3V3 NET 'USB_PHY_INT_1V8' U1051-28 C1056-1 # BYPASS USB PHY INTERNAL 1V8 NET 'GROUND' C1055-2 C1056-2 # GROUND SIDE OF BYPASS CAPS NET 'USB_PHY_INT_BIAS' U1051-24 R1064-2 # USB PHY BIAS SET RESISTOR NET 'GROUND' R1064-1 # GROUND SIDE OF BIAS SET RESISTOR # # 3.3 VOLT POWER AND GROUNDS TO USB PHY CHIP: # ----------------------------------------------- # NET 'BULK_3V3' L1051-1 # BULK_3V3 POWER TO FILTER NET 'USB_PHY_3V3' L1051-2 # FILTERED USB 3V3 POWER NET 'USB_PHY_3V3' C1051-2 C1052-2 # 3V3 BYPASS CAPS NET 'GROUND' C1051-1 C1052-1 # GROUND SIDE OF FILTER CAPS NET 'USB_PHY_3V3' U1051-32 # 3V3 POWER TO THE USB PHY CHIP NET 'GROUND' U1051-33 U1051-34 U1051-35 # GROUNDS TO THE USB PHY CHIP NET 'GROUND' U1051-36 U1051-37 U1051-38 # GROUNDS TO THE USB PHY CHIP NET 'GROUND' U1051-39 U1051-40 U1051-41 # GROUNDS TO THE USB PHY CHIP # # 5.0 VOLT POWER TO USB PHY CHIP: # ----------------------------------- # NET 'BULK_5V0' C1053-1 C1054-1 # 5V0 BYPASS CAPS NET 'GROUND' C1053-2 C1054-2 # GROUND SIDE OF FILTER CAPS NET 'BULK_5V0' U1051-21 # 5V0 POWER TO THE USB PHY CHIP # # LIST THE NETNAMES OF THE SIGNALS THAT MUST BE # CONNECTED TO FPGA FLOATING PINS. HERE JUST LIST # THE NETNAMES - THE ACTUAL CONNECTIONS TO THESE # FPGA FLOATING PINS ARE MADE IN THE NETS FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # ---------------------------------------------------- # # # THIS IS A 3V3 SIGNAL: REFERENCE CLOCK TO THE USB PHY CHIP # ------------------------------------------------------------- # # # NET 'FPGA_REF_CLK_TO_USB_PHY' # FPGA USB PHY REF CLK TO SERIES TERM # # # # BB AUDIO ADC # ---------------- # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # INITIAL REV. 27-NOV-2022 # CURRENT REV. 5-DEC-2023 # # # THIS NET LIST HOLDS THE BB AUDIO ADC AND # ITS CONNECTIONS TO THE DK FPGA. # # # THE COMPONENTS FOR THE BB AUDIO ADC # ARE IN THE RANGE 1101 TO 1149. # # # BB AUDIO ADC ANALOG INPUT SIGNALS & THEIR AC COUPLING CAPACITORS: # -------------------------------------------------------------------- # NET 'INTERPOSER_1_AUDIO_DIR' C1111-2 # INTERPOSER #1 AUDIO SIGNAL DIR NET 'BB_AUDIO_ADC_INPUT_1_DIR' U1101-6 C1111-1 # BB AUDIO ADC ANALOG INPUT #1 DIR NET 'INTERPOSER_1_AUDIO_CMP' C1112-2 # INTERPOSER #1 AUDIO SIGNAL CMP NET 'BB_AUDIO_ADC_INPUT_1_CMP' U1101-7 C1112-1 # BB AUDIO ADC ANALOG INPUT #1 CMP NET 'INTERPOSER_2_AUDIO_DIR' C1113-2 # INTERPOSER #2 AUDIO SIGNAL DIR NET 'BB_AUDIO_ADC_INPUT_2_DIR' U1101-8 C1113-1 # BB AUDIO ADC ANALOG INPUT #2 DIR NET 'INTERPOSER_2_AUDIO_CMP' C1114-2 # INTERPOSER #2 AUDIO SIGNAL CMP NET 'BB_AUDIO_ADC_INPUT_2_CMP' U1101-9 C1114-1 # BB AUDIO ADC ANALOG INPUT #2 CMP NET 'NO_CONN_AUDIO_ADC_INPUT_3_DIR' U1101-10 # NO CONNECTION INPUT 3 DIR PIN 10 NET 'NO_CONN_AUDIO_ADC_INPUT_3_CMP' U1101-11 # NO CONNECTION INPUT 3 CMP PIN 11 NET 'NO_CONN_AUDIO_ADC_INPUT_4_DIR' U1101-12 # NO CONNECTION INPUT 4 DIR PIN 12 NET 'NO_CONN_AUDIO_ADC_INPUT_4_CMP' U1101-13 # NO CONNECTION INPUT 4 CMP PIN 13 # # BB AUDIO ADC TO/FROM DK FPGA CONNECTIONS: # --------------------------------------------- # NET 'FPGA_BB_ADC_CLK_OUT' R1101-1 # FPGA BB AUDIO ADC CLK TO TERM RESISTOR NET 'BB_AUDIO_ADC_CLK_GPIO1' U1101-20 R1101-2 # TERM RESISTOR TO BB ADC CLK GPIO1 INPUT NET 'BB_AUDIO_ADC_SDOUT' U1101-21 R1102-2 # BB ADC SERIAL DATA TO TERM RESISTOR NET 'FPGA_BB_ADC_SDATA_IN' R1102-1 # TERM RESISTOR TO FPGA BB ADC SDATA INPUT NET 'BB_AUDIO_ADC_BCLK_OUT' U1101-22 R1103-2 # BB ADC BCLK OUTPUT TO TERM RESISTOR NET 'FPGA_BB_ADC_BCLK_IN' R1103-1 # TERM RESISTOR TO FPGA BB ADC BCLK INPUT NET 'BB_AUDIO_ADC_FSYNC_OUT' U1101-23 R1104-2 # BB ADC FSYNC OUTPUT TO TERM RESISTOR NET 'FPGA_BB_ADC_FSYNC_IN' R1104-1 # TERM RESISTOR TO FPGA BB ADC FSYNC INPUT # # BB AUDIO ADC RESET SIGNAL: # ------------------------------ # NET 'BB_AUDIO_ADC_RESET_B' U1101-14 # BB AUDIO ADC RESET_B SIGNAL # # INTERNAL PS AND BIAS CONNECTIONS FOR THE BB AUDIO ADC CHIP: # -------------------------------------------------------------- # NET 'BB_AUDIO_ADC_AREG' U1101-2 C1105-1 C1106-2 # BYPASS ANALOG REGULATOR NET 'GROUND' C1105-2 C1106-1 # GROUND SIDE OF BYPASS CAPS NET 'BB_AUDIO_ADC_VREF' U1101-3 C1107-1 # BYPASS VREF PIN NET 'GROUND' C1107-2 # GROUND SIDE OF BYPASS CAP NET 'BB_AUDIO_ADC_MIC_BIAS' U1101-5 C1108-2 # BYPASS MIC_BIAS PIN NET 'GROUND' C1108-1 # GROUND SIDE OF BYPASS CAP NET 'BB_AUDIO_ADC_DREG' U1101-24 C1109-1 C1110-2 # BYPASS DIGITAL REGULATOR NET 'GROUND' C1109-2 C1110-1 # GROUND SIDE OF BYPASS CAPS # # BB AUDIO ADC I2C BUS CONNECTION: # ------------------------------------ # NET 'I2C_SCLK_SENSOR_BB_ADC' U1101-17 # I2C BUS SCLK CONNECTION NET 'I2C_DATA_SENSOR_BB_ADC' U1101-18 # I2C BUS DATA CONNECTION # # BB AUDIO ADC ADDRESS PINS: # ------------------------------ # NET 'GROUND' U1101-15 U1101-16 # GROUNDS TO THE ADDRESS PINS # # LIST THE NETNAMES OF THE SIGNALS THAT MUST BE # CONNECTED TO FPGA FLOATING PINS. HERE JUST LIST # THE NETNAMES - THE ACTUAL CONNECTIONS TO THESE # FPGA FLOATING PINS ARE MADE IN THE NETS FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # ---------------------------------------------------- # # # ALL OF THESE ARE 1V8 SIGNALS: CLOCK TO AND DATA FROM THE AUDIO ADC # --------------------------------------------------------------------- # # # NET 'FPGA_BB_ADC_CLK_OUT' # FPGA BB AUDIO ADC CLK TO TERM RESISTOR # # NET 'FPGA_BB_ADC_SDATA_IN' # TERM RESISTOR TO FPGA BB ADC SDATA INPUT # # NET 'FPGA_BB_ADC_BCLK_IN' # TERM RESISTOR TO FPGA BB ADC BCLK INPUT # # NET 'FPGA_BB_ADC_FSYNC_IN' # TERM RESISTOR TO FPGA BB ADC FSYNC INPUT # # # THE SENSOR I2C BUS CONNECTIONS TO THE FPGA (THIS I2C BUS IS ALSO # USED TO SETUP THIS AUDIO ADC) ARE REFERENCED IN THE ENVIRONMENTAL # SENSORS NETS FILE. # # # # 3.3 VOLT POWER AND GROUNDS TO BB AUDIO ADC CHIP: # ---------------------------------------------------- # NET 'BULK_3V3' L1101-2 # BULK_3V3 POWER TO FILTER NET 'BB_AUDIO_ADC_3V3' L1101-1 # FILTERED BB AUDIO ADC 3V3 POWER NET 'BB_AUDIO_ADC_3V3' C1101-1 C1102-2 # 3V3 BYPASS CAPS NET 'GROUND' C1101-2 C1102-1 # GROUND SIDE OF FILTER CAPS NET 'BB_AUDIO_ADC_3V3' U1101-1 # 3V3 POWER TO THE BB AUDIO ADC NET 'GROUND' U1101-4 # GROUND TO THE AVSS ADC PIN NET 'GROUND' U1101-25 U1101-26 U1101-27 # GROUNDS TO THE THERMAL VIA PINS NET 'GROUND' U1101-28 U1101-29 U1101-30 # GROUNDS TO THE THERMAL VIA PINS NET 'GROUND' U1101-31 U1101-32 U1101-33 # GROUNDS TO THE THERMAL VIA PINS # # 1.8 VOLT POWER TO BB AUDIO ADC CHIP: # ---------------------------------------- # NET 'BULK_1V8' L1102-1 # BULK_1V8 POWER TO FILTER NET 'BB_AUDIO_ADC_1V8' L1102-2 # FILTERED BB AUDIO ADC 1V8 POWER NET 'BB_AUDIO_ADC_1V8' C1103-2 C1104-1 # 1V8 BYPASS CAPS NET 'GROUND' C1103-1 C1104-2 # GROUND SIDE OF FILTER CAPS NET 'BB_AUDIO_ADC_1V8' U1101-19 # 1V8 POWER TO THE BB AUDIO ADC # # JTAG FOR THE DK'S FPGA/CPU NETS # -------------------------------------- # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # INITIAL REV. 30-NOV-2023 # CURRENT REV. 20-DEC-2023 # # # # THIS NET LIST HOLDS THE JTAG FOR THE DK'S FPGA/CPU # ------------------------------ # # THE COMPONENTS FOR THE # JTAG FOR THE DK'S FPGA/CPU # ARE IN THE RANGE 1401 TO 1449. # # # NOTE: THE HEX INVERTER U1402 OFFICIALLY BELONGS TO # THIS NET LIST FILE THAT COVERS THE DK FPGA/CPU # JTAG CIRCUITS BUT THAT ONE SECTION IN THE U1402 # HEX INVERTER IS USED TO HANDLE INVERTING THE # DK_CPU_IS_AWAKE_B SIGNAL IN THE STARTUP AND RESETS # NET LIST FILE. # # # THE JTAG CONNECTION TO THE FPGA/CPU ON THE DK BOARD IS MADE # VIA THE FIRST 10 PIN ON THE DK J12 ACCESS CONNECTOR. # # ACCESS CONNECTOR J12 PINOUT (FIRST 10 PINS) # ------------------------------------------------- # # 1. JTAG_TCLK 2. GROUND # 3. JTAG_TDO 4. NO_CONN # 5. JTAG_TMS 6. JTAG_3V3 # 7. NO_CONN 8. JTAG_TRSTB # 9. JTAG_TDI 10. GROUND # # # THIS JTAG PINOUT MATCHES THE MICROCHIP "STANDARD" FOR THEIR # POLARFIRE SOC PARTS AS SHOWN ON PAGE 15 OF THEIR, "BOARD # DESIGN GUIDELINES" DOCUMENT. # # NOTE - THIS DOCUMENT IS NOT CONSISTENT: # # FOR THE TRSTB SIGNAL THIS DOCUMENT SHOWS A 1K OHM PULL-DOWN # RESISTOR AND THE TEXT SAYS, "MUST BE CONNECTED TO VDDI3 THROUGH # A 1K OHM RESISTOR" AND IT ALSO SAYS "TRSTB MUST BE HELD LOW # DURING DEVICE OPERATION". WHAT OPERATION - NORMAL OPERATION # OR JTAG OPERATION ??? # # FOR THE TCLK SIGNAL THIS DOCUMENT SHOWS A 1K OHM PULL-DOWN # RESISTOR AND THE TEXT SAYS, "MUST BE CONNECTED TO VSS THROUGH # A 10K OHM RESISTOR". # # SEE ALSO SHEETS 12 AND 24 OF THE SCHEMATICS FOR THE # POLARFIRE SOC SEV KIT DEMO BOARD. # # FROM READING VARIOUS OTHER JTAG DOCUMENTS AND CHECKING THEIR # DEMO-BOARD SCHEMATICS I WILL DO THE FOLLOWING ON THE DK BOARD: # # TCLK PULL-DOWN # TMS PULL-UP # TDI PULL-UP # TDO SERIES TERMINATOR # TRSTB PULL-DOWN # # # TCLK INPUT SIGNAL TO THE DK BOARD: # --------------------------------------- # NET 'JTAG_TCLK_INPUT' J12-1 R1401-1 U1401-1 # TCLK INPUT TO PULL-DOWN AND 1ST BUFFER NET 'JTAG_TCLK_1ST_2ND' U1401-2 U1401-3 # TCLK 1ST BUF OUTPUT TO 2ND BUF INPUT NET 'JTAG_TCLK_2ND_TERM' U1401-4 R1405-2 # TCLK 2ND BUF OUTPUT TO SERIES TERM NET 'JTAG_TCLK_TERM_FPGA' R1405-1 U1-H12 # TCLK SERIES TERM TO FPGA INPUT NET 'GROUND' R1401-2 # PULL-DOWN ANCHOR # # TMS INPUT SIGNAL TO THE DK BOARD: # -------------------------------------- # NET 'JTAG_TMS_INPUT' J12-5 R1402-1 U1401-13 # TMS INPUT TO PULL-UP AND 1ST BUFFER NET 'JTAG_TMS_1ST_2ND' U1401-12 U1401-11 # TMS 1ST BUF OUTPUT TO 2ND BUF INPUT NET 'JTAG_TMS_2ND_TERM' U1401-10 R1406-2 # TMS 2ND BUF OUTPUT TO SERIES TERM NET 'JTAG_TMS_TERM_FPGA' R1406-1 U1-J12 # TMS SERIES TERM TO FPGA INPUT NET 'BULK_3V3' R1402-2 # PULL-UP 3V3 SOURCE # # TDI INPUT SIGNAL TO THE DK BOARD: # -------------------------------------- # NET 'JTAG_TDI_INPUT' J12-9 R1403-1 U1401-9 # TDI INPUT TO PULL-UP AND 1ST BUFFER NET 'JTAG_TDI_1ST_2ND' U1401-8 U1401-5 # TDI 1ST BUF OUTPUT TO 2ND BUF INPUT NET 'JTAG_TDI_2ND_TERM' U1401-6 R1407-2 # TDI 2ND BUF OUTPUT TO SERIES TERM NET 'JTAG_TDI_TERM_FPGA' R1407-1 U1-H11 # TDI SERIES TERM TO FPGA INPUT NET 'BULK_3V3' R1403-2 # PULL-UP 3V3 SOURCE # # TDO OUTPUT SIGNAL FROM THE DK BOARD: # ----------------------------------------- # NET 'JTAG_TDO_FPGA_1ST_TERM' U1-J11 R1409-1 # TDO FPGA OUTPUT TO 1ST SERIES TERM NET 'JTAG_TDO_1ST_TERM_1ST_BUF' R1409-2 U1402-3 # TDO 1ST TERM TO 1ST BUF INPUT NET 'JTAG_TDO_1ST_2ND' U1402-4 U1402-5 # TDO 1ST BUF OUTPUT TO 2ND BUF INPUT NET 'JTAG_TDO_2ND_BUF_2ND_TERM' U1402-6 R1408-2 # TDO 2ND BUF OUTPUT TO 2ND TERM NET 'JTAG_TDO_OUTPUT' R1408-1 J12-3 # 2ND SERIES TERM TO TDO OUTPUT PIN # # TRST_B INPUT SIGNAL TO THE DK BOARD: # -------------------------------------- # NET 'JTAG_TRST_B_INPUT' J12-8 R1404-1 U1402-11 # TRST_B INPUT TO PULL-DOWN AND 1ST BUFFER NET 'JTAG_TRST_B_1ST_2ND' U1402-10 U1402-9 # TRST_B 1ST BUF OUTPUT TO 2ND BUF INPUT NET 'JTAG_TRST_B_2ND_FPGA' U1402-8 U1-J10 # TRST_B 2ND BUF OUTPUT TO FPGA INPUT NET 'GROUND' R1404-2 # PULL-DOWN ANCHOR # # 3.3 VOLT POWER AND GROUNDS TO THE JTAG PART OF THE J12 ACCESS CONNECTOR: # ----------------------------------------------------------------------------- # NET 'BULK_3V3' F1401-2 # BULK_3V3 POWER TO THE JTAG FUSE NET 'JTAG_3V3' F1401-1 J12-6 # 3V3 POWER TO THE JTAG CONNECTOR NET 'GROUND' J12-2 J12-10 # GROUND PINS IN THE JTAG PART OF J12 NET 'NO_CONN_J12_PIN_4' J12-4 # NO CONNECT PIN #4 IN J12 NET 'NO_CONN_J12_PIN_7' J12-7 # NO CONNECT PIN #7 IN J12 # # 3.3 VOLT POWER AND GROUNDS TO THE JTAG BUFFER CHIPS: # -------------------------------------------------------- # NET 'BULK_3V3' C1401-1 C1402-1 C1403-1 # 3V3 BYPASS CAPS NET 'GROUND' C1401-2 C1402-2 C1403-2 # GROUND SIDE OF BYPASS CAPS NET 'BULK_3V3' U1401-14 U1402-14 # 3V3 POWER TO THE BUFFER CHIPS NET 'GROUND' U1401-7 U1402-7 # GROUND PINS ON THE BUFFER CHIPS NET 'GROUND' U1402-13 # GROUND UNUSED INPUT TO BUFFER U1402 # # CPU BOOT MEMORY CPU QSPI PORT # -=====---------------------------- # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # INITIAL REV. 27-NOV-2022 # CURRENT REV. 30-NOV-2023 # # # THIS NET LIST HOLDS THE CPU BOOT MEMORY # ITS CONNECTIONS TO THE DK CPU QSPI PORT. # # # THE COMPONENTS FOR THE CPU BOOT MEMORY # ARE IN THE RANGE 1201 TO 1249. # # # CPU BOOT MEMORY TO/FROM DK CPU QSPI PORT: # -===----------------------------------------- # NET 'CPU_BOOT_MEM_SELECT_B' U1201-7 R1203-2 R1204-2 # SELECT_B TO PULL-UP AND TERM NET 'CPU_QSPI_SS0' U1-N9 R1204-1 # TERM RESISTOR TO CPU QSPI PORT NET 'CPU_BOOT_MEM_DQ3_HOLD_B' U1201-1 R1202-2 R1205-2 # DQ3/HOLD_B TO PULL-UP AND TERM NET 'CPU_QSPI_DATA_3' U1-N11 R1205-1 # TERM RESISTOR TO CPU QSPI PORT NET 'CPU_BOOT_MEM_DQ2_W_B' U1201-9 R1201-2 R1206-2 # DQ2/W_B TO PULL-UP AND TERM NET 'CPU_QSPI_DATA_2' U1-M11 R1206-1 # TERM RESISTOR TO CPU QSPI PORT NET 'CPU_BOOT_MEM_DQ1' U1201-8 R1207-2 # DQ1 TO TERMINATOR RESISTOR NET 'CPU_QSPI_DATA_1' U1-M9 R1207-1 # TERM RESISTOR TO CPU QSPI PORT NET 'CPU_BOOT_MEM_DQ0' U1201-15 R1208-2 # DQ0 TO TERMINATOR RESISTOR NET 'CPU_QSPI_DATA_0' U1-L10 R1208-1 # TERM RESISTOR TO CPU QSPI PORT NET 'CPU_BOOT_MEM_CLOCK' U1201-16 R1209-2 # CLOCK TO TERMINATOR RESISTOR NET 'CPU_QSPI_CLK' U1-M10 R1209-1 # TERM RESISTOR TO CPU QSPI PORT NET 'BULK_3V3' R1201-1 R1202-1 R1203-1 # PULL-UP 3V3 SOURCE # # CPU BOOT MEMORY RESET SIGNAL: # -===-------------------------- # NET 'CPU_BOOT_MEM_RESET_B' U1201-3 R1210-2 # CPU BOOT MEMORY RESET_B PIN NET 'BULK_3V3' R1210-1 # PULL-UP 3V3 SOURCE # # 3.3 VOLT POWER AND GROUNDS TO THE CPU BOOT MEMORY: # ------------------------------------===-------------- # NET 'BULK_3V3' C1201-2 C1202-2 C1203-1 # 3V3 BYPASS CAPS NET 'GROUND' C1201-1 C1202-1 C1203-2 # GROUND SIDE OF BYPASS CAPS NET 'BULK_3V3' U1201-2 # 3V3 POWER TO THE CPU BOOT MEMORY NET 'GROUND' U1201-10 # GROUND TO THE CPU BOOT MEMORY # # CPU BOOT MEMORY NO_CONNECT PINS: # -===------------------------------- # NET 'NO_CONN_CPU_BOOT_MEM_PIN_4' U1201-4 # NO CONN U1201 PIN 4 NET 'NO_CONN_CPU_BOOT_MEM_PIN_5' U1201-5 # NO CONN U1201 PIN 5 NET 'NO_CONN_CPU_BOOT_MEM_PIN_6' U1201-6 # NO CONN U1201 PIN 6 NET 'NO_CONN_CPU_BOOT_MEM_PIN_11' U1201-11 # NO CONN U1201 PIN 11 NET 'NO_CONN_CPU_BOOT_MEM_PIN_12' U1201-12 # NO CONN U1201 PIN 12 NET 'NO_CONN_CPU_BOOT_MEM_PIN_13' U1201-13 # NO CONN U1201 PIN 13 NET 'NO_CONN_CPU_BOOT_MEM_PIN_14' U1201-14 # NO CONN U1201 PIN 14 # # FPGA BOOT MEMORY FPGA BANK #3 # -=====---------------------------- # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # INITIAL REV. 27-NOV-2022 # CURRENT REV. 30-NOV-2023 # # # THIS NET LIST HOLDS THE: # # FPGA BOOT MEMORY AND ITS CONNECTIONS TO THE DK FPGA BANK #3 # ------------------------------------------------------------- # # # NOTE: THIS FILE ALSO HOLDS THE NETS FOR SOME: # # BANK #3 PULL-UP RESISTORS FOR DEFAULT OPERATION # --------------------------------------------------- # # # THE COMPONENTS FOR THE FPGA BOOT MEMORY # ARE IN THE RANGE 1251 TO 1299. # # THE COMPONENTS FOR THE BANK #3 DEFAULT OPERATION PULL-UP RESISTORS # ARE FROM A SEPARATE COMPS FILE: R1351, R1352, R1353. # # # FPGA BOOT MEMORY TO/FROM MULTIPLEXER: # -===--------------------------------------- # NET 'FPGA_BOOT_MEM_SELECT_B' U1251-7 U1252-3 U1252-18 # SELECT_B FROM MUX. NET 'FPGA_BOOT_MEM_DQ1' U1251-8 U1252-15 U1252-4 # MISO / DQ1 TO MUX. NET 'FPGA_BOOT_MEM_DQ0' U1251-15 U1252-7 U1252-14 # MOSI / DQ0 FROM MUX. NET 'FPGA_BOOT_MEM_CLOCK' U1251-16 U1252-9 U1252-12 # CLOCK / SCK FROM MUX. # # MULTIPLEXER TO/FROM DK FPGA BANK #3: # ------------------------------------------ # NET 'FPGA_BANK_3_SPI_SS' U1-J9 U1252-2 # FPGA SPI SEL_B TO FPGA BOOT MEM MUX. NET 'FPGA_BOOT_MUX_FPGA_MISO' U1252-16 R1254-2 # SPI MISO FROM MUX TO TERM RES NET 'FPGA_BANK_3_SPI_MISO' U1-K10 R1254-1 # TERM RES TO FPGA SPI MISO NET 'FPGA_BANK_3_SPI_MOSI' U1-H8 R1255-1 # FPGA SPI MOSI TO TERM RES NET 'FPGA_BOOT_MUX_FPGA_MOSI' U1252-6 R1255-2 # TERM RES TO FPGA BOOT MEM MUX. NET 'FPGA_BANK_3_SPI_SCK' U1-J8 R1256-1 # FPGA SPI SCK TO TERM RES NET 'FPGA_BOOT_MUX_FPGA_SCK' U1252-8 R1256-2 # TERM RES TO FPGA BOOT MEM MUX. # # MULTIPLEXER TO/FROM ER UPROCESSOR: # --------------------------------------- # NET 'RESCUE_PIO_0_21_SPI_SSEL0' U1252-17 # ER UPROC SPI SEL_B TO FPGA BOOT MEM MUX. NET 'FPGA_BOOT_MUX_ER_MISO' U1252-5 R1251-2 # SPI MISO FROM MUX TO TERM RES NET 'RESCUE_PIO_0_22_SPI_MISO' R1251-1 # TERM RES TO ER UPROC SPI MISO NET 'RESCUE_PIO_0_23_SPI_MOSI' R1252-1 # ER UPROC SPI MOSI TO TERM RES NET 'FPGA_BOOT_MUX_ER_MOSI' U1252-13 R1252-2 # TERM RES TO FPGA BOOT MEM MUX. NET 'RESCUE_PIO_0_14_SPI_SCK' R1253-1 # ER UPROC SPI SCK TO TERM RES NET 'FPGA_BOOT_MUX_ER_SCK' U1252-11 R1253-2 # TERM RES TO FPGA BOOT MEM MUX. NET 'ER_CONTROLS_BOOT_SPI' U1252-1 U1252-19 # CONTROL SIGNAL FROM ER UPROCESSOR # HW LOGIC HI ---> ER TAKES CONTROL # OF THE FPGA BOOT MEMORY SPI BUS # # PULL-UP & PULL-DOWN RESISTORS FOR FPGA BOOT MEMORY CLOCK SIGNAL: # -------------------------------------------------------------------- # NET 'FPGA_BOOT_MEM_CLOCK' R1261-2 R1262-2 # FPGA BOOT MEM CLOCK / SCLK NET 'BULK_3V3' R1261-1 # PULL-UP 3V3 SOURCE NET 'GROUND' R1262-1 # PULL-DOWN ANCHOR # # PULL-UP RESISTORS ON THE FPGA BOOT MEMORY: # ----------------------------====-------------- # NET 'FPGA_BOOT_MEM_DQ3_HOLD_B' U1251-1 R1257-2 # FPGA BOOT MEMORY DQ3/HOLD_B PIN NET 'FPGA_BOOT_MEM_RESET_B' U1251-3 R1258-2 # FPGA BOOT MEMORY RESET_B PIN NET 'FPGA_BOOT_MEM_DQ2_W_B' U1251-9 R1259-1 # FPGA BOOT MEMORY DQ2/W_B PIN NET 'BULK_3V3' R1257-1 R1258-1 R1259-2 # PULL-UP 3V3 SOURCE NET 'FPGA_BOOT_MEM_SELECT_B' R1260-2 # FPGA BOOT MEMORY SELECT_B PIN NET 'BULK_3V3' R1260-1 # PULL-UP 3V3 SOURCE # # 3.3 VOLT POWER AND GROUNDS TO THE FPGA BOOT MEMORY & MULTIPLEXER CHIP: # ------------------------------------===------------------------------------ # NET 'BULK_3V3' C1251-1 C1252-2 C1253-1 C1254-2 # 3V3 BYPASS CAPS NET 'GROUND' C1251-2 C1252-1 C1253-2 C1254-1 # GROUND SIDE OF BYPASS CAPS NET 'BULK_3V3' U1251-2 U1252-20 # 3V3 POWER TO THE FPGA BOOT & MUX NET 'GROUND' U1251-10 U1252-10 # GROUND TO THE FPGA BOOT & MUX # # FPGA BOOT MEMORY NO_CONNECT PINS: # -====------------------------------- # NET 'NO_CONN_FPGA_BOOT_MEM_PIN_4' U1251-4 # NO CONN U1201 PIN 4 NET 'NO_CONN_FPGA_BOOT_MEM_PIN_5' U1251-5 # NO CONN U1201 PIN 5 NET 'NO_CONN_FPGA_BOOT_MEM_PIN_6' U1251-6 # NO CONN U1201 PIN 6 NET 'NO_CONN_FPGA_BOOT_MEM_PIN_11' U1251-11 # NO CONN U1201 PIN 11 NET 'NO_CONN_FPGA_BOOT_MEM_PIN_12' U1251-12 # NO CONN U1201 PIN 12 NET 'NO_CONN_FPGA_BOOT_MEM_PIN_13' U1251-13 # NO CONN U1201 PIN 13 NET 'NO_CONN_FPGA_BOOT_MEM_PIN_14' U1251-14 # NO CONN U1201 PIN 14 # # BANK #3 DEFAULT OPERATION PULL-UP RESISTORS # ------------------------------------------------- # NET 'BANK_3_FF_EXIT_N' U1-J13 R1351-2 # PULL-UP FF_EXIT_N NET 'BANK_3_IO_CFG_INTF' U1-H13 R1352-2 # PULL-UP IO_CFG_INTF NET 'BANK_3_SPI_EN' U1-K12 R1353-2 # PULL-UP SPI_EN NET 'BULK_3V3' R1351-1 R1352-1 R1353-1 # PULL-UP 3V3 SOURCE # # INTERPOSER ALL SPI NETS # ------------------------------ # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # INITIAL REV. 30-NOV-2023 # CURRENT REV. 21-DEC-2023 # # # # THIS NET LIST HOLDS THE INTERPOSER ALL SPI NETS # ---------------------------- # # THE COMPONENTS FOR THE # DK'S INTERPOSER ALL SPI NETS # ARE IN THE RANGE 1451 TO 1499. # # # NOTE: THAT 2 SECTIONS OF THE U1459 HEX INVERTER, WHICH # OFFICIALLY BELONGS TO THE INTERPOSER_ALL_OTHER NET # LIST FILE WHERE IS IS USED TO HANDLE THE MUON SMUT SIGNALS, # IS USED IN THIS NET LIST FILE TO HANDLE INVERTING THE # INTERPOSER SPI MUX CONTROL SIGNALS. # # # SPI SIGNALS MUX TO INTERPOSER #1 CONNECTOR J4: # --------------------------------------------------- # NET 'POSER_1_CONN_SCLK' R1453-2 # SCLK SERIES TERM TO POSER #1 CONN NET 'POSER_1_DRV_SCLK' U1451-18 R1453-1 R1461-1 # SCLK DRIVER TO SER TERM & PULL_DWN NET 'POSER_1_CONN_MOSI' R1454-2 # MOSI SERIES TERM TO POSER #1 CONN NET 'POSER_1_DRV_MOSI' U1451-16 R1454-1 R1462-1 # MOSI DRIVER TO SER TERM & PULL_DWN NET 'POSER_1_CONN_MISO' U1451-6 R1463-2 # MISO POSER #1 CONN TO PULL-DOWN & RECEIVER NET 'POSER_1_CONN_CS_B' U1451-12 R1481-2 # CS_B DRIVER & PULL-UP TO POSER #1 CONN NET 'POSER_1_CONN_CS_A0' U1451-9 R1464-2 # CS_A0 DRIVER & PULL-UP TO POSER #1 CONN NET 'POSER_1_CONN_CS_A1' U1451-7 R1465-2 # CS_A1 DRIVER & PULL-UP TO POSER #1 CONN NET 'POSER_1_CONN_CS_A2' U1451-5 R1466-2 # CS_A2 DRIVER & PULL-UP TO POSER #1 CONN NET 'BULK_3V3' R1481-1 # PULL-UP SOURCE NET 'GROUND' R1461-2 R1462-2 R1463-1 # PULL-DOWN ANCHOR NET 'GROUND' R1464-1 R1465-1 R1466-1 # PULL-DOWN ANCHOR # # SPI SIGNALS MUX TO INTERPOSER #2 CONNECTOR J5: # --------------------------------------------------- # NET 'POSER_2_CONN_SCLK' R1455-2 # SCLK SERIES TERM TO POSER #2 CONN NET 'POSER_2_DRV_SCLK' U1452-18 R1455-1 R1467-1 # SCLK DRIVER TO SER TERM & PULL_DWN NET 'POSER_2_CONN_MOSI' R1456-2 # MOSI SERIES TERM TO POSER #2 CONN NET 'POSER_2_DRV_MOSI' U1452-16 R1456-1 R1468-1 # MOSI DRIVER TO SER TERM & PULL_DWN NET 'POSER_2_CONN_MISO' U1452-6 R1469-2 # MISO POSER #2 CONN TO PULL-DOWN & RECEIVER NET 'POSER_2_CONN_CS_B' U1452-12 R1482-2 # CS_B DRIVER & PULL-UP TO POSER #2 CONN NET 'POSER_2_CONN_CS_A0' U1452-9 R1470-2 # CS_A0 DRIVER & PULL-UP TO POSER #2 CONN NET 'POSER_2_CONN_CS_A1' U1452-7 R1471-2 # CS_A1 DRIVER & PULL-UP TO POSER #2 CONN NET 'POSER_2_CONN_CS_A2' U1452-5 R1472-2 # CS_A2 DRIVER & PULL-UP TO POSER #2 CONN NET 'BULK_3V3' R1482-1 # PULL-UP SOURCE NET 'GROUND' R1467-2 R1468-2 R1469-1 # PULL-DOWN ANCHOR NET 'GROUND' R1470-1 R1471-1 R1472-1 # PULL-DOWN ANCHOR # # SPI SIGNALS FPGA TO/FROM MULTIPLEXER: # -------------------------------------------- # NET 'POSER_SCLK_FPGA_TO_TERM' R1451-1 # SCLK FPGA TO SERIES TERM NET 'POSER_SCLK_TERM_TO_MUX' R1451-2 U1451-2 U1452-2 # SCLK SERIES TERM TO MUX NET 'POSER_MOSI_FPGA_TO_TERM' R1452-1 # MOSI FPGA TO SERIES TERM NET 'POSER_MOSI_TERM_TO_MUX' R1452-2 U1451-4 U1452-4 # MOSI SERIES TERM TO MUX NET 'POSER_MISO_MUX_TO_TERM' U1451-14 U1452-14 R1457-1 # MISO MUX TO TERM NET 'POSER_MISO_MUX_TO_TERM' R1473-1 # MISO MUX TO PULL-DWN NET 'POSER_MISO_TERM_TO_FPGA' R1457-2 # MISO MUX TERM TO FPGA NET 'GROUND' R1473-2 # PULL-DOWN ANCHOR # # MUX CONTROL SIGNALS FPGA TO MULTIPLEXER (VIA AN INVERTER WHERE NECESSARY): # --------------------------------------------------------------------------------- # # NOTE: THE USE OF HEX INVERTER U1459 TO HANDLE THE INVERSION # OF THE SPI MUX CONTROL SIGNALS. HEX INVERTER U1459 # OFFICIALLY BELONGS TO THE INTERPOSER ALL OTHER NET LIST # FILE WHERE IT HANDLES MUON SMUT SIGNALS. # NET 'POSER_CS_1_B' U1451-1 U1459-1 # FPGA TO ENABLE ONE HALF INTERPOSER #1 MUX _B NET 'POSER_CS_1' U1459-2 U1451-19 # INVERTER TO ENABLE OTHER HALF INTERPOSER #1 MUX NET 'POSER_CS_2_B' U1452-1 U1459-13 # FPGA TO ENABLE ONE HALF INTERPOSER #2 MUX _B NET 'POSER_CS_2' U1459-12 U1452-19 # INVERTER TO ENABLE OTHER HALF INTERPOSER #2 MUX # # CS ADDRESS SIGNALS FPGA TO MULTIPLEXER: # --------------------------------------------- # NET 'POSER_CS_ADRS_0' U1451-11 U1452-11 # CS ADDRESS 0 FPGA TO MUX NET 'POSER_CS_ADRS_1' U1451-13 U1452-13 # CS ADDRESS 1 FPGA TO MUX NET 'POSER_CS_ADRS_2' U1451-15 U1452-15 # CS ADDRESS 2 FPGA TO MUX # # TIE-DOWN ALL UNUSED CMOS INPUTS: # -------------------------------------- # NET 'GROUND' U1451-17 U1452-17 # TIE-DOWN THE INPUT TO THE # UNUSED SECTION OF THE MUX # # LIST THE NETNAMES OF THE SIGNALS THAT MUST BE # CONNECTED TO FPGA FLOATING PINS. HERE JUST LIST # THE NETNAMES - THE ACTUAL CONNECTIONS TO THESE # FPGA FLOATING PINS ARE MADE IN THE NETS FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # ---------------------------------------------------- # # # ALL OF THESE ARE 3V3 SIGNALS: SPI BUS AND GPIO # ------------------------------------------------- # # NET 'POSER_SCLK_FPGA_TO_TERM' # SCLK FPGA TO SERIES TERM # NET 'POSER_MOSI_FPGA_TO_TERM' # MOSI FPGA TO SERIES TERM # NET 'POSER_MISO_TERM_TO_FPGA' # MISO MUX TERM TO FPGA # # NET 'POSER_CS_1_B' # FPGA SIGNAL TO ENABLE INTERPOSER #1 MUX _B # NET 'POSER_CS_2_B' # FPGA SIGNAL TO ENABLE INTERPOSER #2 MUX _B # # NET 'POSER_CS_ADRS_0' # CS ADDRESS 0 FPGA TO MUX # NET 'POSER_CS_ADRS_1' # CS ADDRESS 1 FPGA TO MUX # NET 'POSER_CS_ADRS_2' # CS ADDRESS 2 FPGA TO MUX # # # 3.3 VOLT POWER AND GROUNDS TO THE INTERPOSER SPI BUFFE CHIPS: # ------------------------------------------------------------------ # NET 'BULK_3V3' U1451-20 U1452-20 # 3V3 POWER TO THE BUFFER CHIPS NET 'GROUND' U1451-10 U1452-10 # GROUND PINS ON THE BUFFER CHIPS NET 'BULK_3V3' C1451-2 C1452-2 # 3V3 BYPASS CAPS NET 'GROUND' C1451-1 C1452-1 # GROUND SIDE OF BYPASS CAPS # # INTERPOSER ALL OTHER NETS # -------------===========------- # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # INITIAL REV. 4-DEC-2023 # CURRENT REV. 27-DEC-2023 # # # # THIS NET LIST HOLDS THE INTERPOSER ALL OTHER NETS # ------------===========----- # # THE COMPONENTS FOR THE # DK'S INTERPOSER ALL OTHER NETS # ARE IN THE RANGE 1451 TO 1499. # # # NOTE: THAT 2 SECTIONS OF THE U1459 HEX INVERTER, WHICH # IS SHOWN LOWER IN THIS FILE, ARE USED IN A DIFFERENT # NET LIST FILE TO HANDLE THE INTERPOSER SPI MUX CONTROL # SIGNALS. # # # PIEZO HYDROPHONE CONNECTION TO THE BB AUDIO ADC INPUTS # ----------------------------------------------------------- # # THIS CONNECTION IS MADE IN THE: # # INTERPOSER_CONNECTORS_ALL_NETS.TXT # AND THE BB_AUDIO_ADC_NETS.TXT FILES. # # # NETS FOR THE INTERPOSER 1V8 UART BUFFERS: # ------------------------------------------------- # # INTERPOSER #1 SERVICED BY CPU MMUART #3 # --------------------------------------------- NET 'CPU_UART_3_TX__TO__POSER_1' R1483-1 # DK CPU UART 3 TX DATA TO TERMINATOR NET 'TX_TO_POSER_1_TERM_BUF' R1483-2 U1454-3 # DK CPU UART TX DATA TO DATA BUFFER NET 'CPU_UART_TX_TO_POSER_1_B' U1454-4 U1454-5 # INVERTED NET 'DATA_TO_POSER_1_BUF_TERM' U1454-6 R1484-1 # TX DATA TO THE DK TX TERMINATOR NET 'DK_TX_DATA_TO_POSER_1' R1484-2 J4-31 # TX DATA TO THE POSER_1 CONNECTOR NET 'DK_RX_DATA_FROM_POSER_1' J4-32 U1454-11 # RX DATA FROM THE POSER_1 CONNECTOR NET 'DK_RX_DATA_FROM_POSER_1_B' U1454-10 U1454-9 # INVERTED NET 'DK_RX_DATA_PSR_1_TO_TERM' U1454-8 R1485-1 # RX DATA FROM THE POSER_1 TO TERM NET 'CPU_UART_3_RX_FROM_POSER_1' R1485-2 # RX DATA FROM THE POSER_1 VIA BUF # AND TERM TO THE DK'S CPU UART #3 NET 'GROUND' U1454-1 U1454-13 # TIE DOWN UNUSED BUFFER INPUTS NET 'BULK_1V8' U1454-14 C1454-1 # 1V8 POWER FOR UART BUFFER NET 'GROUND' U1454-7 C1454-2 # GROUND FOR THE UART BUFFER # INTERPOSER #2 SERVICED BY CPU MMUART #4 # --------------------------------------------- NET 'CPU_UART_4_TX__TO__POSER_2' R1486-1 # DK CPU UART 4 TX DATA TO TERMINATOR NET 'TX_TO_POSER_2_TERM_BUF' R1486-2 U1455-3 # DK CPU UART TX DATA TO DATA BUFFER NET 'CPU_UART_TX_TO_POSER_2_B' U1455-4 U1455-5 # INVERTED NET 'DATA_TO_POSER_2_BUF_TERM' U1455-6 R1487-1 # TX DATA TO THE DK TX TERMINATOR NET 'DK_TX_DATA_TO_POSER_2' R1487-2 J5-31 # TX DATA TO THE POSER_2 CONNECTOR NET 'DK_RX_DATA_FROM_POSER_2' J5-32 U1455-11 # RX DATA FROM THE POSER_2 CONNECTOR NET 'DK_RX_DATA_FROM_POSER_2_B' U1455-10 U1455-9 # INVERTED NET 'DK_RX_DATA_PSR_2_TO_TERM' U1455-8 R1488-1 # RX DATA FROM THE POSER_2 TO TERM NET 'CPU_UART_4_RX_FROM_POSER_2' R1488-2 # RX DATA FROM THE POSER_2 VIA BUF # AND TERM TO THE DK'S CPU UART #4 NET 'GROUND' U1455-1 U1455-13 # TIE DOWN UNUSED BUFFER INPUTS NET 'BULK_1V8' U1455-14 C1455-1 # 1V8 POWER FOR UART BUFFER NET 'GROUND' U1455-7 C1455-2 # GROUND FOR THE UART BUFFER # # FLASH-NOW SIGNAL FROM FPGA/CPU TO BOTH INTERPOSERS AND TO THE AD9546 TG: # ---------------------------------------------------------------------------------- # NET 'FLASH_NOW' R1490-2 R1491-2 # FLASH_NOW SIGNAL FROM THE FPGA/CPU # THIS IS A 3V3 CMOS SINGLE ENDED SIGNAL # FROM A "FLOATING" PIN ON THE FPGA/CPU # TO A PAIR OF SERIES TERMINATORS. NET 'TG_AUX_IN_M1' R1490-1 # FLASH_NOW FROM THE FPGA/CPU TO THE "M1" AUXILIARY INPUT # OF THE AD9546 TIMING GENERATOR FOR TIMING MEASUREMENT. NET 'FLASH_NOW_TO_INTERPOSERS' R1491-1 # FLASH_NOW FROM SERIES TERMINATOR NET 'FLASH_NOW_TO_INTERPOSERS' U1456-5 U1457-5 # TO THE LVDS FLASH NOW DRIVERS INPUTS NET 'POSER_1_FLASH_NOW_DIR' U1456-4 J4-7 # FLASH NOW DIR TO THIS HEMISPHERE NET 'POSER_1_FLASH_NOW_CMP' U1456-3 J4-8 # FLASH NOW CMP TO THIS HEMISPHERE NET 'POSER_2_FLASH_NOW_DIR' U1457-4 J5-7 # FLASH NOW DIR TO OTHER HEMISPHERE NET 'POSER_2_FLASH_NOW_CMP' U1457-3 J5-8 # FLASH NOW CMP TO OTHER HEMISPHERE NET 'BULK_3V3' U1456-1 U1457-1 # BULK_3V3 TO THE LVDS DRIVER CHIPS NET 'GROUND' U1456-2 U1457-2 # GROUND TO THE LVDS DRIVER CHIPS NET 'BULK_3V3' C1481-1 C1482-2 C1483-2 # BULK_3V3 TO THE BYPASS CAPS NET 'GROUND' C1481-2 C1482-1 C1483-1 # GROUND TO THE BYPASS CAPS # # FLASH-TDC SIGNALS FROM BOTH INTERPOSERS TO THE AD9546 FOR TIMING MEASUREMENT: # ---------------------------------------------------------------------------------------- # NET 'POSER_1_FLASH_TDC_IN' J4-15 U1458-3 # FLASH TDC INPUT FROM THIS HEMISPHERE NET 'POSER_1_FLASH_TDC_LINK' U1458-4 U1458-5 # FLASH TDC BUF LINK THIS HEMISPHERE NET 'POSER_1_FLASH_TDC_TERM' U1458-6 R1493-1 # FLASH TDC BUF TERM THIS HEMISPHERE NET 'TG_AUX_IN_M2' R1493-2 # FLASH TDC FROM THIS HEMISPHERE TO THE # "M2" INPUT OF THE AD9546 TIMING GENERATOR # FOR TIME MEASUREMENT A 3V3 CMOS SIGNAL NET 'POSER_2_FLASH_TDC_IN' J5-15 U1458-11 # FLASH TDC INPUT FROM OTHER HEMISPHERE NET 'POSER_2_FLASH_TDC_LINK' U1458-10 U1458-9 # FLASH TDC BUS LINK OTHER HEMISPHERE NET 'POSER_2_FLASH_TDC_TERM' U1458-8 R1492-1 # FLASH TDC BUF TERM OTHER HEMISPHERE NET 'TG_AUX_IN_M3' R1492-2 # FLASH TDC FROM OTHER HEMISPHERE TO THE # "M3" INPUT OF THE AD9546 TIMING GENERATOR # FOR TIME MEASUREMENT A 3V3 CMOS SIGNAL NET 'BULK_3V3' U1458-14 C1484-2 # BULK_3V3 TO THE BUFFER AND BYPASS CAPS NET 'GROUND' U1458-7 C1484-1 # GROUND TO THE BUFFER AND BYPASS CAPS # # INTERPOSER CONTROLLER RESET FROM FPGA/CPU TO BOTH INTERPOSERS: # ---------------------------------------------------------------------------- # NET 'INTERPOSER_CTRL_RESET' R1494-2 # INTERPOSER CTRL RESET FROM FPGA/CPU NET 'POSER_RESET_TERM_TO_BUF' R1494-1 U1458-1 U1458-13 # SERIES TERM TO BUFFER INPUTS NET 'POSER_1_CTRL_RESET' U1458-2 J4-19 # CONTROL RESET TO INTERPOSER THIS HEMISPHERE NET 'POSER_2_CTRL_RESET' U1458-12 J5-19 # CONTROL RESET TO INTERPOSER OTHER HEMISPHERE # # MUON SMUT S1 S2 S3 S4 SIGNALS FROM OTHER HEMISHPERE TO THE FPGA/CPU "TDCS": # --------------------------------------------------------------------------------------- # # # NOTE: THAT MOST OF THE U1459 HEX INVERTER IS USED BY THE # FOLLOWING MUON SMUT SIGNALS BUT 2 SECTIONS OF THE # U1459 HEX INVERTER ARE USED IN A DIFFERENT NET LIST # FILE TO HANDLE THE INTERPOSER SPI MUX CONTROL LINES. # NET 'SMUT_S1_OTHER_HEMI' J5-33 U1459-3 # MUON SMUT SIGNAL S1 FROM OTHER HEMISPHERE NET 'SMUT_S2_OTHER_HEMI' J5-35 U1459-5 # MUON SMUT SIGNAL S2 FROM OTHER HEMISPHERE NET 'SMUT_S3_OTHER_HEMI' J5-36 U1459-9 # MUON SMUT SIGNAL S3 FROM OTHER HEMISPHERE NET 'SMUT_S4_OTHER_HEMI' J5-37 U1459-11 # MUON SMUT SIGNAL S4 FROM OTHER HEMISPHERE NET 'MUON_S1_OTHER_TERM' U1459-4 R1498-1 # SMUT MUON S1 OTHER HEMI TO TERM --> FPGA/CPU "TDC" NET 'MUON_S2_OTHER_TERM' U1459-6 R1497-1 # SMUT MUON S2 OTHER HEMI TO TERM --> FPGA/CPU "TDC" NET 'MUON_S3_OTHER_TERM' U1459-8 R1496-1 # SMUT MUON S3 OTHER HEMI TO TERM --> FPGA/CPU "TDC" NET 'MUON_S4_OTHER_TERM' U1459-10 R1495-1 # SMUT MUON S4 OTHER HEMI TO TERM --> FPGA/CPU "TDC" NET 'MUON_S1_OTHER_HEMI' R1498-2 # SMUT MUON S1 OTHER HEMI TO FPGA/CPU "TDC" NET 'MUON_S2_OTHER_HEMI' R1497-2 # SMUT MUON S2 OTHER HEMI TO FPGA/CPU "TDC" NET 'MUON_S3_OTHER_HEMI' R1496-2 # SMUT MUON S3 OTHER HEMI TO FPGA/CPU "TDC" NET 'MUON_S4_OTHER_HEMI' R1495-2 # SMUT MUON S4 OTHER HEMI TO FPGA/CPU "TDC" NET 'NO_CONN_THIS_HEMI_SMUT_S1_J4_PIN_33' J4-33 # NO SMUT S1 IN THIS HEMISPHERE NET 'NO_CONN_THIS_HEMI_SMUT_S2_J4_PIN_35' J4-35 # NO SMUT S2 IN THIS HEMISPHERE NET 'NO_CONN_THIS_HEMI_SMUT_S3_J4_PIN_36' J4-36 # NO SMUT S3 IN THIS HEMISPHERE NET 'NO_CONN_THIS_HEMI_SMUT_S4_J4_PIN_37' J4-37 # NO SMUT S4 IN THIS HEMISPHERE NET 'BULK_3V3' U1459-14 C1485-2 # BULK_3V3 TO THE BUFFER AND BYPASS CAPS NET 'GROUND' U1459-7 C1485-1 # GROUND TO THE BUFFER AND BYPASS CAPS # # POWER FEEDS TO THE INTERPOSERS - ISOLATION FILTERS AND BYPASS CAPACITORS # ---------------------------------------------------------------------------- # # POSER #1 1V8 POWER # --------------------- NET 'BULK_1V8' C1461-2 L1461-1 # BULK_1V8 FEED TO THE FILTER NET 'POSER_1_1V8' C1462-2 L1461-2 J4-1 J4-2 # POSER #1 1V8 POWER NET 'GROUND' C1461-1 C1462-1 # GROUND ANCHOR FOR THE CAPS # POSER #1 3V3 POWER # --------------------- NET 'BULK_3V3' C1463-2 L1462-1 # BULK_3V3 FEED TO THE FILTER NET 'POSER_1_3V3' C1464-2 L1462-2 J4-3 J4-4 # POSER #1 3V3 POWER NET 'GROUND' C1463-1 C1464-1 # GROUND ANCHOR FOR THE CAPS # POSER #1 5V0 POWER # --------------------- NET 'BULK_5V0' C1465-2 L1463-1 # BULK_5V0 FEED TO THE FILTER NET 'POSER_1_5V0' C1466-1 L1463-2 J4-39 J4-40 # POSER #1 5V0 POWER NET 'GROUND' C1465-1 C1466-2 # GROUND ANCHOR FOR THE CAPS # POSER #2 1V8 POWER # --------------------- NET 'BULK_1V8' C1471-2 L1471-1 # BULK_1V8 FEED TO THE FILTER NET 'POSER_2_1V8' C1472-1 L1471-2 J5-1 J5-2 # POSER #2 1V8 POWER NET 'GROUND' C1471-1 C1472-2 # GROUND ANCHOR FOR THE CAPS # POSER #2 3V3 POWER # --------------------- NET 'BULK_3V3' C1473-2 L1472-1 # BULK_3V3 FEED TO THE FILTER NET 'POSER_2_3V3' C1474-1 L1472-2 J5-3 J5-4 # POSER #2 3V3 POWER NET 'GROUND' C1473-1 C1474-2 # GROUND ANCHOR FOR THE CAPS # POSER #2 5V0 POWER # --------------------- NET 'BULK_5V0' C1475-2 L1473-1 # BULK_5V0 FEED TO THE FILTER NET 'POSER_2_5V0' C1476-2 L1473-2 J5-39 J5-40 # POSER #2 5V0 POWER NET 'GROUND' C1475-1 C1476-1 # GROUND ANCHOR FOR THE CAPS # # LIST THE NETNAMES OF THE SIGNALS THAT MUST BE # CONNECTED TO FPGA FLOATING PINS. HERE JUST LIST # THE NETNAMES - THE ACTUAL CONNECTIONS TO THESE # FPGA FLOATING PINS ARE MADE IN THE NETS FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # ---------------------------------------------------- # # # ALL OF THESE ARE 1V8 SIGNALS: CPU UART DATA TO/FROM BOTH INTERPOSERS # ---------------------------------------------------------------------------- # # NET 'CPU_UART_TX__TO__POSER_1' # TX UART DATA TO INTERPOSER_1 VIA BUFFER # NET 'CPU_UART_RX_FROM_POSER_1' # RX UART DATA FROM INTERPOSER_1 VIA BUFFER # # NET 'CPU_UART_TX__TO__POSER_2' # TX UART DATA TO INTERPOSER_2 VIA BUFFER # NET 'CPU_UART_RX_FROM_POSER_2' # RX UART DATA FROM INTERPOSER_2 VIA BUFFER # # # # ALL OF THESE ARE 3V3 SIGNALS: FLASH-NOW TO BOTH INTERPOSERS AND TO AD9546 # CONTROL-RESET TO BOTH INTERPOSERS # SMUT S1...S4 FROM ONLY OTHER INTERPOSER TO FPGA # ------------------------------------------------------------------------------------- # # NET 'FLASH_NOW' # FLASH_NOW FROM THE FPGA/CPU TO BOTH # # INTERPOSERS AND TO THE AD9546 FOR # # TIME MEASUREMENT A 3V3 CMOS SIGNAL # # NET 'INTERPOSER_CTRL_RESET' # CONTROL RESET TO BOTH INTERPOSERS FROM FPGA/CPU # # NET 'MUON_S1_OTHER_HEMI' # MUON SMUT SIGNAL S1 FROM OTHER HEMISPHERE TO FPGA/CPU # NET 'MUON_S2_OTHER_HEMI' # MUON SMUT SIGNAL S2 FROM OTHER HEMISPHERE TO FPGA/CPU # NET 'MUON_S3_OTHER_HEMI' # MUON SMUT SIGNAL S3 FROM OTHER HEMISPHERE TO FPGA/CPU # NET 'MUON_S4_OTHER_HEMI' # MUON SMUT SIGNAL S4 FROM OTHER HEMISPHERE TO FPGA/CPU # # # INTERPOSER CONNECTORS J4 & J5 ALL NETS # ------------------------------------------- # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # INITIAL REV. 30-NOV-2023 # CURRENT REV. 14-DEC-2023 # # # # THIS NET LIST HOLDS THE INTERPOSER CONNECTORS J4 & J5 ALL NETS # ------------------------------------------- # # # # # FROM ADAM'S DRAWING FROM 20-OCT-2023: 87833-4020 # # # 1 1V8 2 1V8 # 3 3V3 4 3V3 # 5 GND 6 GND # 7 FLASH_PULSE_P 8 FLASH_PULSE_N # 9 GND 10 GND # # 11 PIEZO_P 12 PIEZO_N # 13 GND 14 GND # 15 FLASH_TDC 16 GND # 17 GND 18 SPI_CLK # 19 CTRL_RST 20 SPI_MISO # # 21 GND 22 SPI_MOSI # 23 A0 24 SPI_CS # 25 GND 26 GND # 27 A2 28 A1 # 29 GND 30 GND # # 31 UART_TX 32 UART-RX # 33 SMUT_S1 34 GND # 35 SMUT_S2 36 SMUT_S3 # 37 SMUT_S4 38 GND # 39 5V0 40 5V0 # # # SPI SIGNALS TO INTERPOSER #1 J4 THIS HEMISPHERE: # ---------------------------------------------------------------- # NET 'POSER_1_CONN_SCLK' J4-18 # SPI CLK TO INTERPOSER #1 PIN 18 NET 'POSER_1_CONN_MOSI' J4-22 # SPI MOSI TO INTERPOSER #1 PIN 22 NET 'POSER_1_CONN_MISO' J4-20 # SPI MISO FROM INTERPOSER #1 PIN 20 NET 'POSER_1_CONN_CS_B' J4-24 # SPI CS_B TO INTERPOSER #1 PIN 24 # # ADDRESS SIGNALS TO INTERPOSER #1 J4 THIS HEMISPHERE: # ------------------------------------------------------------ # NET 'POSER_1_CONN_CS_A0' J4-23 # CS_A0 TO POSER #1 CONN PIN 23 NET 'POSER_1_CONN_CS_A1' J4-28 # CS_A1 TO POSER #1 CONN PIN 28 NET 'POSER_1_CONN_CS_A2' J4-27 # CS_A2 TO POSER #1 CONN PIN 27 # # SPI SIGNALS TO INTERPOSER #2 J5 OTHER HEMISPHERE: # ----------------------------------------------------------------- # NET 'POSER_2_CONN_SCLK' J5-18 # SPI CLK TO INTERPOSER #2 PIN 18 NET 'POSER_2_CONN_MOSI' J5-22 # SPI MOSI TO INTERPOSER #2 PIN 22 NET 'POSER_2_CONN_MISO' J5-20 # SPI MISO FROM INTERPOSER #2 PIN 20 NET 'POSER_2_CONN_CS_B' J5-24 # SPI CS_B TO INTERPOSER #2 PIN 24 # # ADDRESS SIGNALS TO INTERPOSER #2 J5 OTHER HEMISPHERE: # ------------------------------------------------------------- # NET 'POSER_2_CONN_CS_A0' J5-23 # CS_A0 TO POSER #2 CONN PIN 23 NET 'POSER_2_CONN_CS_A1' J5-28 # CS_A1 TO POSER #2 CONN PIN 28 NET 'POSER_2_CONN_CS_A2' J5-27 # CS_A2 TO POSER #2 CONN PIN 27 # # PIEZO INPUT SIGNALS TO BB AUDIO ADC FOR INTERPOSER #1 & #2: # ----------------------------------------------------------------- # NET 'INTERPOSER_1_AUDIO_DIR' J4-11 # INTERPOSER #1 AUDIO SIGNAL DIR AKA PIEZO_P NET 'INTERPOSER_1_AUDIO_CMP' J4-12 # INTERPOSER #1 AUDIO SIGNAL CMP AKA PIEZO_N NET 'INTERPOSER_2_AUDIO_DIR' J5-11 # INTERPOSER #2 AUDIO SIGNAL DIR AKA PIEZO_P NET 'INTERPOSER_2_AUDIO_CMP' J5-12 # INTERPOSER #2 AUDIO SIGNAL CMP AKA PIEZO_N # # GROUND PINS ON THE INTERPOSER CONNECTORS: # ------------------------------------------- # NET 'GROUND' J4-5 J4-6 J4-9 J4-10 # GROUNDS ON J4 NET 'GROUND' J4-13 J4-14 J4-16 J4-17 # GROUNDS ON J4 NET 'GROUND' J4-21 J4-25 J4-26 J4-29 # GROUNDS ON J4 NET 'GROUND' J4-30 J4-34 J4-38 # GROUNDS ON J4 NET 'GROUND' J5-5 J5-6 J5-9 J5-10 # GROUNDS ON J5 NET 'GROUND' J5-13 J5-14 J5-16 J5-17 # GROUNDS ON J5 NET 'GROUND' J5-21 J5-25 J5-26 J5-29 # GROUNDS ON J5 NET 'GROUND' J5-30 J5-34 J5-38 # GROUNDS ON J5 # # CRYSTAL OSCILLATORS # ----------------------- # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # INITIAL REV. 6-DEC-2022 # CURRENT REV. 12-DEC-2023 # # # THIS NET LIST HOLDS THE CRYSTAL OSCILLATORS # AND THEIR CONNECTIONS TO THE DK FPGA/CPU. # # # THE COMPONENTS FOR THE CRYSTAL OSCILLATORS # ARE IN THE RANGE 1501 TO 1549. # # # CURRENTLY (12-DEC-2023) IT IS ASSUMED THAT: # # - XTAL #1 WILL BE INSTALLED AND WILL BE 125 MHZ # # - XTAL #1 WILL PROVIDE ITS SIGNAL TO BOTH: # - THE PREFERED MSS_REF_CLK_IN P11, R11 IN BANK #5 AND # - XCVR_0A_REF_CLK_IN PINS R23, R24 IN THE XCVR_0 SECTION # # NOTE: FOR THIS DOUBLE LOAD TO WORK WE MUST BE # ABLE TO TURN OFF THE TERMINATOR IN ONE OF # THE TWO LOADS. THE 100 OHM TERMINATOR IN THE # XCVR REF CLOCK 0A INPUT CAN BE SET TO OPEN CIRCUIT. # # # - XTAL #2 IS A SPARE AND WILL NOT BE INSTALLED # # - XTAL #2 IS WIRED TO A PREFERED CCC CLOCK INPUT # IN BANK #7 CCC_SW_CLK_IN_W_0 AKA # GPIO_167P_B7 / CLKIN_W_0 G5,G4 # # # FOR REFERENCE: CURRENTLY (7-DEC-2023) THE OTHER CLOCKS THAT ARE # PROVIDED TO THE FPGA/CPU COME FROM THE AD9546 # TIMING GENERATOR AND ARE: # # TIME GEN OUTPUT 1A TO XCVR_1A_REF_CLK_IN L23, L24 JESD CLOCK # # TIME GEN OUTPUT 1B TO CCC_SE_CLK_IN_S_9 J14, H14 A SPARE CLK # GPIO11PB1/CLKIN_S_9 BANK #1 # # # CRYSTAL OSCILLATORS LVDS OUTPUTS TO THE FPGA/CPU: # ------------------------------------------------------- # NET 'XTAL_1_OUTPUT_DIR' Y1501-4 U1-P11 # XTAL #1 OUTPUT DIR TO # MSS_REF_CLK_IN_P NET 'XTAL_1_OUTPUT_CMP' Y1501-5 U1-R11 # XTAL #1 OUTPUT CMP TO # MSS_REF_CLK_IN_N # XTAL #1 ALSO FEEDS (BUT ONLY ONE CAN BE TERMINATED): NET 'XTAL_1_OUTPUT_DIR' U1-R23 # XTAL #1 OUTPUT DIR TO # XCVR_0A_REF_CLK_IN_P NET 'XTAL_1_OUTPUT_CMP' U1-R24 # XTAL #1 OUTPUT CMP TO # XCVR_0A_REF_CLK_IN_N NET 'XTAL_2_OUTPUT_DIR' Y1502-4 U1-G5 # XTAL #2 OUTPUT DIR TO # GPIO_167P_B7 / CLKIN_W_0 / CCC_SW_CLKIN_W_O NET 'XTAL_2_OUTPUT_CMP' Y1502-5 U1-G4 # XTAL #2 OUTPUT CMP TO # GPIO_167N_B7 # # CRYSTAL OSCILLATOR ENABLE PINS: # ------------------------------------ # NET 'XTAL_1_ENABLE' Y1501-1 R1501-1 # HI ENABLE THE XTAL #1 OUTPUT NET 'XTAL_2_ENABLE' Y1502-1 R1502-1 # HI ENABLE THE XTAL #2 OUTPUT NET 'XTAL_1_3V3' R1501-2 # PULL-UP SOURCE NET 'XTAL_2_3V3' R1502-2 # PULL-UP SOURCE # # 3.3 VOLT POWER AND GROUNDS TO THE CRYSTAL OSCILLATORS: # ----------------------------------------------------------- # NET 'BULK_3V3' L1501-1 # BULK_3V3 POWER TO FILTER NET 'XTAL_1_3V3' L1501-2 # FILTERED XTAL #1 3V3 POWER NET 'XTAL_1_3V3' C1501-2 C1503-2 # FILTERED 3V3 BYPASS CAPS NET 'GROUND' C1501-1 C1503-1 # GROUND SIDE OF FILTER CAPS NET 'XTAL_1_3V3' Y1501-6 # FILTERED 3V3 POWER TO XTAL #1 NET 'GROUND' Y1501-3 # GROUND TO XTAL #1 NET 'BULK_3V3' L1502-1 # BULK_3V3 POWER TO FILTER NET 'XTAL_2_3V3' L1502-2 # FILTERED XTAL #2 3V3 POWER NET 'XTAL_2_3V3' C1502-2 C1504-2 # FILTERED 3V3 BYPASS CAPS NET 'GROUND' C1502-1 C1504-1 # GROUND SIDE OF FILTER CAPS NET 'XTAL_2_3V3' Y1502-6 # FILTERED 3V3 POWER TO XTAL #2 NET 'GROUND' Y1502-3 # GROUND TO XTAL #2 # # BARNACLE INTERFACE # ---------------------- # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # INITIAL REV. 6-DEC-2022 # CURRENT REV. 27-DEC-2023 # # # THIS NET LIST HOLDS THE BARNACLE INTERFACE # # # THE COMPONENTS FOR THE BARNACLE INTERFACE # ARE IN THE RANGE 1551 TO 1599. # # # NOTE: IN ANOTHER NET LIST FILE THE EMERGENCY RESCUE # FUNCTIONS USE 1 SECTION OF THE U1551 HEX INVERTER # THAT IS OFFICIALLY PART OF THE BARNACLE INTERFACE CIRCUIT. # # # BARNACLE INTERFACE UART DATA BUFFERS AND THEIR FPGA/CPU CONNECTION: # -------------------------------------------------------------------------- # NET 'CPU_UART_2_TX__TO__BARNACLE' R1551-1 # DK CPU UART TX DATA TO TERMINATOR NET 'TX_TO_BARNACLE_TERM_BUF' R1551-2 U1551-3 # DK CPU UART TX DATA TO DATA BUFFER NET 'CPU_UART_TX_TO_BARNACLE_B' U1551-4 U1551-5 # INVERTED NET 'DATA_TO_BARNACLE_BUF_TERM' U1551-6 R1552-1 # TX DATA TO THE DK TX TERMINATOR NET 'DK_TX_DATA_TO_BARNACLE' R1552-2 J7-5 # TX DATA TO THE BARNACLE CONNECTOR NET 'DK_RX_DATA_FROM_BARNACLE' J7-7 U1551-11 # RX DATA FROM THE BARNACLE CONNECTOR NET 'DK_RX_DATA_FROM_BARNACLE_B' U1551-10 U1551-9 # INVERTED NET 'DK_RX_DATA_TO_TERMINATOR' U1551-8 R1553-1 # RX DATA FROM THE BARNACLE TO TERM NET 'CPU_UART_2_RX_FROM_BARNACLE' R1553-2 # RX DATA FROM THE BARNACLE VIA BUF # AND TERM TO THE DK'S CPU UART # # LIST THE NETNAMES OF THE SIGNALS THAT MUST BE # CONNECTED TO FPGA FLOATING PINS. HERE JUST LIST # THE NETNAMES - THE ACTUAL CONNECTIONS TO THESE # FPGA FLOATING PINS ARE MADE IN THE NETS FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # ---------------------------------------------------- # # # ALL OF THESE ARE 3V3 SIGNALS: BARNACLE UART DATA # --------------------------------------------------------------------------- # # NET 'CPU_UART_2_TX__TO__BARNACLE' # DK CPU UART 2 TX DATA TO BARNACLE # NET 'CPU_UART_2_RX_FROM_BARNACLE' # DK CPU UART 2 RX DATA FROM BARNACLE # # # # # BARNACLE INTERFACE MASTER_RESET_B & CONTROL SIGNALS TO THE BARNACLE: # ----------------------------------------------------------------------------- # NET 'BARNACLE_MASTER_RESET_B' J7-3 # MASTER_RESET_B TO THE BARNACLE NET 'DK_CONTROL_1_TO_BARNACLE' J7-9 # CONTROL SIGNAL #1 FROM DK TO THE BARNACLE NET 'DK_CONTROL_2_TO_BARNACLE' J7-11 # CONTROL SIGNAL #2 FROM DK TO THE BARNACLE # THESE 3 BARNACLE CONTROL SIGNALS COME FROM THE HARDWIRED # RESET CIRCUITS WHERE THEY ARE ALL FORCED LOW DURING POWER UP. # # BARNACLE INTERFACE POWER FEED AND GROUND PINS: # ----------------------------------------------------- # NET 'BULK_5V0' L1551-2 C1551-2 # BULK_5V0 POWER TO FILTER NET 'GROUND' C1551-1 # GROUND FILTER INPUT CAPACITOR NET 'BARNACLE_5V0' L1551-1 C1552-2 # FILTERED BARNACLE 5V0 POWER NET 'GROUND' C1552-1 # GROUND THE BYPASS CAPACITOR NET 'BARNACLE_5V0' J7-1 J7-13 # FILTERED 5V0 TO THE BARNACLE CONNECTOR NET 'GROUND' J7-2 J7-4 J7-6 # GROUNDS TO THE BARNACLE CONNECTOR NET 'GROUND' J7-8 J7-10 J7-12 NET 'GROUND' J7-14 # # 3.3 VOLT POWER AND GROUNDS TO THE UART DATA BUFFERS: # --------------------------------------------------------- # NET 'BULK_3V3' C1553-1 C1554-1 # UART DATA BUFFER 3V3 BYPASS CAPS NET 'GROUND' C1553-2 C1554-2 # GROUND SIDE OF BYPASS CAPS NET 'BULK_3V3' U1551-14 # 3V3 POWER TO UART DATA BUFFER CHIP NET 'GROUND' U1551-7 # GROUND TO UART DATA BUFFER CHIP NET 'GROUND' U1551-13 # TIE DOWN THE UNUSED INPUT OF THE # U1551 HEX INVERTER # # ACCESS CONNECTOR J12 # ------------------------- # # AND MISCELLANEOUS UART CONNECTIONS # ------------------------------------ # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # INITIAL REV. 14-DEC-2022 # CURRENT REV. 18-DEC-2023 # # # THIS NET LIST HOLDS THE CONNECTIONS TO THE J12 # ACCESS CONNECTOR PINS 11:40 AND MISCELLANEOUS # UART CONNECTIONS. # # # ADDITIONAL CONNECTIONS TO THE ACCESS CONNECTOR ARE # MADE IN THE NET LIST FILE: JTAG_FOR_FPGA_CPU_NETS.TXT # # # ADDITIONAL UART CONNECTIONS ARE MADE IN THE FOLLOWING # NET LIST FILES: # # BARNACLE_INTERFACE_NETS.TXT CPU MMUART #2 3V3 # # INTERPOSER_ALL_OTHER_NETS.TXT CPU MMUART #3 1V8 INTERPOSER #1 # CPU MMUART #4 1V8 INTERPOSER #2 # # RESCUE_RS485_NETS.TXT RESCUE UART #0 TO THE RS-485 CABLE # RESCUE UART #1 TO THE ACCESS HEADER # RESCUE UART #2 TO THE FPGA/CPU MMUART #1 # RESCUE UART #3 TO THE TOMCAT VIA LVDS # RESCUE UART #4 TO THE NOT USED # # # ALL OF THE ACTUAL UART CONNECTIONS TO THE FPGA/CPU ARE # MADE IN THE NET LIST FILE: # # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # # # THE COMPONENTS FOR THE ACCESS CONNECTOR # ARE IN THE RANGE 1401 TO 1449. # # # # ACCESS CONNECTOR J12 PINOUT # ------------------------------- # # # 1. JTAG_TCLK 2. GROUND # 3. JTAG_TDO 4. NO_CONNECTION # 5. JTAG_TMS 6. JTAG_3V3 # 7. NO_CONNECTION 8. JTAG_TRST # 9. JTAG_TDI 10. GROUND # # 11. GROUND 12. GROUND # 13. CPU MMUART #0 TX 3V3 14. CPU MMUART #0 RX 3V3 # 15. GROUND 16. GROUND # 17. RESCUE UART #1 TX 3V3 18. RESCUE UART #1 RX 3V3 # 19. GROUND 20. GROUND # # 21. ACCESS_SIGNAL_1 22. GROUND # 23. ACCESS_SIGNAL_2 24. GROUND # 25. ACCESS_SIGNAL_3 26. GROUND # 27. ACCESS_SIGNAL_4 28. GROUND # 29. ACCESS_SIGNAL_5 30. GROUND # # 31. GROUND 32. GROUND # 33. DIFF_SIGNAL_1_DIR 34. DIFF_SIGNAL_1_CMP # 35. GROUND 36. GROUND # 37. DIFF_SIGNAL_2_DIR 38. DIFF_SIGNAL_2_CMP # 39. GROUND 40. GROUND # # # # CONNECT THE FPGA/CPU MMUART #1 WITH THE RESCUE UART #2 # ----------------------------------------------------------- # # CONNECT THESE TX TO RX VIA 499 OHM RESISTORS TO HELP # LIMIT THE CURRENT FLOW WHEN ONE DEVICE IS POWERED UP # AND THE OTHER IS NOT YET DRIVING IT OUTPUT BANKS. # NET 'RESCUE_PIO_0_20_UART_2_TX' R1411-1 # ER UART 2 TX DATA TO NET 'CPU_UART_1_RX_FROM_ER_UPROC' R1411-2 # FPGA/CPU MMUART 1 RX NET 'RESCUE_PIO_0_19_UART_2_RX' R1412-1 # ER UART 2 RX DATA FROM NET 'CPU_UART_1_TX__TO__ER_UPROC' R1412-2 # FPGA/CPU MMUART 1 TX # # CONNECT PINS 11 THROUGH 40 OF THE J12 ACCESS CONNECTOR # -------------------------------------------------------------- # # NET 'GROUND' J12-11 J12-12 NET 'CPU_UART_0_TX__TO__ACCESS' J12-13 # CPU UART 0 TX DATA TO ACCESS CONNECTOR NET 'CPU_UART_0_RX_FROM_ACCESS' J12-14 # CPU UART 0 RX DATA FROM ACCESS CONNECTOR NET 'GROUND' J12-15 J12-16 NET 'RESCUE_PIO_0_7_UART_1_TX' J12-17 # ER UART 1 TX DATA TO HEADER PIN NET 'RESCUE_PIO_0_6_UART_1_RX' J12-18 # ER UART 1 RX DATA FROM HEADER PIN NET 'GROUND' J12-19 J12-20 NET 'ACCESS_SIGNAL_1' J12-21 # ACCESS CONNECTOR FPGA SIGNAL #1 NET 'GROUND' J12-22 NET 'ACCESS_SIGNAL_2' J12-23 # ACCESS CONNECTOR FPGA SIGNAL #2 NET 'GROUND' J12-24 NET 'ACCESS_SIGNAL_3' J12-25 # ACCESS CONNECTOR FPGA SIGNAL #3 NET 'GROUND' J12-26 NET 'ACCESS_SIGNAL_4' J12-27 # ACCESS CONNECTOR FPGA SIGNAL #4 NET 'GROUND' J12-28 NET 'ACCESS_SIGNAL_5' J12-29 # ACCESS CONNECTOR FPGA SIGNAL #5 NET 'GROUND' J12-30 NET 'GROUND' J12-31 J12-32 NET 'ACCESS_DIFF_PAIR_1_DIR' J12-33 # ACCESS CONNECTOR FPGA DIFFERENTIAL PAIR #1 DIR NET 'ACCESS_DIFF_PAIR_1_CMP' J12-34 # ACCESS CONNECTOR FPGA DIFFERENTIAL PAIR #1 CMP NET 'GROUND' J12-35 J12-36 NET 'ACCESS_DIFF_PAIR_2_DIR' J12-37 # ACCESS CONNECTOR FPGA DIFFERENTIAL PAIR #2 DIR NET 'ACCESS_DIFF_PAIR_2_CMP' J12-38 # ACCESS CONNECTOR FPGA DIFFERENTIAL PAIR #2 CMP NET 'GROUND' J12-39 J12-40 # # LIST THE NETNAMES OF THE SIGNALS THAT MUST BE # CONNECTED TO FPGA FLOATING PINS. HERE JUST LIST # THE NETNAMES - THE ACTUAL CONNECTIONS TO THESE # FPGA FLOATING PINS ARE MADE IN THE NETS FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # ---------------------------------------------------- # # # THESE ARE 3V3 SIGNALS: CPU MMUART #0 DATA TO/FROM ACCESS CONNECTOR # ------------------------------------------------------------------------ # # NET 'CPU_UART_0_TX__TO__ACCESS' # CPU UART 0 TX DATA TO ACCESS CONNECTOR # NET 'CPU_UART_0_RX_FROM_ACCESS' # CPU UART 0 RX DATA FROM ACCESS CONNECTOR # # # THESE ARE 3V3 SIGNALS: CPU MMUART #1 DATA TO/FROM EMERGENCY RESCUE UPROCESSOR # ----------------------------------------------------------------------------------- # # NET 'CPU_UART_1_TX__TO__ER_UPROC' # CPU UART 1 TX DATA TO EMERGENCY RESCUE UPROC # NET 'CPU_UART_1_RX_FROM_ER_UPROC' # CPU UART 1 RX DATA FROM EMERGENCY RESCUE UPROC # # # # THESE ARE 3V3 SIGNALS: FPGA/CPU <--> ACCESS CONNECTOR SINGLE ENDED SIGNALS # --------------------------------------------------------------------------------- # # NET 'ACCESS_SIGNAL_1' # ACCESS CONNECTOR FPGA SIGNAL #1 # NET 'ACCESS_SIGNAL_2' # ACCESS CONNECTOR FPGA SIGNAL #2 # NET 'ACCESS_SIGNAL_3' # ACCESS CONNECTOR FPGA SIGNAL #3 # NET 'ACCESS_SIGNAL_4' # ACCESS CONNECTOR FPGA SIGNAL #4 # NET 'ACCESS_SIGNAL_5' # ACCESS CONNECTOR FPGA SIGNAL #5 # # # # BOTH OF THESE ARE DIFFERENTIAL SIGNALS, E.G. LVDS: # # FPGA/CPU <--> ACCESS CONNECTOR DIFFERENTIAL PAIRS # ---------------------------------------------------------------------------------------- # # NET 'ACCESS_DIFF_PAIR_1_DIR' # ACCESS CONNECTOR FPGA DIFFERENTIAL PAIR #1 DIR # NET 'ACCESS_DIFF_PAIR_1_CMP' # ACCESS CONNECTOR FPGA DIFFERENTIAL PAIR #1 CMP # # NET 'ACCESS_DIFF_PAIR_2_DIR' # ACCESS CONNECTOR FPGA DIFFERENTIAL PAIR #2 DIR # NET 'ACCESS_DIFF_PAIR_2_CMP' # ACCESS CONNECTOR FPGA DIFFERENTIAL PAIR #2 CMP # # # STARTUP AND RESET NETS # --------------------------- # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # INITIAL REV. 15-DEC-2022 # CURRENT REV. 4-JAN-2024 # # # THIS NET LIST HOLDS THE STARTUP AND RESET # NETS. # # THE COMPONENTS IN THE STARTUP AND RESET # SECTION OF THE DESIGN HAVE REFERENCE # DESIGNATORS IN THE RANGE 1151 :1199 # # NOTE: BELOW THE USE OF ONE SECTION IN THE U1402 HEX INVERTER # TO HANDLE INVERTING THE DK_CPU_IS_AWAKE_B SIGNAL. # U1402 OFFICIALLY BELONGS TO THE DK FPGA/CPU JTAG # CIRCUITS AND APPEARS IN THAT NET LIST FILE. # # NOTES: THE STARTUP AND RESETS ICS U1151 THROUGH U1155 ARE # POWERED BY THE "ALWAYS ON" CNST_3V3 SUPPLY WHERE AS # THE ASSOCIATED PULL-UP RESISTORS R1171 & R1172 ARE # POWERED BY BULK_3V3 BECAUSE THERE IS NO NEED OR # DESIRE FOR THE SIGNALS PULLED UP BY THESE RESISTORS # TO BE IN THE HI STATE BEFORE THE BULK_3V3 HAS # FINISHED ITS RAMP UP. # # U1156 AND THE PULL-UP RESISTOR R1177 ARE POWERED BY # THE BULK_5V0 SUPPLY BECAUSE THIS CIRCUIT MUST SUPPLY # A GLITCH FREE MASTER_RESET_B TO THE BARNACLE INTERFACE # AS THE BULK_5V0 SUPPLY RAMPS UP. # # TWO SECTION OF THE U1602 QUAD NAND (WHICH IS OFFICIALLY # PART OF THE SFP CONTROL CIRCUITS) ARE USED BY THE # STARTUP AND RESET CIRCUITS THAT ARE DESCRIBED BELOW. # U1602 4,5,6 IS USED TO MAKE THE DK_CPU_IS_SANE_B # SIGNAL THAT IS USED BY THE EMERGENCY RESCUE CIRCUITS # AND U1602 8,9,10 IS USED TO MAKE A SPARE RUN SIGNAL. # # # STARTUP DELAY TPS3808S U1151 - SENSES THE BULK_5V0 AND # --------------- MAKES THE DCDC CONVERTER "TRACK BUS": # ----------------------------------------------------------------------------- # NET 'BULK_5V0' R1161-1 # BULK 5V0 TO THE SENSE RESISTOR DIVIDER NET 'START_DELAY_SENSE' R1161-2 R1162-1 # SENSE INPUT TO THE STARTUP DELAY NET 'START_DELAY_SENSE' U1151-5 C1161-1 # SENSE INPUT TO THE STARTUP DELAY NET 'GROUND' R1162-2 C1161-2 # GROUND VOLT DIVIDER AND FILTER CAP NET 'START_DELAY_CAP_T' U1151-4 C1162-1 # START DELAY TIMING CAP NET 'GROUND' C1162-2 # GROUND TIMING CAP NET 'NO_CONN_U1151_PIN_3' U1151-3 # UN-USED START DELAY MR_B PIN NET 'DCDC_CONV_TRACK' U1151-1 # START DELAY RESET_B PIN # "TRACK BUS" TO THE 7 DCDC CONVERTERS # # ALL POWER GOOD TPS3808S U1152 - SENSES THE BULK_3V3 AND # ---------------- MAKES THE DELAYED_ALL_POWER_GOOD SIGNAL: # ----------------------------------------------------------------------------------- # NET 'BULK_3V3' R1163-1 # BULK 3V3 TO THE SENSE RESISTOR DIVIDER NET 'ALL_GOOD_DELAY_SENSE' R1163-2 R1164-1 # SENSE INPUT TO THE ALL_POWER_GOOD DELAY NET 'ALL_GOOD_DELAY_SENSE' U1152-5 C1163-1 # SENSE INPUT TO THE ALL_POWER_GOOD DELAY NET 'GROUND' R1164-2 C1163-2 # GROUND VOLT DIVIDER AND FILTER CAP NET 'ALL_GOOD_DELAY_CAP_T' U1152-4 C1164-1 # ALL_POWER_GOOD DELAY TIMING CAP NET 'GROUND' C1164-2 # GROUND TIMING CAP NET 'NO_CONN_U1152_PIN_3' U1152-3 # UN-USED ALL POWER GOOD MR_B PIN NET 'DELAYED_ALL_POWER_GOOD' U1152-1 # ALL POWER GOOD DELAY RESET_B PIN # DELAYED_ALL_POWER_GOOD TO THE RESET CIRCUITS # # MAKE THE "CPU IS SANE" AND "FPGA/CPU_RESET_B" SIGNALS: # -------------------------------------------------------------- # # NOTE: THE USE OF ONE SECTION IN THE U1402 HEX INVERTER # TO HANDLE INVERTING THE DK_CPU_IS_AWAKE_B SIGNAL. # U1402 OFFICIALLY BELONGS TO THE DK FPGA/CPU JTAG # CIRCUITS AND APPEARS IN THAT NET LIST FILE. # # THE DK_CPU_IS_SANE SIGNAL IS MADE BELOW BY U1153 # AND DK_CPU_IS_SANE_B IS MADE IN THE SFP NET LIST FILE # BY U1602. # NET 'DELAYED_ALL_POWER_GOOD' R1171-1 U1153-5 U1155-1 # PULL-UP ON DELAYED ALL POWER GOOD NET 'BULK_3V3' R1171-2 # 3V3 PULL-UP SOURCE NET 'FPGA_CPU_RESET_B' R1172-1 U1-H9 U1155-2 # RESET TO THE FPGA/CPU NET 'BULK_3V3' R1172-2 # 3V3 PULL-UP SOURCE NET 'DK_CPU_IS_AWAKE' R1173-1 U1153-2 # CPU IS AWAKE & ITS PULL-DOWN NET 'GROUND' R1173-2 # PULL-DOWN ANCHOR NET 'DK_CPU_IS_AWAKE_B' R1174-1 U1402-1 # CPU IS AWAKE_B TO INVERTER & PULL-UP NET 'CNST_3V3' R1174-2 # 3V3 PULL-UP SOURCE NET 'DK_CPU_IS_AWAKE_B_INV' U1402-2 U1153-1 # INVERTED AWAKE_B TO AND NET 'DK_CPU_AWAKE_AND_B' U1153-3 U1153-4 # AWAKE & _B TO AND WITH DELAYED ALL GOOD NET 'DK_CPU_IS_SANE' R1178-1 U1153-6 # DK_CPU_IS_SANE FOR DISTRIBUTION NET 'GROUND' R1178-2 # PULL-DOWN ON DK_CPU_IS_SANE WITH 4.7K # SO THAT IT IS DEFINED EVEN BEFORE THE # CNST_3V3 SUPPLY IS FULLY RAMPED UP. # IN THIS WAY THE BARNACLE_MASTER_RESET_B # IS DEFINED LOW WHILE THE BULK_5V0 RAMPS. # # MAKE THE PMT_ADC_RESET_B THIS IS A 1V8 LOW ACTIVE SIGNAL: # ------------------------------------------------------------------ NET 'RUN_PMT_ADC' U1153-9 # RUN_PMT_ADC SIGNAL FROM CPU NET 'DK_CPU_IS_SANE' U1153-10 # AND WITH DK_CPU_IS_SANE NET 'DK_SANE__RUN_PMT' U1153-8 U1155-3 # AND OF SANE AND RUN_PMT NET 'PMT_ADC_RESET_B' U1155-4 R1175-1 # PMT_ADC_RESET_B SIGNAL NET 'BULK_1V8' R1175-2 # PULL-UP 1V8 SOURCE # # MAKE THE BB_AUDIO_ADC_RESET_B THIS IS A 1V8 LOW ACTIVE SIGNAL: # ----------------------------------------------------------------------- NET 'RUN_BB_AUDIO_ADC' U1153-13 # RUN_BB_AUDIO_ADC SIGNAL FROM CPU NET 'DK_CPU_IS_SANE' U1153-12 # AND WITH DK_CPU_IS_SANE NET 'DK_SANE__RUN_BB_ADC' U1153-11 U1155-5 # AND OF SANE AND RUN_BB_AUDIO_ADC NET 'BB_AUDIO_ADC_RESET_B' U1155-6 R1176-1 # BB_AUDIO_ADC_RESET_B SIGNAL NET 'BULK_1V8' R1176-2 # PULL-UP 1V8 SOURCE # # MAKE THE CLOCK_GENERATOR_RESET_B THIS IS A 3V3 LOW ACTIVE SIGNAL: # -------------------------------------------------------------------------- NET 'RUN_CLOCK_GENERATOR' U1154-5 # RUN_BB_AUDIO_ADC SIGNAL FROM CPU NET 'DK_CPU_IS_SANE' U1154-4 # AND WITH DK_CPU_IS_SANE NET 'CLOCK_GEN_RESET_B' U1154-6 # CLOCK_GEN_RESET_B SIGNAL # # MAKE THE USB_RESET_B THIS IS A 3V3 LOW ACTIVE SIGNAL: # -------------------------------------------------------------- NET 'RUN_USB_INTERFACE' U1154-1 # RUN_USB_INTERFACE SIGNAL FROM CPU NET 'DK_CPU_IS_SANE' U1154-2 # AND WITH DK_CPU_IS_SANE NET 'USB_RESET_B' U1154-3 # USB_RESET_B SIGNAL # # MAKE A SPARE_RESET SIGNAL THIS IS A 3V3 HI ACTIVE SIGNAL: # # THIS RUN SPARE CIRCUIT USES U1602 WHICH IS OFFICIALLY # PART OF THE SFP CONTROL CIRCUITS. IN THE SFP CONTROL # CIRCUIT NET LIST FILE THE DK_CPU_IS_SANE SIGNAL IS # CONNECTED TO PIN U1602-10. # ------------------------------------------------------------------ NET 'RUN_SPARE' U1602-9 # RUN_SPARE SIGNAL FROM CPU NET 'SPARE_RESET' U1602-8 # SPARE_RESET SIGNAL 3V3 HI ACTIVE # CURRENTLY THIS RESET SIGNAL IS NOT USED. # # MAKE THE BARNACLE_CONTROL_ 1 AND 2 SIGNALS # # THEY ARE OPEN-DRAIN OUTPUTS WITH PULL-UP RESISTORS ON THE BARNACLE: # ----------------------------------------------------------------------- NET 'BARNACLE_CONTROL_1' U1154-13 # BARNACLE_CONTROL_1 SIGNAL FROM CPU NET 'DK_CPU_IS_SANE' U1154-12 # AND WITH DK_CPU_IS_SANE NET 'DK_SANE__BARN_CTRL_1' U1154-11 U1155-13 # AND OF SANE AND BARN_CTRL_1 NET 'DK_CONTROL_1_TO_BARNACLE' U1155-12 # CONTROL_1 SIGNAL TO THE BARNACLE NET 'BARNACLE_CONTROL_2' U1154-9 # BARNACLE_CONTROL_2 SIGNAL FROM CPU NET 'DK_CPU_IS_SANE' U1154-10 # AND WITH DK_CPU_IS_SANE NET 'DK_SANE__BARN_CTRL_2' U1154-8 U1155-11 # AND OF SANE AND BARN_CTRL_2 NET 'DK_CONTROL_2_TO_BARNACLE' U1155-10 # CONTROL_2 SIGNAL TO THE BARNACLE # # MAKE THE BARNACLE_MASTER_RESET_B SIGNAL # # THIS IS AN OPEN-DRAIN OUTPUT WITH ITS PULL-UP RESISTOR ON THE BARNACLE: # LIMIT THE PULL-UP CURRENT ON THE BARNACLE TO 500 UAMPS # --------------------------------------------------------------------------- # NET 'DK_CPU_IS_SANE' R1165-1 # DK_CPU_IS_SANE CMOS LOGIC SIGNAL # INPUT TO VOLTAGE DIVIDER THAT NET 'BARN_SENSE_PIN' R1165-2 R1166-1 # FEEDS THE SENSE PIN ON THE NET 'BARN_SENSE_PIN' C1165-1 U1156-5 # BARNACLE_MASTER_RESET_B TPS3808 NET 'GROUND' C1165-2 R1166-2 # GROUND LOW SIDE DIVIDER AND FLTR CAP NET 'RUN_BARNACLE' U1155-9 # RUN_BARNACLE 3V3 SIGNAL FROM THE FPGA/CPU # INPUT TO THE O.D. BUFFER FOR CONVERSION NET 'RUN_BARN_5V' U1155-8 R1177-1 # TO A 5V LOGIC SIGNAL TO FEED THE MR_B NET 'RUN_BARN_5V' U1156-3 # INPUT ON THE BARN_MASTER_RESET_B TPS3808 NET 'BULK_5V0' R1177-2 # PULL-UP SOURCE TO BULK_5V0 NET 'NO_CONN_BARNACLE_U1156_PIN_4' U1156-4 # OPEN TPS3808 TIMING PIN ---> 20 MSEC. NET 'BARNACLE_MASTER_RESET_B' U1156-1 # MASTER_RESET_B TO THE BARNACLE # # POWER AND GROUND TO THE ICS AND THEIR BYPASS CAPS: # ------------------------------------------------------- # NET 'CNST_3V3' U1151-6 U1152-6 # CNST_3V3 TO THE TWO STARTUP TPS3808S NET 'GROUND' U1151-2 U1152-2 # AND THEIR GROUND NET 'CNST_3V3' U1153-14 U1154-14 U1155-14 # CNST_3V3 TO THE THREE RESET ICS NET 'GROUND' U1153-7 U1154-7 U1155-7 # AND THEIR GROUND NET 'CNST_3V3' C1151-1 C1152-1 C1153-1 # CNST_3V3 TO BYPASS CAPS NET 'GROUND' C1151-2 C1152-2 C1153-2 # AND THE BYPASS GROUNDS NET 'CNST_3V3' C1154-1 C1155-1 # CNST_3V3 TO BYPASS CAPS NET 'GROUND' C1154-2 C1155-2 # AND THE BYPASS GROUNDS NET 'BULK_5V0' U1156-6 # 5V0 TO THE BARNACLE RESET TPS3808 NET 'GROUND' U1156-2 # AND ITS GROUND NET 'BULK_5V0' C1156-1 # 5V0 TO A BYPASS CAP NET 'GROUND' C1156-2 # AND THAT BYPASS GROUND # # LIST THE NETNAMES OF THE SIGNALS THAT MUST BE # CONNECTED TO FPGA FLOATING PINS. HERE JUST LIST # THE NETNAMES - THE ACTUAL CONNECTIONS TO THESE # FPGA FLOATING PINS ARE MADE IN THE NETS FILE: # FPGA_CPU_FLOATING_CONNECTION_NETS.TXT # ---------------------------------------------------- # # # THESE ARE 3V3 SIGNALS: DK_CPU_IS_AWAKE (_B) AND THE RUN SIGNALS # ----------------------------------------------------------------------- # # NET 'DK_CPU_IS_AWAKE' # CPU IS AWAKE SIGNAL # NET 'DK_CPU_IS_AWAKE_B' # CPU IS AWAKE_B SIGNAL # # NET 'RUN_PMT_ADC' # LOW ---> RESET THE AD9083 PMT ADC # NET 'RUN_CLOCK_GENERATOR' # LOW ---> RESET THE AD9546 CLOCK GENERATOR # NET 'RUN_USB_INTERFACE' # LOW ---> RESET THE USB3340 USB TRANSCEIVER # NET 'RUN_BB_AUDIO_ADC' # LOW ---> RESET THE TLV320ADC6140 BB AUDIO ADC # NET 'RUN_SPARE' # CURRENTLY 26-DEC-2023 THIS SIGNAL IS NOT USED # # NET 'RUN_BARNACLE' # LOW ---> BARNACLE POWER DOWN AND MASTER_RESET_B # NET 'BARNACLE_CONTROL_1' # BARNACLE CONTROL SIGNAL 1 DEFAULT IS LOW # NET 'BARNACLE_CONTROL_2' # BARNACLE CONTROL SIGNAL 2 DEFAULT IS LOW # # # DISCO-KRAKEN KEY IN NET LIST # ------------------------------- # # # FLOATING PIN CONNECTIONS TO FPGA/CPU # -==============------------------------- # # # # INITIAL REV. 4-DEC-2023 # CURRENT REV. 27-DEC-2023 # # # # THIS NETLIST HOLDS JUST THE FPGA/CPU END OF NETS THAT CONNECT # TO "FLOATING" PINS ON THIS COMPONENT, I.E. TO PINS THAT ARE # FIXED TO A GIVEN PIN NUMBER ONLY BY THE DESIGN PUT INTO THE # FPGA/CPU. # # FUNCTION SPECIFIC PINS, E.G. BANK #3, DDR4 MEMORY, HIGH-SPEED # SERIAL LINKS, ARE ALL ASSIGNED IN THE NET LIST FILE THAT # DESCRIBES THAT PARTICULAR FUNCTION ON THE DK BOARD. # # THIS NET LIST FILE IS ONLY FOR THE FPGA/CPU END OF THESE # "FLOATING" CONNECTIONS. ALL OF THESE FLOATING CONNECTIONS # ARE EITHER TO: BANK #9 FOR 1V8 I/O OR TO BANKS #1 & #7 # FOR 3V3 I/O. MOST OF THESE FLOATING CONECTIONS GO TO CPU # PERIPHERALS OR TO NORMAL FPGA I/O SIGNALS. # # FOR REFERENCE THE PINS IN BANKS 1, 7, AND 9 ARE LISTED AT # THE END OF THIS FILE. # # THE INTENT OF THIS NET LIST FILE IS TO COLLECT IN ONE PLACE ALL # OF THE FLOATING PIN CONNECTIONS TO THE FPGA/CPU SO THAT IT IS # EASIER TO COORDINATE THESE PIN NUMBERS WITH THE FIRMWARE/SOFTWARE # WORK ON THIS PART. # # THE NET LIST FILES THAT DESCRIBE THE FUNCTIONS THAT ARE ASSIGNED # TO FLOATING PINS ON THE FPGA/CPU ALL INCLUDED A NOTE TO REMIND # FOLKS THAT THE FINAL STEP IN THESE FLOATING FPGA/CPU CONECTIONS # IS IN THIS FILE. # # THIS FILE IS DEVIDED INTO A NUMBER OF SECTIONS - ONE SECTION FOR # EACH DK BOARD FUNCTION THAT CONNECTS TO THE FPGA/CPU VIA FLOATING # PIN ASSIGNMENTS. # # #--------------------------------------------------------------------- # # 26-DEC-2023 CURRENTLY THERE ARE 72 FLOATING PIN NETS # START BY RANDOMLY ASSIGNING THEM TO RANDOM PINS. # ASSIGN INTO THE CORRECT VOLTAGE BANK AND # FOR NOW INTO THE FIRST 3 RINGS. # # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # ACCESS CONNECTOR AND UART TO ER UPROC CONNECTIONS WITH THE FPGA/CPU 13 PINS # --------------------------------------------------------------------------------------- # # # THESE ARE 3V3 SIGNALS: CPU MMUART #0 DATA TO/FROM ACCESS CONNECTOR # ------------------------------------------------------------------------ NET 'CPU_UART_0_TX__TO__ACCESS' U1-B4 # CPU UART 0 TX DATA TO ACCESS CONN. GPIO177PB1/CCC_SW_PLL0_OUT0 NET 'CPU_UART_0_RX_FROM_ACCESS' U1-A4 # CPU UART 0 RX DATA FROM ACCESS CONN. GPIO177NB1 # # THESE ARE 3V3 SIGNALS: CPU MMUART #1 DATA TO/FROM EMERGENCY RESCUE UPROCESSOR # ----------------------------------------------------------------------------------- NET 'CPU_UART_1_TX__TO__ER_UPROC' U1-D4 # CPU UART 1 TX DATA TO ER UPROC GPIO176PB1/DQS/CCC_SW_PLL0_OUT0 NET 'CPU_UART_1_RX_FROM_ER_UPROC' U1-C4 # CPU UART 1 RX DATA FROM ER UPROC GPIO176NB1/DQS # # # THESE ARE 3V3 SIGNALS: FPGA/CPU <--> ACCESS CONNECTOR SINGLE ENDED SIGNALS # ---------------------------------------------------------------------------------------- NET 'ACCESS_SIGNAL_1' U1-C1 # ACCESS CONN. FPGA SIGNAL #1 GPIO172PB1/CCC_SW_PLL1_OUT1 NET 'ACCESS_SIGNAL_2' U1-B1 # ACCESS CONN. FPGA SIGNAL #2 GPIO172NB1 NET 'ACCESS_SIGNAL_3' U1-C2 # ACCESS CONN. FPGA SIGNAL #3 GPIO168PB1/CCC_SW_CLKIN_S_0 NET 'ACCESS_SIGNAL_4' U1-B2 # ACCESS CONN. FPGA SIGNAL #4 GPIO168NB1 NET 'ACCESS_SIGNAL_5' U1-A2 # ACCESS CONN. FPGA SIGNAL #5 GPIO173PB1/CLKIN_S_3/ # CCC_SW_CLKIN_S_3 # # BOTH OF THESE ARE DIFFERENTIAL SIGNALS, E.G. LVDS: # # FPGA/CPU <--> ACCESS CONNECTOR DIFFERENTIAL PAIRS # ---------------------------------------------------------------------------------------- NET 'ACCESS_DIFF_PAIR_1_DIR' U1-E1 # ACCESS CONN. DIFF PAIR #1 DIR GPIO170PB1/DQS/CCC_SW_PLL1_OUT0 NET 'ACCESS_DIFF_PAIR_1_CMP' U1-D1 # ACCESS CONN. DIFF PAIR #1 CMP GPIO170NB1/DQS NET 'ACCESS_DIFF_PAIR_2_DIR' U1-D3 # ACCESS CONN. DIFF PAIR #2 DIR GPIO171PB1/ # CLKIN_S_2/CCC_SW_CLKIN_S_2/ # CCC_SW_PLL1_OUT0 NET 'ACCESS_DIFF_PAIR_2_CMP' U1-C3 # ACCESS CONN. DIFF PAIR #2 CMP GPIO171NB1 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # BARNACLE TO/FROM CPU MMUART #2 DATA CONNECTIONS 2 PINS # ------------------------------------------------------------------- # # # THESE ARE 3V3 SIGNALS: BARNACLE UART DATA # CPU MMUART #2 # ---------------------------------------------- NET 'CPU_UART_2_TX__TO__BARNACLE' U1-E3 # DK CPU UART 2 TX DATA TO BARNACLE GPIO169PB1/ # CCC_SW_CLKIN_S_1 NET 'CPU_UART_2_RX_FROM_BARNACLE' U1-E2 # DK CPU UART 2 RX DATA FROM BARNACLE GPIO169NB1 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # BB AUDIO ADC CLOCK AND READOUT DATA CONNECTIONS WITH THE FPGA/CPU 4 PINS # --------------------------------------------------------------------------------- # # # THESE ARE 1V8 SIGNALS: BB AUDIO ADC READOUT SIGNALS # ------------------------------------------------------- NET 'FPGA_BB_ADC_CLK_OUT' U1-A27 # FPGA OUTPUT BB AUDIO ADC CLK GPIO57PB9/ # CLKIN_S_12/ # CCC_SE_CLKIN_S_12/ # CCC_SE_PLL0_OUT0 NET 'FPGA_BB_ADC_SDATA_IN' U1-A22 # FPGA INPUT BB ADC SDATA INPUT GPIO50PB9/DQS NET 'FPGA_BB_ADC_BCLK_IN' U1-A23 # FPGA INPUT BB ADC BCLK INPUT GPIO50NB9/DQS NET 'FPGA_BB_ADC_FSYNC_IN' U1-A24 # FPGA INPUT BB ADC FSYNC INPUT GPIO53PB9 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # ENVIRONMENTAL SENSOR I2C BUS CONNECTIONS WITH THE FPGA/CPU 2 PINS # -------------------------------------------------------------------------- # # # THESE ARE 1V8 SIGNALS: ENV SESNSOR AND BB AUDIO I2C BUS # CPU I2C CONTROLLER #1 # ----------------------------------------------------------- NET 'I2C_DATA_SENSOR_BB_ADC' U1-B20 # SENSOR & BB ADC I2C BUS DATA GPIO47PB9 NET 'I2C_SCLK_SENSOR_BB_ADC' U1-A20 # SENSOR & BB ADC I2C BUS CLOCK GPIO47NB9 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # INTERPOSER 1 AND 2 CONNECTIONS TO THE FPGA/CPU VIA FLOATING PINS 18 PINS # --------------------------------------------------------------------------------- # # # THESE ARE 3V3 SIGNALS: SPI BUS AND GPIO USED WITH THE INTERPOSER SPI BUS # FROM CPU SPI CONTROLLER #1 AND 5 GPIO SIGNALS # ------------------------------------------------------------------------------ NET 'POSER_SCLK_FPGA_TO_TERM' U1-B6 # SCLK FPGA TO INTERPOSERS GPIO175NB1 NET 'POSER_MOSI_FPGA_TO_TERM' U1-B5 # MOSI FPGA TO INTERPOSERS GPIO179PB1 NET 'POSER_MISO_TERM_TO_FPGA' U1-A5 # MISO MUX TERM TO FPGA GPIO179NB1 NET 'POSER_CS_1_B' U1-B7 # FPGA SIGNAL TO ENABLE INTERPOSER #1 MUX _B GPIO1PB1/CLKIN_S_5 NET 'POSER_CS_2_B' U1-A7 # FPGA SIGNAL TO ENABLE INTERPOSER #2 MUX _B GPIO1NB1 NET 'POSER_CS_ADRS_0' U1-C8 # CS ADDRESS 0 FPGA TO MUX GPIO2PB1/DQS NET 'POSER_CS_ADRS_1' U1-C7 # CS ADDRESS 1 FPGA TO MUX GPIO2NB1/DQS NET 'POSER_CS_ADRS_2' U1-A8 # CS ADDRESS 2 FPGA TO MUX GPIO3PB1/CLKIN_S_6 # # THESE ARE 1V8 SIGNALS: CPU UART DATA TO/FROM BOTH INTERPOSERS --> PMT BASES # CPU MMUART #3 <--> INTERPOSER #1 "THIS HEMISPHERE" # CPU MMUART #4 <--> INTERPOSER #2 "OTHER HEMISPHERE" # --------------------------------------------------------------------------------- NET 'CPU_UART_3_TX__TO__POSER_1' U1-A17 # TX UART 3 DATA TO INTERPOSER_1 VIA BUFFER GPIO43PB9 NET 'CPU_UART_3_RX_FROM_POSER_1' U1-A18 # RX UART 3 DATA FROM INTERPOSER_1 VIA BUFFER GPIO43NB9 NET 'CPU_UART_4_TX__TO__POSER_2' U1-B19 # TX UART 4 DATA TO INTERPOSER_2 VIA BUFFER GPIO45PB9 NET 'CPU_UART_4_RX_FROM_POSER_2' U1-A19 # RX UART 4 DATA FROM INTERPOSER_2 VIA BUFFER GPIO45NB9 # # ALL OF THESE ARE 3V3 SIGNALS: FLASH-NOW TO BOTH INTERPOSERS AND TO AD9546 # CONTROL-RESET TO BOTH INTERPOSERS # SMUT S1...S4 FROM OTHER INTERPOSER TO FPGA # ------------------------------------------------------------------------------------- NET 'FLASH_NOW' U1-A9 # FLASH_NOW FROM THE FPGA/CPU TO BOTH GPIO3NB1 # INTERPOSERS AND TO THE AD9546 FOR # TIME MEASUREMENT A 3V3 CMOS SIGNAL NET 'INTERPOSER_CTRL_RESET' U1-C9 # CONTROL RESET TO BOTH INTERPOSERS FROM FPGA GPIO4PB1/LPRB_A NET 'MUON_S1_OTHER_HEMI' U1-B9 # MUON SMUT SIGNAL S1 FROM OTHER HEMISPHERE TO FPGA GPIO4NB1/LPRB_B NET 'MUON_S2_OTHER_HEMI' U1-B10 # MUON SMUT SIGNAL S2 FROM OTHER HEMISPHERE TO FPGA GPIO5PB1/CLKIN_S_7 NET 'MUON_S3_OTHER_HEMI' U1-A10 # MUON SMUT SIGNAL S3 FROM OTHER HEMISPHERE TO FPGA GPIO5NB1 NET 'MUON_S4_OTHER_HEMI' U1-B11 # MUON SMUT SIGNAL S4 FROM OTHER HEMISPHERE TO FPGA GPIO13NB1 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # PMT ADC CONNECTIONS WITH THE FPGA/CPU 7 PINS # ------------------------------------------------------- # # # THESE ARE 1V8 SPI SIGNALS: PMT ADC SPI BUS (PRIVATE) # CPU SPI BUS CONTROLLER #0 # AND 4W TO 3W CONVERTER # ------------------------------------------------------------ NET 'PMT_ADC_CHIP_SELECT_B' U1-B21 # ADC SPI CHIP SELECT ACTIVE LOW GPIO49PB9 NET 'PMT_ADC_SPI_CLOCK' U1-C21 # ADC SPI CLOCK GPIO49NB9 NET 'PMT_ADC_SPI_DATA_IO' U1-B22 # ADC SPI DATA I/O GPIO52PB9 # # THESE ARE LVDS SIGNALS: PMT ADC CLOCK TYPE SIGNALS # I THINK THIS SHOULD BE 1V8 LVDS # ------------------------------------------------------------ NET 'PMT_ADC_SYNC_ENB_B_DIR' U1-B24 # ADC JESD204B SYNC ENB B DIR GPIO54PB9 NET 'PMT_ADC_SYNC_ENB_B_CMP' U1-C24 # ADC JESD204B SYNC ENB B CMP GPIO54NB9 NET 'PMT_ADC_TRIGGER_DIR' U1-B25 # ADC TRIGGER DIR INPUT GPIO55PB9 NET 'PMT_ADC_TRIGGER_CMP' U1-B26 # ADC TRIGGER CMP INPUT GPIO55NB9 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # SFP MODULE AND I2C CONTROLLER #0 CONNECTIONS WITH THE FPGA/CPU 15 PINS # -------------------------------------------------------------------------------- # # # THESE ARE 3V3 SIGNALS: SFP MODULE CONTROL AND MONITOR SIGNALS # ----------------------------------------------------------------- NET 'SFP_TIME_TX_FAULT' U1-C14 # TIME SFP TX FAULT TO FPGA/CPU GPIO INPUT GPIO15PB1/ # CCC_SE_CLKIN_S_10 NET 'SFP_TIME_MOD_ABS' U1-B12 # TIME SFP MODULE ABSENT TO FPGA/CPU GPIO INPUT GPIO13PB1 NET 'SFP_TIME_RX_LOS' U1-C13 # TIME SFP RX SIGNAL LOSS TO FPGA/CPU GPIO INPUT GPIO14PB1/DQS NET 'SFP_TIME_TRANS_ENABLE' U1-C12 # TIME SFP TX ENABLE FROM FPGA/CPU GPIO OUTPUT GPIO14NB1/DQS NET 'SFP_TIME_RS_0' U1-D11 # TIME SFP RATE SELECT 0 <--> FPGA/CPU GPIO I/O GPIO16PB1 NET 'SFP_TIME_RS_1' U1-C11 # TIME SFP RATE SELECT 1 <--> FPGA/CPU GPIO I/O GPIO16NB1 NET 'SFP_ENET_TX_FAULT' U1-D9 # ENET SFP TX FAULT TO FPGA/CPU GPIO INPUT GPIO0PB1/CLKIN_S_4 NET 'SFP_ENET_MOD_ABS' U1-D10 # ENET SFP MODULE ABSENT TO FPGA/CPU GPIO INPUT GPIO0NB1 NET 'SFP_ENET_RX_LOS' U1-E12 # ENET SFP RX SIGNAL LOSS TO FPGA/CPU GPIO INPUT GPIO6NB1 NET 'SFP_ENET_TRANS_ENABLE' U1-E13 # ENET SFP TX ENABLE FROM FPGA/CPU GPIO OUTPUT GPIO7NB1 NET 'SFP_ENET_RS_0' U1-D14 # TIME SFP RATE SELECT 0 <--> FPGA/CPU GPIO I/O GPIO8PB1/DQS NET 'SFP_ENET_RS_1' U1-D13 # TIME SFP RATE SELECT 1 <--> FPGA/CPU GPIO I/O GPIO8NB1/DQS # # THESE ARE 3V3 SIGNALS: I2C BUS FOR BOTH SFP MODULES AND FOR TIMING GENERATOR # CPU I2C CONTROLLER #0 SERIAL CLK & DATA # -------------------------------------------------------------------------------- NET 'CPU_I2C_CTRL_0_SCL' U1-A12 # FPGA/CPU CONTROLLER 0 I2C SCLK TO FAN-OUT GPIO17PB1/ # CCC_SE_CLKIN_S_11 NET 'CPU_I2C_CTRL_0_SDA' U1-A13 # FPGA/CPU CONTROLLER 0 I2C SDATA TO FAN-OUT GPIO17NB1 NET 'CPU_I2C_CTRL_0_FAN_OUT_RESET_B' U1-B14 # I2C FANOUT RESET_B FROM FPGA/CPU GPIO GPIO15NB1 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # STARTUP AND RESETS CONTROLLER CONNECTIONS WITH THE FPGA/CPU 10 PINS # ----------------------------------------------------------------------------- # # # THESE ARE 3V3 SIGNALS: DK_CPU_IS_AWAKE (_B) AND THE RUN SIGNALS # ----------------------------------------------------------------------- NET 'DK_CPU_IS_AWAKE' U1-A3 # CPU IS AWAKE SIGNAL GPIO173NB1 NET 'DK_CPU_IS_AWAKE_B' U1-C6 # CPU IS AWAKE_B SIGNAL GPIO175PB1 NET 'RUN_PMT_ADC' U1-D5 # LOW ---> RESET THE AD9083 PMT ADC GPIO178NB1 NET 'RUN_CLOCK_GENERATOR' U1-E5 # LOW ---> RESET THE AD9546 CLOCK GENERATOR GPIO174PB1 NET 'RUN_USB_INTERFACE' U1-E6 # LOW ---> RESET THE USB3340 USB TRANSCEIVER GPIO182NB1/DQS NET 'RUN_BB_AUDIO_ADC' U1-E7 # LOW ---> RESET THE TLV320ADC6140 BB AUDIO ADC GPIO182PB1/DQS NET 'RUN_SPARE' U1-D8 # CURRENTLY 26-DEC-2023 THIS SIGNAL IS NOT USED GPIO185NB1 NET 'RUN_BARNACLE' U1-E8 # LOW ---> BARNACLE POWER DOWN & MASTER_RESET_B GPIO185PB1 NET 'BARNACLE_CONTROL_1' U1-E10 # BARNACLE CONTROL SIGNAL 1 DEFAULT IS LOW GPIO12NB1 NET 'BARNACLE_CONTROL_2' U1-E11 # BARNACLE CONTROL SIGNAL 2 DEFAULT IS LOW GPIO12PB1 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # USB PHY REFERENCE CLOCK CONNECTIONS WITH THE FPGA/CPU 1 PIN # ------------------------------------------------------------------- # # # THESE ARE 3V3 SIGNALS: USB PHY REF CLK 26 MHZ # FROM A FPGA/CPU CCC CLOCK OUTPUT # ------------------------------------------------------------ NET 'FPGA_REF_CLK_TO_USB_PHY' U1-D6 # FPGA CLK OUTPUT TO USB PHY REF CLK INPUT GPIO178PB1/ # CCC_SW_PLL0_OUT1 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- #--------------------------------------------------------------------- #--------------------------------------------------------------------- # # # REFERENCE DATA MPFS250T-1FCVG784I BANKS: 1, 7, 9 # --------------------------------------------------------- # # # FPGA BANK 1 # ------------------- # # THERE ARE 72 PINS IN BANK 1 THIS IS A 3V3 BANK ON THE DK. # # BANK 1 PINS ARE LOCATED IN TWO GROUPS ON THE FCVG784 PACKAGE. # # # D9 GPIO0PB1/CLKIN_S_4 DDR_S_3 I/O GPIO # D10 GPIO0NB1 DDR_S_3 I/O GPIO # # B7 GPIO1PB1/CLKIN_S_5 DDR_S_3 I/O GPIO # A7 GPIO1NB1 DDR_S_3 I/O GPIO # # C8 GPIO2PB1/DQS DDR_S_3 I/O GPIO # C7 GPIO2NB1/DQS DDR_S_3 I/O GPIO # # A8 GPIO3PB1/CLKIN_S_6 DDR_S_3 I/O GPIO # A9 GPIO3NB1 DDR_S_3 I/O GPIO # # C9 GPIO4PB1/LPRB_A DDR_S_3 I/O GPIO # B9 GPIO4NB1/LPRB_B DDR_S_3 I/O GPIO # # B10 GPIO5PB1/CLKIN_S_7 DDR_S_3 I/O GPIO # A10 GPIO5NB1 DDR_S_3 I/O GPIO # # F12 GPIO6PB1 DDR_S_4 I/O GPIO # E12 GPIO6NB1 DDR_S_4 I/O GPIO # # F13 GPIO7PB1 DDR_S_4 I/O GPIO # E13 GPIO7NB1 DDR_S_4 I/O GPIO # # D14 GPIO8PB1/DQS DDR_S_4 I/O GPIO # D13 GPIO8NB1/DQS DDR_S_4 I/O GPIO # # G12 GPIO9PB1/CLKIN_S_8/ # CCC_SE_CLKIN_S_8 DDR_S_4 I/O GPIO # G11 GPIO9NB1 DDR_S_4 I/O GPIO # # F14 GPIO10PB1 DDR_S_4 I/O GPIO # G14 GPIO10NB1 DDR_S_4 I/O GPIO # # J14 GPIO11PB1/CLKIN_S_9/ # CCC_SE_CLKIN_S_9 DDR_S_4 I/O GPIO # H14 GPIO11NB1 DDR_S_4 I/O GPIO # # E11 GPIO12PB1 DDR_S_5 I/O GPIO # E10 GPIO12NB1 DDR_S_5 I/O GPIO # # B12 GPIO13PB1 DDR_S_5 I/O GPIO # B11 GPIO13NB1 DDR_S_5 I/O GPIO # # C13 GPIO14PB1/DQS DDR_S_5 I/O GPIO # C12 GPIO14NB1/DQS DDR_S_5 I/O GPIO # # C14 GPIO15PB1/ # CCC_SE_CLKIN_S_10 DDR_S_5 I/O GPIO # B14 GPIO15NB1 DDR_S_5 I/O GPIO # # D11 GPIO16PB1 DDR_S_5 I/O GPIO # C11 GPIO16NB1 DDR_S_5 I/O GPIO # # A12 GPIO17PB1/ # CCC_SE_CLKIN_S_11 DDR_S_5 I/O GPIO # A13 GPIO17NB1 DDR_S_5 I/O GPIO # # # # # C2 GPIO168PB1/CCC_SW_CLKIN_S_0 DDR_S_0 1 I/O GPIO # B2 GPIO168NB1 DDR_S_0 1 I/O GPIO # # E3 GPIO169PB1/CCC_SW_CLKIN_S_1 DDR_S_0 1 I/O GPIO # E2 GPIO169NB1 DDR_S_0 1 I/O GPIO # # E1 GPIO170PB1/DQS/CCC_SW_PLL1_OUT0 DDR_S_0 1 I/O GPIO # D1 GPIO170NB1/DQS DDR_S_0 1 I/O GPIO # # D3 GPIO171PB1/ DDR_S_0 1 I/O GPIO # CLKIN_S_2/CCC_SW_CLKIN_S_2/ # CCC_SW_PLL1_OUT0 # C3 GPIO171NB1 DDR_S_0 1 I/O GPIO # # C1 GPIO172PB1/CCC_SW_PLL1_OUT1 DDR_S_0 1 I/O GPIO # B1 GPIO172NB1 DDR_S_0 1 I/O GPIO # # A2 GPIO173PB1/CLKIN_S_3/ DDR_S_0 1 I/O GPIO # CCC_SW_CLKIN_S_3 # A3 GPIO173NB1 DDR_S_0 1 I/O GPIO # # E5 GPIO174PB1 DDR_S_1 1 I/O GPIO # F5 GPIO174NB1 DDR_S_1 1 I/O GPIO # # C6 GPIO175PB1 DDR_S_1 1 I/O GPIO # B6 GPIO175NB1 DDR_S_1 1 I/O GPIO # # D4 GPIO176PB1/DQS/CCC_SW_PLL0_OUT0 DDR_S_1 1 I/O GPIO # C4 GPIO176NB1/DQS DDR_S_1 1 I/O GPIO # # B4 GPIO177PB1/CCC_SW_PLL0_OUT0 DDR_S_1 1 I/O GPIO # A4 GPIO177NB1 DDR_S_1 1 I/O GPIO # # D6 GPIO178PB1/CCC_SW_PLL0_OUT1 DDR_S_1 1 I/O GPIO # D5 GPIO178NB1 DDR_S_1 1 I/O GPIO # # B5 GPIO179PB1 DDR_S_1 1 I/O GPIO # A5 GPIO179NB1 DDR_S_1 1 I/O GPIO # # G9 GPIO180PB1 DDR_S_2 1 I/O GPIO # F9 GPIO180NB1 DDR_S_2 1 I/O GPIO # # G7 GPIO181PB1 DDR_S_2 1 I/O GPIO # G6 GPIO181NB1 DDR_S_2 1 I/O GPIO # # E7 GPIO182PB1/DQS DDR_S_2 1 I/O GPIO # E6 GPIO182NB1/DQS DDR_S_2 1 I/O GPIO # # G10 GPIO183PB1 DDR_S_2 1 I/O GPIO # F10 GPIO183NB1 DDR_S_2 1 I/O GPIO # # F8 GPIO184PB1 DDR_S_2 1 I/O GPIO # F7 GPIO184NB1 DDR_S_2 1 I/O GPIO # # E8 GPIO185PB1 DDR_S_2 1 I/O GPIO # D8 GPIO185NB1 DDR_S_2 1 I/O GPIO # # # # # # FPGA BANK 7 # ------------------- # # THERE ARE 24 PINS IN BANK 7 THIS IS A 3V3 BANK ON THE DK. # # # K5 GPIO138NB7 DDR_W_4 I/O GPIO # K6 GPIO138PB7 DDR_W_4 I/O GPIO # # K3 GPIO139NB7 DDR_W_4 I/O GPIO # J3 GPIO139PB7/CLKIN_W_7 DDR_W_4 I/O GPIO # # J4 GPIO140NB7 DDR_W_4 I/O GPIO # J5 GPIO140PB7/CLKIN_W_6 DDR_W_4 I/O GPIO # # H4 GPIO141NB7/DQS DDR_W_4 I/O GPIO # H3 GPIO141PB7/DQS DDR_W_4 I/O GPIO # # J6 GPIO142NB7 DDR_W_4 I/O GPIO # K7 GPIO142PB7/CLKIN_W_5 DDR_W_4 I/O GPIO # # H6 GPIO143NB7 DDR_W_4 I/O GPIO # H7 GPIO143PB7/CLKIN_W_4 DDR_W_4 I/O GPIO # # K2 GPIO162NB7 DDR_W_0 I/O GPIO # K1 GPIO162PB7/CLKIN_W_3/ DDR_W_0 I/O GPIO # CCC_SW_CLKIN_W_3 # # J1 GPIO163NB7 DDR_W_0 I/O GPIO # H1 GPIO163PB7/CLKIN_W_2/ DDR_W_0 I/O GPIO # CCC_SW_CLKIN_W_2/ # CCC_SW_PLL0_OUT0 # # F3 GPIO164NB7 DDR_W_0 I/O GPIO # F4 GPIO164PB7/CLKIN_W_1/ DDR_W_0 I/O GPIO # CCC_SW_CLKIN_W_1 # # H2 GPIO165NB7/DQS DDR_W_0 I/O GPIO # G2 GPIO165PB7/DQS/ DDR_W_0 I/O GPIO # CCC_SW_PLL0_OUT0 # # G1 GPIO166NB7 DDR_W_0 I/O GPIO # F2 GPIO166PB7 DDR_W_0 I/O GPIO # # G4 GPIO167NB7 DDR_W_0 I/O GPIO # G5 GPIO167PB7/CLKIN_W_0/ DDR_W_0 I/O GPIO # CCC_SW_CLKIN_W_0 # # # # # # FPGA BANK 9 # ------------------- # # THERE ARE 84 PINS IN BANK 9 THIS IS A 1V8 BANK ON THE DK. # # # E15 GPIO18PB9 DDR_S_6 I/O GPIO # D15 GPIO18NB9 DDR_S_6 I/O GPIO # # A14 GPIO19PB9 DDR_S_6 I/O GPIO # A15 GPIO19NB9 DDR_S_6 I/O GPIO # # B15 GPIO20PB9/DQS DDR_S_6 I/O GPIO # B16 GPIO20NB9/DQS DDR_S_6 I/O GPIO # # E17 GPIO21PB9 DDR_S_6 I/O GPIO # E16 GPIO21NB9 DDR_S_6 I/O GPIO # # D16 GPIO22PB9 DDR_S_6 I/O GPIO # C16 GPIO22NB9 DDR_S_6 I/O GPIO # # C17 GPIO23PB9 DDR_S_6 I/O GPIO # B17 GPIO23NB9 DDR_S_6 I/O GPIO # # K15 GPIO24PB9 DDR_S_7 I/O GPIO # J15 GPIO24NB9 DDR_S_7 I/O GPIO # # G17 GPIO25PB9 DDR_S_7 I/O GPIO # F17 GPIO25NB9 DDR_S_7 I/O GPIO # # G16 GPIO26PB9/DQS DDR_S_7 I/O GPIO # H16 GPIO26NB9/DQS DDR_S_7 I/O GPIO # # H17 GPIO27PB9 DDR_S_7 I/O GPIO # J16 GPIO27NB9 DDR_S_7 I/O GPIO # # G15 GPIO28PB9 DDR_S_7 I/O GPIO # F15 GPIO28NB9 DDR_S_7 I/O GPIO # # K17 GPIO29PB9 DDR_S_7 I/O GPIO # K16 GPIO29NB9 DDR_S_7 I/O GPIO # # F18 GPIO30PB9 DDR_S_8 I/O GPIO # F19 GPIO30NB9 DDR_S_8 I/O GPIO # # G19 GPIO31PB9 DDR_S_8 I/O GPIO # H18 GPIO31NB9 DDR_S_8 I/O GPIO # # J18 GPIO32PB9/DQS DDR_S_8 I/O GPIO # K18 GPIO32NB9/DQS DDR_S_8 I/O GPIO # # K20 GPIO33PB9 DDR_S_8 I/O GPIO # J20 GPIO33NB9 DDR_S_8 I/O GPIO # # F20 GPIO34PB9 DDR_S_8 I/O GPIO # G20 GPIO34NB9 DDR_S_8 I/O GPIO # # H19 GPIO35PB9 DDR_S_8 I/O GPIO # J19 GPIO35NB9 DDR_S_8 I/O GPIO # # D19 GPIO42PB9 DDR_S_10 I/O GPIO # E20 GPIO42NB9 DDR_S_10 I/O GPIO # # A17 GPIO43PB9 DDR_S_10 I/O GPIO # A18 GPIO43NB9 DDR_S_10 I/O GPIO # # C18 GPIO44PB9/DQS DDR_S_10 I/O GPIO # C19 GPIO44NB9/DQS DDR_S_10 I/O GPIO # # B19 GPIO45PB9 DDR_S_10 I/O GPIO # A19 GPIO45NB9 DDR_S_10 I/O GPIO # # E18 GPIO46PB9 DDR_S_10 I/O GPIO # D18 GPIO46NB9 DDR_S_10 I/O GPIO # # B20 GPIO47PB9 DDR_S_10 I/O GPIO # A20 GPIO47NB9 DDR_S_10 I/O GPIO # # D21 GPIO48PB9 DDR_S_11 I/O GPIO # D20 GPIO48NB9 DDR_S_11 I/O GPIO # # B21 GPIO49PB9 DDR_S_11 I/O GPIO # C21 GPIO49NB9 DDR_S_11 I/O GPIO # # A22 GPIO50PB9/DQS DDR_S_11 I/O GPIO # A23 GPIO50NB9/DQS DDR_S_11 I/O GPIO # # C23 GPIO51PB9 DDR_S_11 I/O GPIO # D23 GPIO51NB9 DDR_S_11 I/O GPIO # # B22 GPIO52PB9 DDR_S_11 I/O GPIO # C22 GPIO52NB9 DDR_S_11 I/O GPIO # # A24 GPIO53PB9 DDR_S_11 I/O GPIO # A25 GPIO53NB9 DDR_S_11 I/O GPIO # # B24 GPIO54PB9 DDR_S_12 I/O GPIO # C24 GPIO54NB9 DDR_S_12 I/O GPIO # # B25 GPIO55PB9 DDR_S_12 I/O GPIO # B26 GPIO55NB9 DDR_S_12 I/O GPIO # # C27 GPIO56PB9/DQS/ DDR_S_12 I/O GPIO # CCC_SE_PLL0_OUT0 # C26 GPIO56NB9/DQS DDR_S_12 I/O GPIO # # A27 GPIO57PB9/ DDR_S_12 I/O GPIO # CLKIN_S_12/ # CCC_SE_CLKIN_S_12/ # CCC_SE_PLL0_OUT0 # B27 GPIO57NB9 DDR_S_12 I/O GPIO # # D25 GPIO58PB9/ DDR_S_12 I/O GPIO # CCC_SE_PLL0_OUT1 # D24 GPIO58NB9 DDR_S_12 I/O GPIO # # B28 GPIO59PB9/ DDR_S_12 I/O GPIO # CLKIN_S_13/ # CCC_SE_CLKIN_S_13 # C28 GPIO59NB9 DDR_S_12 I/O GPIO # # H21 GPIO60PB9 DDR_S_13 I/O GPIO # G21 GPIO60NB9 DDR_S_13 I/O GPIO # # K21 GPIO61PB9 DDR_S_13 I/O GPIO # J21 GPIO61NB9 DDR_S_13 I/O GPIO # # F22 GPIO62PB9/DQS/ DDR_S_13 I/O GPIO # CCC_SE_PLL1_OUT0 # G22 GPIO62NB9/DQS DDR_S_13 I/O GPIO # # E21 GPIO63PB9/ DDR_S_13 I/O GPIO # CCC_SE_CLKIN_S_14/ # CCC_SE_PLL1_OUT0 # E22 GPIO63NB9 DDR_S_13 I/O GPIO # # H22 GPIO64PB9/ DDR_S_13 I/O GPIO # CCC_SE_PLL1_OUT1 # G23 GPIO64NB9 DDR_S_13 I/O GPIO # # F23 GPIO65PB9/ DDR_S_13 I/O GPIO # CCC_SE_CLKIN_S_15 # E23 GPIO65NB9 DDR_S_13 I/O GPIO # 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