# # FPGA DDR4 Controller to DDR4 Memory Chips # ------ # # Address and Command Signals Net List # ---------------------------------------------- # # # Initial Rev. 10-Mar-2023 # Current Rev. 14-Mar-2023 # # # This net list holds the connections between the FPGA's DDR4 # Controller and the two DDR4 Memory Chips. The FPGA's DDR4 # Controller uses pins in the FPGA HSIO Back #0. # # The DDR4 memory chips which are assumed to be Micron # MT40A1G16 16 Gbit, 1 Gig Address by 16 Data Bits in the # 96 pin BGA package. # # U1 is the MPFS250T FPGA-CPU in the FCVG784 package # # U301 is the MT40A1G16 SDRAM for data bits 0:15 # U302 is the MT40A1G16 SDRAM for data bits 16:31 # # # The following signals have external termination resistors: # # ADRS0 through ADRS13, ADRS14_WE_B, ADRS15_CAS_B, # ADRS16_RAS_B, BA0, BA1, BG0, ODT, CLK_ENB, CS_B, # PAR_IN, ACT_B # # This is 25 termination resistors to the VTERM_DDR4_FPGA supply. # # # The CLK_DIR - CLK_CMP differential pair clock signal # has an external differential resistor terminator. # # This is 2 more termination resistors. # # # That makes for a total of 27 external termination resistors # of 39 Ohms each. # # # The ALERT_B signal has an external Pull-Up resistor # to the 1V2 rail. # # The RESET_B and TEN signals have an external Pull-Down # resistors to Ground. # # # This net list file defines: # # 30 pins on each Memory Chip # 30 pins on the DDR4 Memory Controller Bank 0 # # # Start with the Address and Control Bus that # goes to both U301 and U302. # NET 'DDR4_FPGA_ADRS0' U1-AG28 U301-P3 U302-P3 R309-2 NET 'DDR4_FPGA_ADRS1' U1-Y22 U301-P7 U302-P7 R310-2 NET 'DDR4_FPGA_ADRS2' U1-AC26 U301-R3 U302-R3 R305-2 NET 'DDR4_FPGA_ADRS3' U1-Y23 U301-N7 U302-N7 R314-2 NET 'DDR4_FPGA_ADRS4' U1-AE26 U301-N3 U302-N3 R313-2 NET 'DDR4_FPGA_ADRS5' U1-AC27 U301-P8 U302-P8 R311-2 NET 'DDR4_FPGA_ADRS6' U1-AG27 U301-P2 U302-P2 R308-2 NET 'DDR4_FPGA_ADRS7' U1-AC22 U301-R8 U302-R8 R307-2 NET 'DDR4_FPGA_ADRS8' U1-Y21 U301-R2 U302-R2 R304-2 NET 'DDR4_FPGA_ADRS9' U1-AC28 U301-R7 U302-R7 R306-2 NET 'DDR4_FPGA_ADRS10' U1-AE25 U301-M3 U302-M3 R317-2 NET 'DDR4_FPGA_ADRS11' U1-W21 U301-T2 U302-T2 R301-2 NET 'DDR4_FPGA_ADRS12' U1-AA22 U301-M7 U302-M7 R318-2 NET 'DDR4_FPGA_ADRS13' U1-AB22 U301-T8 U302-T8 R303-2 NET 'DDR4_FPGA_ADRS14_WE_B' U1-AF25 U301-L2 U302-L2 R320-2 NET 'DDR4_FPGA_ADRS15_CAS_B' U1-AF28 U301-M8 U302-M8 R319-2 NET 'DDR4_FPGA_ADRS16_RAS_B' U1-AF27 U301-L8 U302-L8 R323-2 NET 'DDR4_FPGA_BA0' U1-AD24 U301-N2 U302-N2 R312-2 NET 'DDR4_FPGA_BA1' U1-AD28 U301-N8 U302-N8 R315-2 NET 'DDR4_FPGA_BG0' U1-AF24 U301-M2 U302-M2 R316-2 NET 'DDR4_FPGA_ODT' U1-AH26 U301-K3 U302-K3 R325-2 NET 'DDR4_FPGA_CLK_DIR' U1-AB25 U301-K7 U302-K7 NET 'DDR4_FPGA_ClK_CMP' U1-AB24 U301-K8 U302-K8 NET 'DDR4_FPGA_CLK_ENB' U1-AG26 U301-K2 U302-K2 R324-2 NET 'DDR4_FPGA_CS_B' U1-AH27 U301-L7 U302-L7 R322-2 NET 'DDR4_FPGA_ALERT_B' U1-W22 U301-P9 U302-P9 NET 'DDR4_FPGA_PARITY' U1-AC24 U301-T3 U302-T3 R302-2 NET 'DDR4_FPGA_ACT_B' U1-AD25 U301-L3 U302-L3 R321-2 NET 'DDR4_FPGA_RESET_B' U1-AD21 U301-P1 U302-P1 NET 'DDR4_FPGA_TEN' U1-AA23 U301-N9 U302-N9 # # Note: the ALERT_B, RESET_B, and TEN signals # do not have termination resistors but the do have # pull-up or pull-down resistors. These connections # are made in the file: # # ddr4_fpga_bank_0_power_and_sundry_nets.txt # # # Note: the DDR4_FPGA_CLK signals do have # differential termination resistors. These # connections are made in the file: # # ddr4_fpga_bank_0_power_and_sundry_nets.txt # # # Now connect the Termination Resistors to the # DDR4_VTERM_FPGA supply and connect the # bypass capacitors for this supply to it and # to ground. # NET 'DDR4_VTERM_FPGA' R301-1 R302-1 R303-1 R304-1 R305-1 NET 'DDR4_VTERM_FPGA' R306-1 R307-1 R308-1 R309-1 R310-1 NET 'DDR4_VTERM_FPGA' R311-1 R312-1 R313-1 R314-1 R315-1 NET 'DDR4_VTERM_FPGA' R316-1 R317-1 R318-1 R319-1 R320-1 NET 'DDR4_VTERM_FPGA' R321-1 R322-1 R323-1 R324-1 R325-1 NET 'DDR4_VTERM_FPGA' C371-2 C372-2 C373-2 C374-2 C375-2 NET 'DDR4_VTERM_FPGA' C376-2 C377-2 C378-2 C379-2 C380-2 NET 'DDR4_VTERM_FPGA' C381-2 C382-2 C383-2 C384-2 NET 'GROUND' C371-1 C372-1 C373-1 C374-1 C375-1 NET 'GROUND' C376-1 C377-1 C378-1 C379-1 C380-1 NET 'GROUND' C381-1 C382-1 C383-1 C384-1 # # FPGA DDR4 Controller to DDR4 Memory Chips # ------ # # Data Path Net List # ---------------------------------------------- # # # Initial Rev. 10-Mar-2023 # Current Rev. 10-Mar-2023 # # # This net list holds the connections between the FPGA's DDR4 # Controller and the two DDR4 Memory Chips. The FPGA's DDR4 # Controller uses pins in the FPGA HSIO Back #0. # # The DDR4 memory chips which are assumed to be Micron # MT40A1G16 16 Gbit, 1 Gig Address by 16 Data Bits in the # 96 pin BGA package. # # U1 is the MPFS250T FPGA-CPU in the FCVG784 package # # U301 is the MT40A1G16 SDRAM for data bits 0:15 # U302 is the MT40A1G16 SDRAM for data bits 16:31 # # # This net list file defines: # # 22 pins on each Memory Chip # 44 pins on the DDR4 Memory Controller Bank 0 # # # Now the Data Path type signals D0:D15 to U301 # NET 'DDR4_FPGA_DQ0' U1-AG24 U301-G2 NET 'DDR4_FPGA_DQ1' U1-AE23 U301-F7 NET 'DDR4_FPGA_DQ2' U1-AF23 U301-H3 NET 'DDR4_FPGA_DQ3' U1-AH23 U301-H7 NET 'DDR4_FPGA_DQ4' U1-AH22 U301-H2 NET 'DDR4_FPGA_DQ5' U1-AG21 U301-H8 NET 'DDR4_FPGA_DQ6' U1-AH21 U301-J3 NET 'DDR4_FPGA_DQ7' U1-AF22 U301-J7 NET 'DDR4_FPGA_DQS0_DIR' U1-AE21 U301-G3 NET 'DDR4_FPGA_DQS0_CMP' U1-AE22 U301-F3 NET 'DDR4_FPGA_DM0_B' U1-AG22 U301-E7 NET 'DDR4_FPGA_DQ8' U1-AG20 U301-A3 NET 'DDR4_FPGA_DQ9' U1-AD19 U301-B8 NET 'DDR4_FPGA_DQ10' U1-AC19 U301-C3 NET 'DDR4_FPGA_DQ11' U1-AG19 U301-C7 NET 'DDR4_FPGA_DQ12' U1-AF19 U301-C2 NET 'DDR4_FPGA_DQ13' U1-AH19 U301-C8 NET 'DDR4_FPGA_DQ14' U1-AH18 U301-D3 NET 'DDR4_FPGA_DQ15' U1-AF18 U301-D7 NET 'DDR4_FPGA_DQS1_DIR' U1-AE20 U301-B7 NET 'DDR4_FPGA_DQS1_CMP' U1-AD20 U301-A7 NET 'DDR4_FPGA_DM1_B' U1-AE18 U301-E2 # # Now the Data Path type signals D16:D31 to U302 # NET 'DDR4_FPGA_DQ16' U1-AC21 U302-G2 NET 'DDR4_FPGA_DQ17' U1-AB21 U302-F7 NET 'DDR4_FPGA_DQ18' U1-Y20 U302-H3 NET 'DDR4_FPGA_DQ19' U1-W20 U302-H7 NET 'DDR4_FPGA_DQ20' U1-Y19 U302-H2 NET 'DDR4_FPGA_DQ21' U1-W19 U302-H8 NET 'DDR4_FPGA_DQ22' U1-AA19 U302-J3 NET 'DDR4_FPGA_DQ23' U1-AB19 U302-J7 NET 'DDR4_FPGA_DQS2_DIR' U1-AB20 U302-G3 NET 'DDR4_FPGA_DQS2_CMP' U1-AA20 U302-F3 NET 'DDR4_FPGA_DM2_B' U1-AA18 U302-E7 NET 'DDR4_FPGA_DQ24' U1-AE16 U302-A3 NET 'DDR4_FPGA_DQ25' U1-AD16 U302-B8 NET 'DDR4_FPGA_DQ26' U1-AC18 U302-C3 NET 'DDR4_FPGA_DQ27' U1-AD18 U302-C7 NET 'DDR4_FPGA_DQ28' U1-AH17 U302-C2 NET 'DDR4_FPGA_DQ29' U1-AG17 U302-C8 NET 'DDR4_FPGA_DQ30' U1-AH16 U302-D3 NET 'DDR4_FPGA_DQ31' U1-AG16 U302-D7 NET 'DDR4_FPGA_DQS3_DIR' U1-AE17 U302-B7 NET 'DDR4_FPGA_DQS3_CMP' U1-AF17 U302-A7 NET 'DDR4_FPGA_DM3_B' U1-AC17 U302-E2 # # FPGA Fabric DDR4 Controller to DDR4 Memory Chips # ------------- # # Power Supply and Sundry Net List # ----------------------------------------------------- # # # Initial Rev. 10-Mar-2023 # Current Rev. 1-Mar-2023 # # # This net list holds the Power and Ground connections # on each Memory Chip and 2 Sundry pins on each of # these chips. # # The DDR4 memory chips which are assumed to be Micron # MT40A1G16 16 Gbit, 1 Gig Address by 16 Data Bits in the # 96 pin BGA package. # # U1 is the MPFS250T FPGA-CPU in the FCVG784 package # # U301 is the MT40A1G16 SDRAM for data bits 0:15 # U302 is the MT40A1G16 SDRAM for data bits 16:31 # # # The ZQ signal has an external 240 Ohm resistor to # Ground - a separate resistor for each of the 2 SDRAM chips. # # # This file has 44 pins on each Memory Chip # and no pins on the DDR4 Memory Controller. # # # For the 2 Memory Chips: # # the ZQ Reference Resistors # # the Clock Termination Resistors and Capacitors # # the ALERT_B Pull-Up Resistor # # the RESET_B Pull-Down Resistor # # the TEN Pull-Down Resistor # # the Un-Used pin on each Memory Chip # NET 'ZQ_REFERENCE_U301' U301-F9 R328-2 NET 'ZQ_REFERENCE_U302' U302-F9 R329-2 NET 'GROUND' R328-1 R329-1 NET 'DDR4_FPGA_ClK_CMP' R326-2 NET 'DDR4_FPGA_CLK_DIR' R327-2 NET 'DDR4_FPGA_CLK_TERM' R326-1 R327-1 NET 'DDR4_FPGA_CLK_TERM' C385-2 C386-2 NET 'BULK_1V2' C385-1 C386-1 NET 'DDR4_FPGA_ALERT_B' R330-2 NET 'BULK_1V2' R330-1 NET 'DDR4_FPGA_RESET_B' R331-2 NET 'GROUND' R331-1 NET 'DDR4_FPGA_TEN' R332-2 NET 'GROUND' R332-1 NET 'NO_CONN_U301_PIN_T7' U301-T7 NET 'NO_CONN_U302_PIN_T7' U302-T7 # # U301 Power and Ground # NET 'BULK_1V2' U301-B3 U301-B9 U301-D1 U301-G7 U301-J1 # VDD NET 'BULK_1V2' U301-J9 U301-L1 U301-L9 U301-R1 U301-T9 NET 'BULK_1V2' U301-A1 U301-A9 U301-C1 U301-D9 U301-F2 # VDDQ NET 'BULK_1V2' U301-F8 U301-G1 U301-G9 U301-J2 U301-J8 NET 'Digital_2V5' U301-B1 U301-R9 # VPP NET 'DDR4_VREF_FPGA' U301-M1 # VREF NET 'GROUND' U301-B2 U301-E1 U301-E9 U301-G8 U301-K1 # VSS NET 'GROUND' U301-K9 U301-M9 U301-N1 U301-T1 NET 'GROUND' U301-A2 U301-A8 U301-C9 U301-D2 U301-D8 # VSSQ NET 'GROUND' U301-E3 U301-E8 U301-F1 U301-H1 U301-H9 # # U302 Power and Ground # NET 'BULK_1V2' U302-B3 U302-B9 U302-D1 U302-G7 U302-J1 # VDD NET 'BULK_1V2' U302-J9 U302-L1 U302-L9 U302-R1 U302-T9 NET 'BULK_1V2' U302-A1 U302-A9 U302-C1 U302-D9 U302-F2 # VDDQ NET 'BULK_1V2' U302-F8 U302-G1 U302-G9 U302-J2 U302-J8 NET 'Digital_2V5' U302-B1 U302-R9 # VPP NET 'DDR4_VREF_FPGA' U302-M1 # VREF NET 'GROUND' U302-B2 U302-E1 U302-E9 U302-G8 U302-K1 # VSS NET 'GROUND' U302-K9 U302-M9 U302-N1 U302-T1 NET 'GROUND' U302-A2 U302-A8 U302-C9 U302-D2 U302-D8 # VSSQ NET 'GROUND' U302-E3 U302-E8 U302-F1 U302-H1 U302-H9 # # Bypass Capacitors for U301 # NET 'BULK_1V2' C301-1 C302-1 C303-1 C304-1 C305-1 NET 'BULK_1V2' C306-1 C307-1 C308-1 C309-1 C310-1 NET 'BULK_1V2' C311-1 C312-1 C313-1 C314-1 C315-1 NET 'BULK_1V2' C316-1 C317-1 NET 'GROUND' C301-2 C302-2 C303-2 C304-2 C305-2 NET 'GROUND' C306-2 C307-2 C308-2 C309-2 C310-2 NET 'GROUND' C311-2 C312-2 C313-2 C314-2 C315-2 NET 'GROUND' C316-2 C317-2 NET 'Digital_2V5' C320-1 C321-1 C322-1 C323-1 C324-1 NET 'Digital_2V5' C325-1 NET 'GROUND' C320-2 C321-2 C322-2 C323-2 C324-2 NET 'GROUND' C325-2 NET 'DDR4_VREF_FPGA' C327-1 C328-1 C329-1 NET 'GROUND' C327-2 C328-2 C329-2 # # Bypass Capacitors for U302 # NET 'BULK_1V2' C331-1 C332-1 C333-1 C334-1 C335-1 NET 'BULK_1V2' C336-1 C337-1 C338-1 C339-1 C340-1 NET 'BULK_1V2' C341-1 C342-1 C343-1 C344-1 C345-1 NET 'BULK_1V2' C346-1 C347-1 NET 'GROUND' C331-2 C332-2 C333-2 C334-2 C335-2 NET 'GROUND' C336-2 C337-2 C338-2 C339-2 C340-2 NET 'GROUND' C341-2 C342-2 C343-2 C344-2 C345-2 NET 'GROUND' C346-2 C347-2 NET 'Digital_2V5' C350-1 C351-1 C352-1 C353-1 C354-1 NET 'Digital_2V5' C355-1 NET 'GROUND' C350-2 C351-2 C352-2 C353-2 C354-2 NET 'GROUND' C355-2 NET 'DDR4_VREF_FPGA' C357-1 C358-1 C359-1 NET 'GROUND' C357-2 C358-2 C359-2 # # FPGA DDR4 Controller to DDR4 Memory Chips # ------ # # FPGA Bank 0 No Connection Net List # ------------------------------------------------ # # # Initial Rev. 10-Mar-2023 # Current Rev. 13-Mar-2023 # # # This net list holds the pins in the FPGA BANK 0 # DDR Controller that have No Connection when this # DDR Controller is used with DDR4 Memory Chips. # # # # Un-Used Pins in the U1 FPGA's Bank 0 # i.e. the DDR Controller. # # These pins are declared as "Single Pin Nets". # # We are using BANK 0 pins for the FPGA's DDR4 Controller # with 32 Data Bits and One Rank. Microchip may call this # the North-NE Option 1. # # These BANK 0 pins are used with some other DDR4 options, e.g. # bus widths > 32 bits, North-NW option, and Option 2. # # This net list file holds 10 pins in the Bank 0 DDR Memory Controller. # NET 'NO_CONN_U1_PIN_AC16' U1-AC16 # DQ16 for North_NW Option 1 & 2 NET 'NO_CONN_U1_PIN_AC23' U1-AC23 # DQ60 for North_NW Option 1 & 2 NET 'NO_CONN_U1_PIN_AD23' U1-AD23 # CS1_B for North-NE Option 2 NET 'NO_CONN_U1_PIN_AD26' U1-AD26 # BG1 for North_NE Option 1 & 2 # DQ66 for North-NW Option 1 & 2 NET 'NO_CONN_U1_PIN_AE27' U1-AE27 # DQS8 for North-NW Option 1 & 2 # CK1 for North-NE Option 2 NET 'NO_CONN_U1_PIN_AE28' U1-AE28 # DQS8_B for North-NW Option 1 & 2 # CK1_B for North-NE Option 2 NET 'NO_CONN_U1_PIN_AF20' U1-AF20 # DQ39 for North-NW Option 1 & 2 NET 'NO_CONN_U1_PIN_AG25' U1-AG25 # DQ48 for North-NW Option 1 & 2 # CKE1 for North-NE Option 2 NET 'NO_CONN_U1_PIN_AH24' U1-AH24 # DQ47 for North-NW Option 1 & 2 NET 'NO_CONN_U1_PIN_Y18' U1-Y18 # DQ24 for North-NW Option 1 & 2 # # CPU DDR4 Controller to DDR4 Memory Chips # ----- # # Address and Command Signals Net List # --------------------------------------------- # # # Initial Rev. 29-Dec-2022 # Current Rev. 14-Mar-2023 # # # This net list holds the connections between the CPU's DDR4 # Controller and the two DDR4 Memory Chips. The CPU's DDR4 # Controller uses pins in the CPU HSIO Back #6. # # The DDR4 memory chips which are assumed to be Micron # MT40A1G16 16 Gbit, 1 Gig Address by 16 Data Bits in the # 96 pin BGA package. # # U1 is the MPFS250T FPGA-CPU in the FCVG784 package # # U401 is the MT40A1G16 SDRAM for data bits 0:15 # U402 is the MT40A1G16 SDRAM for data bits 16:31 # # # The following signals have external termination resistors: # # ADRS0 through ADRS13, ADRS14_WE_B, ADRS15_CAS_B, # ADRS16_RAS_B, BA0, BA1, BG0, ODT, CLK_ENB, CS_B, # PAR_IN, ACT_B # # This is 25 termination resistors to the VTERM_DDR4_CPU supply. # # # The CLK_DIR - CLK_CMP differential pair clock signal # has an external differential resistor terminator. # # This is 2 more termination resistors. # # # That makes for a total of 27 external termination resistors # of 39 Ohms each. # # # The ALERT_B signal has an external Pull-Up resistor # to the 1V2 rail. # # The RESET_B and TEN signals have an external Pull-Down # resistors to Ground. # # # This net list file defines: # # 30 pins on each Memory Chip # 29 pins on the DDR4 Memory Controller Bank 6 # # # Start with the Address and Control Bus that # goes to both U401 and U402. # NET 'DDR4_CPU_ADRS0' U1-V1 U401-P3 U402-P3 R409-2 NET 'DDR4_CPU_ADRS1' U1-V2 U401-P7 U402-P7 R410-2 NET 'DDR4_CPU_ADRS2' U1-Y1 U401-R3 U402-R3 R405-2 NET 'DDR4_CPU_ADRS3' U1-W1 U401-N7 U402-N7 R414-2 NET 'DDR4_CPU_ADRS4' U1-W3 U401-N3 U402-N3 R413-2 NET 'DDR4_CPU_ADRS5' U1-W4 U401-P8 U402-P8 R411-2 NET 'DDR4_CPU_ADRS6' U1-W5 U401-P2 U402-P2 R408-2 NET 'DDR4_CPU_ADRS7' U1-Y6 U401-R8 U402-R8 R407-2 NET 'DDR4_CPU_ADRS8' U1-W6 U401-R2 U402-R2 R404-2 NET 'DDR4_CPU_ADRS9' U1-Y5 U401-R7 U402-R7 R406-2 NET 'DDR4_CPU_ADRS10' U1-V9 U401-M3 U402-M3 R417-2 NET 'DDR4_CPU_ADRS11' U1-U9 U401-T2 U402-T2 R401-2 NET 'DDR4_CPU_ADRS12' U1-V7 U401-M7 U402-M7 R418-2 NET 'DDR4_CPU_ADRS13' U1-V8 U401-T8 U402-T8 R403-2 NET 'DDR4_CPU_ADRS14_WE_B' U1-T7 U401-L2 U402-L2 R420-2 NET 'DDR4_CPU_ADRS15_CAS_B' U1-U7 U401-M8 U402-M8 R419-2 NET 'DDR4_CPU_ADRS16_RAS_B' U1-U10 U401-L8 U402-L8 R423-2 NET 'DDR4_CPU_BA0' U1-U11 U401-N2 U402-N2 R412-2 NET 'DDR4_CPU_BA1' U1-W10 U401-N8 U402-N8 R415-2 NET 'DDR4_CPU_BG0' U1-U2 U401-M2 U402-M2 R416-2 NET 'DDR4_CPU_ODT' U1-V3 U401-K3 U402-K3 R425-2 NET 'DDR4_CPU_CLK_DIR' U1-Y3 U401-K7 U402-K7 NET 'DDR4_CPU_ClK_CMP' U1-Y2 U401-K8 U402-K8 NET 'DDR4_CPU_CLK_ENB' U1-V4 U401-K2 U402-K2 R424-2 NET 'DDR4_CPU_CS_B' U1-T4 U401-L7 U402-L7 R422-2 NET 'DDR4_CPU_ALERT_B' U1-V6 U401-P9 U402-P9 NET 'DDR4_CPU_PARITY' U1-U6 U401-T3 U402-T3 R402-2 NET 'DDR4_CPU_ACT_B' U1-U5 U401-L3 U402-L3 R421-2 NET 'DDR4_CPU_RESET_B' U1-U1 U401-P1 U402-P1 NET 'DDR4_CPU_TEN' U401-N9 U402-N9 # NOT Driven ? # # Note: the CPU (MSS) DDR4 Controller in # the MPFS250T does not appear to generate # a TEN signal. MUST Verify. # TEN is the High Active Test Enable signal. # # # Note: the ALERT_B, RESET_B, and TEN signals # do not have termination resistors but the do have # pull-up or pull-down resistors. These connections # are made in the file: # # ddr4_cpu_bank_6_power_and_sundry_nets.txt # # # Note: the DDR4_CPU_CLK signals do have # differential termination resistors. These # connections are made in the file: # # ddr4_cpu_bank_6_power_and_sundry_nets.txt # # # Now connect the Termination Resistors to the # DDR4_VTERM_CPU supply and connect the # bypass capacitors for this supply to it and # to ground. # NET 'DDR4_VTERM_CPU' R401-1 R402-1 R403-1 R404-1 R405-1 NET 'DDR4_VTERM_CPU' R406-1 R407-1 R408-1 R409-1 R410-1 NET 'DDR4_VTERM_CPU' R411-1 R412-1 R413-1 R414-1 R415-1 NET 'DDR4_VTERM_CPU' R416-1 R417-1 R418-1 R419-1 R420-1 NET 'DDR4_VTERM_CPU' R421-1 R422-1 R423-1 R424-1 R425-1 NET 'DDR4_VTERM_CPU' C471-2 C472-2 C473-2 C474-2 C475-2 NET 'DDR4_VTERM_CPU' C476-2 C477-2 C478-2 C479-2 C480-2 NET 'DDR4_VTERM_CPU' C481-2 C482-2 C483-2 C484-2 NET 'GROUND' C471-1 C472-1 C473-1 C474-1 C475-1 NET 'GROUND' C476-1 C477-1 C478-1 C479-1 C480-1 NET 'GROUND' C481-1 C482-1 C483-1 C484-1 # # CPU DDR4 Controller to DDR4 Memory Chips # ----- # Data Path Net List # --------------------------------------------- # # # Initial Rev. 29-Dec-2022 # Current Rev. 8-Mar-2023 # # # This net list holds the connections between the CPU's DDR4 # Controller and the two DDR4 Memory Chips. The CPU's DDR4 # Controller uses pins in the CPU HSIO Back #6. # # The DDR4 memory chips which are assumed to be Micron # MT40A1G16 16 Gbit, 1 Gig Address by 16 Data Bits in the # 96 pin BGA package. # # U1 is the MPFS250T FPGA-CPU in the FCVG784 package # # U401 is the MT40A1G16 SDRAM for data bits 0:15 # U402 is the MT40A1G16 SDRAM for data bits 16:31 # # # This net list file defines: # # 22 pins on each Memory Chip # 44 pins on the DDR4 Memory Controller Bank 6 # # # Now the Data Path type signals D0:D15 to U401 # NET 'DDR4_CPU_DQ0' U1-AB5 U401-G2 NET 'DDR4_CPU_DQ1' U1-AB4 U401-F7 NET 'DDR4_CPU_DQ2' U1-AA4 U401-H3 NET 'DDR4_CPU_DQ3' U1-AA3 U401-H7 NET 'DDR4_CPU_DQ4' U1-AA2 U401-H2 NET 'DDR4_CPU_DQ5' U1-AC4 U401-H8 NET 'DDR4_CPU_DQ6' U1-AC1 U401-J3 NET 'DDR4_CPU_DQ7' U1-AC2 U401-J7 NET 'DDR4_CPU_DQS0_DIR' U1-AB2 U401-G3 NET 'DDR4_CPU_DQS0_CMP' U1-AB1 U401-F3 NET 'DDR4_CPU_DM0_B' U1-AC3 U401-E7 NET 'DDR4_CPU_DQ8' U1-AB7 U401-A3 NET 'DDR4_CPU_DQ9' U1-AC6 U401-B8 NET 'DDR4_CPU_DQ10' U1-AC7 U401-C3 NET 'DDR4_CPU_DQ11' U1-AA5 U401-C7 NET 'DDR4_CPU_DQ12' U1-AB6 U401-C2 NET 'DDR4_CPU_DQ13' U1-AC8 U401-C8 NET 'DDR4_CPU_DQ14' U1-AA9 U401-D3 NET 'DDR4_CPU_DQ15' U1-AB9 U401-D7 NET 'DDR4_CPU_DQS1_DIR' U1-AA7 U401-B7 NET 'DDR4_CPU_DQS1_CMP' U1-AA8 U401-A7 NET 'DDR4_CPU_DM1_B' U1-AC9 U401-E2 # # Now the Data Path type signals D16:D31 to U402 # NET 'DDR4_CPU_DQ16' U1-AD6 U402-G2 NET 'DDR4_CPU_DQ17' U1-AE5 U402-F7 NET 'DDR4_CPU_DQ18' U1-AD5 U402-H3 NET 'DDR4_CPU_DQ19' U1-AD4 U402-H7 NET 'DDR4_CPU_DQ20' U1-AF5 U402-H2 NET 'DDR4_CPU_DQ21' U1-AE6 U402-H8 NET 'DDR4_CPU_DQ22' U1-AE2 U402-J3 NET 'DDR4_CPU_DQ23' U1-AD1 U402-J7 NET 'DDR4_CPU_DQS2_DIR' U1-AD3 U402-G3 NET 'DDR4_CPU_DQS2_CMP' U1-AE3 U402-F3 NET 'DDR4_CPU_DM2_B' U1-AE1 U402-E7 NET 'DDR4_CPU_DQ24' U1-AF4 U402-A3 NET 'DDR4_CPU_DQ25' U1-AF3 U402-B8 NET 'DDR4_CPU_DQ26' U1-AF1 U402-C3 NET 'DDR4_CPU_DQ27' U1-AG1 U402-C7 NET 'DDR4_CPU_DQ28' U1-AH2 U402-C2 NET 'DDR4_CPU_DQ29' U1-AH3 U402-C8 NET 'DDR4_CPU_DQ30' U1-AG5 U402-D3 NET 'DDR4_CPU_DQ31' U1-AG4 U402-D7 NET 'DDR4_CPU_DQS3_DIR' U1-AF2 U402-B7 NET 'DDR4_CPU_DQS3_CMP' U1-AG2 U402-A7 NET 'DDR4_CPU_DM3_B' U1-AH4 U402-E2 # # CPU DDR4 Controller to DDR4 Memory Chips # ----- # # Power Supply and Sundry Net List # --------------------------------------------- # # # Initial Rev. 29-Dec-2022 # Current Rev. 1-Dec-2023 # # # This net list holds the Power and Ground connections # on each Memory Chip and 2 Sundry pins on each of # these chips. # # The DDR4 memory chips which are assumed to be Micron # MT40A1G16 16 Gbit, 1 Gig Address by 16 Data Bits in the # 96 pin BGA package. # # U1 is the MPFS250T FPGA-CPU in the FCVG784 package # # U401 is the MT40A1G16 SDRAM for data bits 0:15 # U402 is the MT40A1G16 SDRAM for data bits 16:31 # # # The ZQ signal has an external 240 Ohm resistor to # Ground - a separate resistor for each of the 2 SDRAM chips. # # # This file has 44 pin on each Memory Chip # and no pins on the DDR4 Memory Controller. # # # For the 2 Memory Chips: # # the ZQ Reference Resistors # # the Clock Termination Resistors and Capacitors # # the ALERT_B Pull-Up Resistor # # the RESET_B Pull-Down Resistor # # the TEN Pull-Down Resistor # # the Un-Used pin on each Memory Chip # NET 'ZQ_REFERENCE_U401' U401-F9 R428-2 NET 'ZQ_REFERENCE_U402' U402-F9 R429-2 NET 'GROUND' R428-1 R429-1 NET 'DDR4_CPU_ClK_CMP' R426-2 NET 'DDR4_CPU_CLK_DIR' R427-2 NET 'DDR4_CPU_CLK_TERM' R426-1 R427-1 NET 'DDR4_CPU_CLK_TERM' C485-2 C486-2 NET 'BULK_1V2' C485-1 C486-1 NET 'DDR4_CPU_ALERT_B' R430-2 NET 'BULK_1V2' R430-1 NET 'DDR4_CPU_RESET_B' R431-2 NET 'GROUND' R431-1 NET 'DDR4_CPU_TEN' R432-2 NET 'GROUND' R432-1 NET 'NO_CONN_U401_PIN_T7' U401-T7 NET 'NO_CONN_U402_PIN_T7' U402-T7 # # U401 Power and Ground # NET 'BULK_1V2' U401-B3 U401-B9 U401-D1 U401-G7 U401-J1 # VDD NET 'BULK_1V2' U401-J9 U401-L1 U401-L9 U401-R1 U401-T9 NET 'BULK_1V2' U401-A1 U401-A9 U401-C1 U401-D9 U401-F2 # VDDQ NET 'BULK_1V2' U401-F8 U401-G1 U401-G9 U401-J2 U401-J8 NET 'Digital_2V5' U401-B1 U401-R9 # VPP NET 'DDR4_VREF_CPU' U401-M1 # VREF NET 'GROUND' U401-B2 U401-E1 U401-E9 U401-G8 U401-K1 # VSS NET 'GROUND' U401-K9 U401-M9 U401-N1 U401-T1 NET 'GROUND' U401-A2 U401-A8 U401-C9 U401-D2 U401-D8 # VSSQ NET 'GROUND' U401-E3 U401-E8 U401-F1 U401-H1 U401-H9 # # U402 Power and Ground # NET 'BULK_1V2' U402-B3 U402-B9 U402-D1 U402-G7 U402-J1 # VDD NET 'BULK_1V2' U402-J9 U402-L1 U402-L9 U402-R1 U402-T9 NET 'BULK_1V2' U402-A1 U402-A9 U402-C1 U402-D9 U402-F2 # VDDQ NET 'BULK_1V2' U402-F8 U402-G1 U402-G9 U402-J2 U402-J8 NET 'Digital_2V5' U402-B1 U402-R9 # VPP NET 'DDR4_VREF_CPU' U402-M1 # VREF NET 'GROUND' U402-B2 U402-E1 U402-E9 U402-G8 U402-K1 # VSS NET 'GROUND' U402-K9 U402-M9 U402-N1 U402-T1 NET 'GROUND' U402-A2 U402-A8 U402-C9 U402-D2 U402-D8 # VSSQ NET 'GROUND' U402-E3 U402-E8 U402-F1 U402-H1 U402-H9 # # Bypass Capacitors for U401 # NET 'BULK_1V2' C401-1 C402-1 C403-1 C404-1 C405-1 NET 'BULK_1V2' C406-1 C407-1 C408-1 C409-1 C410-1 NET 'BULK_1V2' C411-1 C412-1 C413-1 C414-1 C415-1 NET 'BULK_1V2' C416-1 C417-1 NET 'GROUND' C401-2 C402-2 C403-2 C404-2 C405-2 NET 'GROUND' C406-2 C407-2 C408-2 C409-2 C410-2 NET 'GROUND' C411-2 C412-2 C413-2 C414-2 C415-2 NET 'GROUND' C416-2 C417-2 NET 'Digital_2V5' C420-1 C421-1 C422-1 C423-1 C424-1 NET 'Digital_2V5' C425-1 NET 'GROUND' C420-2 C421-2 C422-2 C423-2 C424-2 NET 'GROUND' C425-2 NET 'DDR4_VREF_CPU' C427-1 C428-1 C429-1 NET 'GROUND' C427-2 C428-2 C429-2 # # Bypass Capacitors for U402 # NET 'BULK_1V2' C431-1 C432-1 C433-1 C434-1 C435-1 NET 'BULK_1V2' C436-1 C437-1 C438-1 C439-1 C440-1 NET 'BULK_1V2' C441-1 C442-1 C443-1 C444-1 C445-1 NET 'BULK_1V2' C446-1 C447-1 NET 'GROUND' C431-2 C432-2 C433-2 C434-2 C435-2 NET 'GROUND' C436-2 C437-2 C438-2 C439-2 C440-2 NET 'GROUND' C441-2 C442-2 C443-2 C444-2 C445-2 NET 'GROUND' C446-2 C447-2 NET 'Digital_2V5' C450-1 C451-1 C452-1 C453-1 C454-1 NET 'Digital_2V5' C455-1 NET 'GROUND' C450-2 C451-2 C452-2 C453-2 C454-2 NET 'GROUND' C455-2 NET 'DDR4_VREF_CPU' C457-1 C458-1 C459-1 NET 'GROUND' C457-2 C458-2 C459-2 # # CPU DDR4 Controller to DDR4 Memory Chips # ----- # # CPU (MSS) Bank 6 No Connection Net List # ----------------------------------------------- # # # Initial Rev. 29-Dec-2022 # Current Rev. 8-Mar-2023 # # # This net list holds the pins in the CPU (MSS) # BANK 6 DDR Controller that have No Connection # when this DDR Controller is used with DDR4 Memory Chips. # # # # Un-Used Pins in the U1 CPU's Bank 6 # i.e. the DDR Controller. # # These pins are declared as "Single Pin Nets". # # This net list file holds 15 pins in the Bank 6 DDR Memory Controller. # # # Pins for a Second Rank of memory chips. # NET 'NO_CONN_U1_PIN_U4' U1-U4 # CPU DDR4 Controller BG1 pin U4 NET 'NO_CONN_U1_PIN_T5' U1-T5 # CPU DDR4 Controller ODT1 pin T5 NET 'NO_CONN_U1_PIN_W8' U1-W8 # CPU DDR4 Controller CLK1_P pin W8 NET 'NO_CONN_U1_PIN_W9' U1-W9 # CPU DDR4 Controller CLK1_N pin W9 NET 'NO_CONN_U1_PIN_T2' U1-T2 # CPU DDR4 Controller CKE1 pin T2 NET 'NO_CONN_U1_PIN_T3' U1-T3 # CPU DDR4 Controller CS1_n pin T3 # # Pin for a Error Checking Correcting memory system. # NET 'NO_CONN_U1_PIN_AB10' U1-AB10 # CPU DDR4 Controller DQ0_ECC pin AB10 NET 'NO_CONN_U1_PIN_AB11' U1-AB11 # CPU DDR4 Controller DQ1_ECC pin AB11 NET 'NO_CONN_U1_PIN_AA10' U1-AA10 # CPU DDR4 Controller DQ2_ECC pin AA10 NET 'NO_CONN_U1_PIN_Y11' U1-Y11 # CPU DDR4 Controller DQ3_ECC pin Y11 NET 'NO_CONN_U1_PIN_Y7' U1-Y7 # CPU DDR4 Controller DQSP_ECC pin Y7 NET 'NO_CONN_U1_PIN_Y8' U1-Y8 # CPU DDR4 Controller DQSN_ECC pin Y8 NET 'NO_CONN_U1_PIN_W11' U1-W11 # CPU DDR4 Controller DQM_ECC/DBI_ECC pin W11 # # Other Un-Used Pins in the CPU DDR Controller Bank 6 # NET 'NO_CONN_U1_PIN_V11' U1-V11 # CPU DDR4 Controller MSS_DDR3_WE_N NET 'NO_CONN_U1_PIN_Y10' U1-Y10 # CPU DDR4 Controller MSS_DDR_VREF_IN # # FPGA DDR4 Reference and Terminator # ------ # # Power Supply Net List # ------------------------------------------ # # # Initial Rev. 13-Mar-2023 # Current Rev. 15-Nov-2023 # # # This net list holds the Reference and Terminator # Power Supply nets for the FPGA DDR4 Memory. # ------ # # These nets involve Reference Designators starting at 1921. # # # Aux Power Vin to this power supply chip: # NET 'BULK_3V3' U1921-10 C1921-1 C1922-2 NET 'BULK_3V3' U1921-7 # Enable Pin NET 'GROUND' C1921-2 C1922-1 # # VLD0 Input Power to this power supply chip: # NET 'BULK_1V2' U1921-2 C1923-1 C1924-1 NET 'GROUND' C1923-2 C1924-2 # # Terminator Power Output from this power supply chip: # and its Remote Sense input: NET 'DDR4_VTERM_FPGA' U1921-3 C1925-1 C1926-2 # Terminator Output Power NET 'GROUND' C1925-2 C1926-1 NET 'DDR4_VTERM_FPGA' U1921-5 # Remote Sense Input # # Reference Output from this power supply chip: # NET 'DDR4_VREF_FPGA' U1921-6 C1927-1 # Reference Output NET 'GROUND' C1927-2 # # Reference Input to this power supply chip: # NET 'BULK_1V2' R1921-2 NET 'Ref_to_FPGA_Term_Supply' R1921-1 R1922-2 C1928-2 U1921-1 NET 'GROUND' R1922-1 C1928-1 # # Ground Pins on the FPGA DDR4 Term Ref Power Supply Chip # NET 'GROUND' U1921-4 U1921-8 NET 'GROUND' U1921-11 U1921-12 U1921-13 U1921-14 # # Voltage Monitor for the FPGA DDR4 Term Ref Power Supply # NET 'DDR4_VTERM_FPGA' R1923-2 NET 'VMON_FPGA_DDR4_TERM' R1923-1 C1929-1 NET 'GROUND' C1929-2 # # Un-Used Pin on the Power Supply Chip # NET 'No_Conn_U1921_pin_9' U1921-9 # Power Good OD Output Pin # # CPU DDR4 Reference and Terminator # ----- # # Power Supply Net List # ----------------------------------------- # # # Initial Rev. 13-Mar-2023 # Current Rev. 15-Nov-2023 # # # This net list holds the Reference and Terminator # Power Supply nets for the CPU DDR4 Memory. # ----- # # These nets involve Reference Designators starting at 1941. # # # Aux Power Vin to this power supply chip: # NET 'BULK_3V3' U1941-10 C1941-1 C1942-2 NET 'BULK_3V3' U1941-7 # Enable Pin NET 'GROUND' C1941-2 C1942-1 # # VLD0 Input Power to this power supply chip: # NET 'BULK_1V2' U1941-2 C1943-1 C1944-1 NET 'GROUND' C1943-2 C1944-2 # # Terminator Power Output from this power supply chip: # and its Remote Sense input: NET 'DDR4_VTERM_CPU' U1941-3 C1945-1 C1946-2 # Terminator Output Power NET 'GROUND' C1945-2 C1946-1 NET 'DDR4_VTERM_CPU' U1941-5 # Remote Sense Input # # Reference Output from this power supply chip: # NET 'DDR4_VREF_CPU' U1941-6 C1947-1 # Reference Output NET 'GROUND' C1947-2 # # Reference Input to this power supply chip: # NET 'BULK_1V2' R1941-2 NET 'Ref_to_CPU_Term_Supply' R1941-1 R1942-2 C1948-2 U1941-1 NET 'GROUND' R1942-1 C1948-1 # # Ground Pins on the CPU DDR4 Term Ref Power Supply Chip # NET 'GROUND' U1941-4 U1941-8 NET 'GROUND' U1941-11 U1941-12 U1941-13 U1941-14 # # Voltage Monitor for the CPU DDR4 Term Ref Power Supply # NET 'DDR4_VTERM_CPU' R1943-2 NET 'VMON_CPU_DDR4_TERM' R1943-1 C1949-1 NET 'GROUND' C1949-2 # # Un-Used Pin on the Power Supply Chip # NET 'No_Conn_U1941_pin_9' U1941-9 # Power Good OD Output Pin # # PMT ADC High Speed Serial Links to # the FPGA High Speed Serial Transceivers # ----------------------------------------- # # # Original Rev. 29-Dec-2022 # Current Rev. 22-Feb-2022 # # # This Net List file gives the four JESD204B links from # the PMT ADC to four High-Speed Transceivers on the FPGA. # # # ADC High-Speed Serial Data Input to the FPGA: # --------------------------------------------- # # The high-speed serial data from the PMT ADC is carried # on four JESD204B links. These links are received by # four high-speed serial receivers in the FPGA-CPU. # For pcb routing it looks best to use the receivers in # high-speed transceiver number 1. # # ADC SEROUT0_DIR D2 to FPGA XCVR_1_RX0_DIR F26 # ADC SEROUT0_CMP D1 to FPGA XCVR_1_RX0_CMP F25 # # ADC SEROUT1_DIR E2 to FPGA XCVR_1_RX1_DIR H26 # ADC SEROUT1_CMP E1 to FPGA XCVR_1_RX1_CMP H25 # # ADC SEROUT2_DIR F2 to FPGA XCVR_1_RX2_DIR K26 # ADC SEROUT2_CMP F1 to FPGA XCVR_1_RX2_CMP K25 # # ADC SEROUT3_DIR G2 to FPGA XCVR_1_RX3_DIR N28 # ADC SEROUT3_CMP G1 to FPGA XCVR_1_RX3_CMP N27 # # This routing does not have any lane cross-overs # and the pins of XCVR_1 look more isolated than # the pins of XCVR_0. # NET 'ADC_SEROUT0_DIR' C671-2 # ADC Lane 0 Out Dir NET 'FPGA_XCVR_1_RX0_DIR' C671-1 U1-F26 # FPGA XCVR_1_RX0_DIR NET 'ADC_SEROUT0_CMP' C672-2 # ADC Lane 0 Out CMP NET 'FPGA_XCVR_1_RX0_CMP' C672-1 U1-F25 # FPGA XCVR_1_RX0_CMP NET 'ADC_SEROUT1_DIR' C673-2 # ADC Lane 1 Out Dir NET 'FPGA_XCVR_1_RX1_DIR' C673-1 U1-H26 # FPGA XCVR_1_RX1_DIR NET 'ADC_SEROUT1_CMP' C674-2 # ADC Lane 1 Out CMP NET 'FPGA_XCVR_1_RX1_CMP' C674-1 U1-H25 # FPGA XCVR_1_RX1_CMP NET 'ADC_SEROUT2_DIR' C675-2 # ADC Lane 2 Out Dir NET 'FPGA_XCVR_1_RX2_DIR' C675-1 U1-K26 # FPGA XCVR_1_RX2_DIR NET 'ADC_SEROUT2_CMP' C676-2 # ADC Lane 2 Out CMP NET 'FPGA_XCVR_1_RX2_CMP' C676-1 U1-K25 # FPGA XCVR_1_RX2_CMP NET 'ADC_SEROUT3_DIR' C677-2 # ADC Lane 3 Out Dir NET 'FPGA_XCVR_1_RX3_DIR' C677-1 U1-N28 # FPGA XCVR_1_RX3_DIR NET 'ADC_SEROUT3_CMP' C678-2 # ADC Lane 3 Out CMP NET 'FPGA_XCVR_1_RX3_CMP' C678-1 U1-N27 # FPGA XCVR_1_RX3_CMP # # Power and Ground Connections to the U1 FPGA # which is a: MPFS250T-1FCVG784I # # # Original Rev. 17-Nov-2022 # Current Rev. 1-Dec-2023 # # # This net list file includes: # # - All Power and Ground connections to the U1 FPGA/CPU # # - and the "Tie-Off" Resistors for the Power Pins of the Un-Used Banks # # # # FPGA/CPU Core Power Pins: # --------------------------- # # # VDD Core Supply 1.00 / 1.05 V 23 pins # NET 'CORE_1V05' U1-M15 U1-M17 U1-M19 U1-M21 U1-N16 NET 'CORE_1V05' U1-N18 U1-N20 U1-N22 U1-P15 U1-P17 NET 'CORE_1V05' U1-P19 U1-P21 U1-R14 U1-R16 U1-R20 NET 'CORE_1V05' U1-R22 U1-T15 U1-T17 U1-T19 U1-T21 NET 'CORE_1V05' U1-U14 U1-U16 U1-U20 # # VDD18 Programming and HSIO Banks AUX 1.8 V 10 pins # NET 'FPGA_1V8' U1-U18 U1-U22 U1-V13 U1-V15 U1-V17 NET 'FPGA_1V8' U1-V19 U1-V21 U1-W12 U1-W13 U1-W16 # # VDD25 PLL and PNVM Supply 2.5 V 5 pins # NET 'Analog_2V5' U1-K22 U1-L12 U1-R18 U1-U12 U1-W23 # # # High-Speed Serial Transceiver Power Pins: # -------------------------------------------- # # # XCVR_VREF XCVR Reference Supply 0.9 / 1.25 V 2 pins # # XCVR_VREF is not used - it is Tied-Off below. # NET 'XCVR_VREF' U1-G24 U1-H23 # # VDD_XCVR_CLK XCVR Ref Clk Supply 2.5 / 3.3 V 4 pins # NET 'Analog_2V5' U1-G25 U1-K23 U1-P23 U1-W25 # # VDDA25 XCVR PLL Supply 2.5 V 4 pins # NET 'Analog_2V5' U1-J25 U1-M23 U1-T23 U1-U25 # #VDDA XCVR Tx/Rx Lanes Supply 1.0 / 1.05 V 10 pins # NET 'XCVR_1V05' U1-H27 U1-K27 U1-L25 U1-M27 U1-N25 NET 'XCVR_1V05' U1-P27 U1-R25 U1-T27 U1-V27 U1-Y27 # # # IO Bank Power Supply Pins: # --------------------------- # # # VDDI0 FPGA HSIO Bank 0 1.2 / 1.35 / 1.5 / 1.8 V 10 pins # NET 'BULK_1V2' U1-AA21 U1-AB18 U1-AC25 U1-AD22 U1-AE19 NET 'BULK_1V2' U1-AF16 U1-AF26 U1-AG23 U1-AH20 U1-W18 # # VDDI1 FPGA GPIO Bank 1 1.2/1.5/1.8/2.5/3.3 V 11 pins # NET 'BULK_3V3' U1-A1 U1-A11 U1-B8 U1-C5 U1-D12 NET 'BULK_3V3' U1-D2 U1-E9 U1-F6 U1-G13 U1-H10 NET 'BULK_3V3' U1-K14 # # VDDI2 MSS I/O Bank 2 1.2/1.5/1.8/2.5/3.3 V 3 pins # NET 'BULK_3V3' U1-L1 U1-L11 U1-M8 # # VDDI3 JTAG Bank 1.8 / 2.5 / 3.3 V 2 pins # NET 'BULK_3V3' U1-K11 U1-L15 # # VDDI4 MSS I/O Bank 4 1.2/1.5/1.8/2.5/3.3 V 2 pins # # VDDI4 is not used - it is Tied-Off below. # NET 'FPGA_VDDI4' U1-N5 U1-P2 # # VDDI5 MSS SGMII Bank 5 2.5 / 3.3 V 2 pins # NET 'BULK_3V3' U1-R9 U1-T11 # # VDDI6 MSS DDR Bank 6 1.2 / 1.5 / 1.6 V 11 pins # NET 'BULK_1V2' U1-AA1 U1-AA11 U1-AB8 U1-AC5 U1-AD2 NET 'BULK_1V2' U1-AG3 U1-T6 U1-U3 U1-V10 U1-W7 NET 'BULK_1V2' U1-Y4 # # VDDI7 FPGA GPIO Bank 7 1.2/1.5/1.8/2.5/3.3 V 3 pins # NET 'BULK_3V3' U1-G3 U1-J7 U1-K4 # # VDDI8 FPGA HSIO Bank 8 1.2 / 1.35 / 1.5 / 1.8 V 8 pins # # VDDI8 is not used - it is Tied-Off below. # NET 'FPGA_VDDI8' U1-AA16 U1-AC15 U1-AD12 U1-AE9 U1-AF6 NET 'FPGA_VDDI8' U1-AG13 U1-AH10 U1-W14 # # VDDI9 FPGA GPIO Bank 9 1.2/1.5/1.8/2.5/3.3 V 10 pins # NET 'FPGA_1V8' U1-A21 U1-B18 U1-C15 U1-C25 U1-D22 NET 'FPGA_1V8' U1-E19 U1-F16 U1-H20 U1-J17 U1-J22 # # # IO Bank Auxiliary Power Supply Pins: # ------------------------------------- # # # VDDAUX1 FPGA GPIO Bank 1 2.5 / 3.3 V 3 pins # NET 'BULK_3V3' U1-K13 U1-L14 U1-L16 # # VDDAUX2 MSS Bank 2 2.5 / 3.3 V 2 pins # NET 'BULK_3V3' U1-N12 U1-P13 # # VDDAUX4 MSS Bank 4 2.5 / 3.3 V 2 pins # # VDDAUX4 is not used - it is Tied-Off below. # NET 'FPGA_VDDAUX4' U1-R12 U1-T13 # # VDDAUX7 FPGA GPIO Bank 7 2.5 / 3.3 V 2 pins # NET 'BULK_3V3' U1-M13 U1-N14 # # VDDAUX9 FPGA GPIO Bank 9 2.5 / 3.3 V 4 pins # NET 'Digital_2V5' U1-K19 U1-L18 U1-L20 U1-L22 # # # FPGA GROUND Pins: # ----------------- # NET 'GROUND' U1-AA24 U1-AA25 U1-AA26 U1-AB26 U1-AB27 NET 'GROUND' U1-AB28 U1-D26 U1-D27 U1-D28 U1-E24 NET 'GROUND' U1-E25 U1-E26 U1-F24 U1-F27 U1-F28 NET 'GROUND' U1-G26 U1-H24 U1-H28 U1-J26 U1-K24 NET 'GROUND' U1-K28 U1-L26 U1-M24 U1-M28 U1-N26 NET 'GROUND' U1-P24 U1-P28 U1-R26 U1-T24 U1-T28 NET 'GROUND' U1-U26 U1-V23 U1-V24 U1-V28 U1-W24 NET 'GROUND' U1-W26 U1-Y24 U1-Y28 U1-A16 U1-A26 NET 'GROUND' U1-A28 U1-A6 U1-AA6 U1-AB13 U1-AB23 NET 'GROUND' U1-AB3 U1-AC10 U1-AC20 U1-AD17 U1-AD27 NET 'GROUND' U1-AD7 U1-AE14 U1-AE24 U1-AE4 U1-AF11 NET 'GROUND' U1-AF21 U1-AG18 U1-AG8 U1-AH1 U1-AH15 NET 'GROUND' U1-AH25 U1-AH28 U1-AH5 U1-B13 U1-B23 NET 'GROUND' U1-B3 U1-C10 U1-C20 U1-D17 U1-D7 NET 'GROUND' U1-E14 U1-E4 U1-F1 U1-F11 U1-F21 NET 'GROUND' U1-G18 U1-G8 U1-H15 U1-H5 U1-J2 NET 'GROUND' U1-K9 U1-L13 U1-L17 U1-L19 U1-L21 NET 'GROUND' U1-L6 U1-M12 U1-M14 U1-M16 U1-M18 NET 'GROUND' U1-M20 U1-M22 U1-M3 U1-N10 U1-N13 NET 'GROUND' U1-N15 U1-N17 U1-N19 U1-N21 U1-P12 NET 'GROUND' U1-P14 U1-P16 U1-P18 U1-P20 U1-P22 NET 'GROUND' U1-P7 U1-R13 U1-R15 U1-R17 U1-R19 NET 'GROUND' U1-R21 U1-R4 U1-T1 U1-T12 U1-T14 NET 'GROUND' U1-T16 U1-T18 U1-T20 U1-T22 U1-U13 NET 'GROUND' U1-U15 U1-U17 U1-U19 U1-U21 U1-U8 NET 'GROUND' U1-V12 U1-V14 U1-V16 U1-V18 U1-V20 NET 'GROUND' U1-V22 U1-V5 U1-W2 U1-Y9 # # # Un-Used Bank Tie-Off Resistors: # ------------------------------------- # #### Tie-Off Bank #4 I/O Supply and Aux Supply Pins #### NET 'FPGA_VDDI4' R1354-2 # Tie-Off Bank #4 I/O Supply NET 'FPGA_VDDAUX4' R1355-2 # Tie-Off Bank #4 Aux Supply NET 'GROUND' R1354-1 R1355-1 # Ground Anchor the Tie-Off Resistors #### Tie-Off Bank #8 I/O Supply Pins #### NET 'FPGA_VDDI8' R1356-2 # Tie-Off Bank #4 I/O Supply NET 'GROUND' R1356-1 # Ground Anchor the Tie-Off Resistor #### Tie-Off XCVR Reference Supply Pins #### #### #### #### XCVR_Ref is only used with #### #### Single Ended XCVR Reference Clocks #### #### i.e. only used by the foolish #### NET 'XCVR_VREF' R1357-1 C1351-1 # Tie-Off the unused XCVR_Ref pins NET 'GROUND' R1357-2 C1351-2 # Ground Anchor the Tie-Off Res & Cap # # Disco-Kraken Net List File # # FPGA Bypass Caps and Power Filters # --------------------------------------- # # # Initial Rev. 16-Nov-2022 # Current Rev. 30-Nov-2023 # # # This net list holds the nets for: # # - FPGA LC Power Filters # # - FPGA ByPass Capacitors # # # CORE Power to the FPGA/CPU 1V05: # ------------------------------------ # NET 'BULK_1V05' L101-1 # Bulk_1V05 Power Into Filter NET 'CORE_1V05' L101-2 # Filtered CORE Power NET 'CORE_1V05' C101-2 C102-2 # CORE Tantalum Bypass NET 'GROUND' C101-1 C102-1 # Tant Bypass Cap Grounds NET 'CORE_1V05' C103-1 C104-1 C105-1 C106-1 # CORE 22 uFd Bypass NET 'GROUND' C103-2 C104-2 C105-2 C106-2 # Bypass Cap Grounds # # FPGA_1V8 Supply for: Programming, HSIO Aux, and Bank #9 I/O # # The FPGA_1V8 Supply comes from the BULK_1V8 Supply via L103 # ------------------------------------------------------------------ # NET 'BULK_1V8' L103-2 # Bulk_1V8 Power into the Filter NET 'FPGA_1V8' L103-1 # Filtered Power to FPGA: Prog, HSIO_Aux, Bank #9 # # Transceiver 1V05 Analog Power: # ---------------------------------- # NET 'BULK_1V05' L102-1 # Bulk_1V05 Power Into Filter NET 'XCVR_1V05' L102-2 # Filtered Transceiver 1V05 Analog Power # # 2V5 Power to the FPGA/CPU and to the DDR4 Memory: # --------------------------------------------------- # # Analog_2V5 for: FPGA_PLL_2V5, XCVR_PLL_2V5, & XCVR_CLK Supplies NET 'BULK_2V5' L104-2 # Bulk_2V5 Power Into Filter NET 'Analog_2V5' L104-1 # Filtered Analog_2V5 Power # Digital_2V5 for: DDR4 Memory PreCharge & Bank #9 Aux Supplies NET 'BULK_2V5' L105-2 # Bulk_2V5 Power Into Filter NET 'Digital_2V5' L105-1 # Filtered Analog_2V5 Power # # BANK 0 FPGA DDR4 Memory BULK_1V2: # --------------------------------------- # NET 'BULK_1V2' C201-1 C202-1 # Bank 0 22 uFd Bypass NET 'GROUND' C201-2 C202-2 # Bypass Cap Grounds NET 'BULK_1V2' C203-1 C204-1 # Bank 0 2.2 uFd Bypass NET 'GROUND' C203-2 C204-2 # Bypass Cap Grounds # # BANK 6 CPU DDR4 Memory BULK_1V2: # -------------------------------------- # NET 'BULK_1V2' C221-1 C222-1 # Bank 0 22 uFd Bypass NET 'GROUND' C221-2 C222-2 # Bypass Cap Grounds NET 'BULK_1V2' C223-1 C224-1 # Bank 0 2.2 uFd Bypass NET 'GROUND' C223-2 C224-2 # Bypass Cap Grounds # # SFP Connector & Cage Pin Net List # ------------------------------------- # # # Original Rev. 23-Feb-2023 # Current Rev. 26-Dec-2023 # # # This Net List file assigns net names and makes # connections to all pins on the SFP Connector and # the SFP Cage. # # NOTE: Currently (11-Dec-2023) my understanding is that # any/all SFP Modules that are used with the DK Board # do include their own AC Coupling capacitors. # # Thus external AC Coupling caps on the DK board itself # have NOT been included in the DK design for either # Rx or Tx channel for either the Timing or Ethernet # SFP modules. # # # This Net List file includes most of the connections to the # PCA9546A I2C Bus Fan-Out chip. This I2C Fan-Out is used # to allow the I2C Controller #0 in the FPGA/CPU to talk to: # both of the SFP Modules on the DK and to the AD9546 # Timing Generator. There is an un-used 4th port on this # Fan-Out (port #3) where it can be left parked to provide # a layer of isolation and protection to important control # registers, e.g. in the Timing Generator. # # This Net List file includes many connections to "Floating" # pins on the FPGA/CPU. The Floating pin connections are # all listed together at the end of this Net List file. # These Floating pins on the FPGA/CPU are assigned to # specific physical pins in the Net List file: # fpga_cpu_floating_connection_nets.txt # # NOTE: Two section of the U1602 Quad NAND are used for # functions that are not directly related to the # SFP Modules: U1602 4,5,6 is used to make the # DK_CPU_Is_Sane_B signal that is used by the # Emergency Rescue circuits and U1602 8,9,10 # is used to make a Spare Run signal in the # Startup and Resets net lists. # # # Timing SFP J13 Rx and Tx Data Connections with NO External AC Coupling caps # ------------------------------------------------------------------------------------ # # SFP_Time_RD_DIR J13-13 # Receiver DIR data output to Time Gen Ref A Input DIR # SFP_Time_RD_CMP J13-12 # Receiver CMP data output to Time Gen Ref A Input CMP # # The Timing SFP Receiver Output is connected to the # Timing Generator Reference A Input. This connection # is made in the timing_generator_nets.txt file. # SFP_Time_TD_DIR J13-18 # Transmitter DIR data input from Time Gen Output 0-C DIR # SFP_Time_TD_CMP J13-19 # Transmitter CMP data input from Time Gen Output 0-C CMP # # The Timing SFP Transmitter Input is connected to the # Timing Generator Output 0-C. This connection # is made in the timing_generator_nets.txt file. # # Ethernet SFP J14 Rx and Tx Data Connections with NO External AC Coupling caps # -------------------------------------------------------------------------------------- # NET 'SFP_ENet_RD_DIR' U1-T26 # Receiver DIR data output to FPGA XCVR_0_Rx_1_Dir NET 'SFP_ENet_RD_CMP' U1-T25 # Receiver CMP data output to FPGA XCVR_0_Rx_1_Cmp # The ENet SFP Receiver Output is routed to the # XCVR_0 Rx_1 Input on the FPGA/CPU. # XCVR_0_Rx_1_Dir is pin T26 # XCVR_0_Rx_1_Cmp is pin T25 NET 'SFP_ENet_TD_DIR' U1-U28 # Transmitter DIR data input from FPGA XCVR_0_Tx_1_Dir NET 'SFP_ENet_TD_CMP' U1-U27 # Transmitter CMP data input from FPGA XCVR_0_Tx_1_Cmp # The ENet SFP Transmitter Input is routed from # the XCVR_0 Tx_1 Output of the FPGA/CPU. # XCVR_0_Tx_1_Dir is pin U28 # XCVR_0_Tx_1_Cmp is pin U27 # # Pull-Up Resistors and Connections to: Tx_Fault, Mod_Present, Rx_Loss # ------------------------------------------------------------------------- # # These 3 pins are Outputs from each SFP module are routed to # "Floating" GPIO Input pins on the FPGA/CPU. All of the # connections in this Net List files that are made to Floating # pins on the FPGA/CPU are summerized in a section below. # # The actual assignment of these signals to a physical pins # on the FPGA/CPU is made in the Net List file: # fpga_cpu_floating_connection_nets.txt # # Timing SFP J13 Connections for: Tx_Fault, Mod_Present, Rx_Loss NET 'SFP_Time_TX_Fault' R1605-2 # Module Tx Fault to FPGA/CPU GPIO 3V3 Input NET 'SFP_Time_MOD_ABS' R1602-2 # Module Absent to FPGA/CPU GPIO 3V3 Input NET 'SFP_Time_RX_LOS' R1601-2 # Rx Signal Loss to FPGA/CPU GPIO 3V3 Input NET 'BULK_3V3' R1601-1 R1602-1 R1605-1 # Pull-Up 3V3 Source # Ethernet SFP J14 Connections for: Tx_Fault, Mod_Present, Rx_Loss NET 'SFP_ENet_TX_Fault' R1610-2 # Module Tx Fault to FPGA/CPU GPIO 3V3 Input NET 'SFP_ENet_MOD_ABS' R1607-2 # Module Absent to FPGA/CPU GPIO 3V3 Input NET 'SFP_ENet_RX_LOS' R1606-2 # Rx Signal Loss to FPGA/CPU GPIO 3V3 Input NET 'BULK_3V3' R1606-1 R1607-1 R1610-1 # Pull-Up 3V3 Source # # SFP Connector Pins: Tx_Disable, Rate_Select_0, Rate_Select_1 # ------------------------------------------------------------------------- # # These 3 pins are Inputs to each SFP module. # # For our use on the DK Board the Tx_Disable needs to be # controlled by a GPIO output signal from the FPGA/CPU. # I will include a series terminator in this line as it # may need to be banged about quite a bit. # # Normally the two Rate_Select pins are not used - but # because of the special types of SFP modules that may be # used on the DK board I will also route the two Rate_Select # pins from the SFP connectors to GPIO pins on the FPGA/CPU. # # The Tx_Disable and the Rate_Select connections to the # FPGA/CPU are to Floating GPIO pin assignments. # # The actual assignment of these signals to a physical pins # on the FPGA/CPU is made in the Net List file: # fpga_cpu_floating_connection_nets.txt # # # The Tx_Disable has 2 jumper selectable options: # # - Install the Ground jumper (JMP1601 JMP1603) # and the Tx Laser is forced ON continuously. # # - Install the FPGA/CPU control jumper (JMP1602 # JMP1604) to require both the DK_CPU_Is_Sane # signal AND the SFP_x_Trans_Enable signal from # the FPGA/CPU to both be HI in order for the # SFP module Tx Laser to come ON. # NOTE: The control signal from the FPGA/CPU is # an "Enable" type signal (not a disable). # # # Tx Disable for the Timing SFP: # --------------------------======------------------ # NET 'SFP_Time_Trans_Enable' R1615-2 # Time SFP Tx Enable from FPGA/CPU GPIO Output NET 'SFP_Time_Tx_Enb_Term' R1615-1 U1602-2 # Time SFP Tx Enable to NAND Gate NET 'SFP_Time_Tx_Enb_Jmpr' U1602-3 JMP1602-1 # Time SFP Tx Enable to Jumper NET 'SFP_Time_TX_Disable' JMP1601-1 JMP1602-2 # Time SFP Tx Disabled Pin #3 NET 'GROUND' JMP1601-2 # Ground Jumper Laser forced ON # # Tx Disable for the Ethernet SFP: # --------------------------========---------------- # NET 'SFP_ENet_Trans_Enable' R1616-2 # ENet SFP Tx Enable from FPGA/CPU GPIO Output NET 'SFP_ENet_Tx_Enb_Term' R1616-1 U1602-12 # ENet SFP Tx Enable to NAND Gate NET 'SFP_ENet_Tx_Enb_Jmpr' U1602-11 JMP1604-1 # ENet SFP Tx Enable to Jumper NET 'SFP_ENet_TX_Disable' JMP1603-1 JMP1604-2 # ENet SFP Tx Disabled Pin #3 NET 'GROUND' JMP1603-2 # Ground Jumper Laser forced ON # # DK_CPU_Is_Sane Distribution to the Tx Disable Circuits: # ------------------------------------------------------------------ # NET 'DK_CPU_Is_Sane' U1602-1 U1602-13 # CPU_Sane to the Tx Disable Gates NET 'DK_CPU_Is_Sane' U1602-4 U1602-5 # CPU_Sane to the Inverter Gate NET 'DK_CPU_Is_Sane' U1602-10 # CPU_Sane to the TOMCat Reset Gate NET 'DK_CPU_Is_Sane_B' U1602-6 # CPU_Sane_B to the Emergency Rescue Circuits # # Tx Disable NAND Gate Power and Ground: # -------------------------------------------------- # NET 'BULK_3V3' C1615-2 U1602-14 # Bulk_3V3 Bypass and Power NET 'GROUND' C1615-1 U1602-7 # Ground the Bypass and Chip # # Pull-Up Resistors and Connection for the: SFP <--> I2C Fan-Out I2C Links # ------------------------------------------------------------------------------- # # Timing SFP J13 Connection for: I2C Link to the I2C Fan-Out Ch #1 NET 'SFP_Time_SCL' R1603-2 U1601-7 # Time SFP I2C SCLK to Fan-Out Channel 1 NET 'SFP_Time_SDA' R1604-2 U1601-6 # Time SFP I2C SDATA to Fan-Out Channel 1 NET 'BULK_3V3' R1603-1 R1604-1 # Pull-Up 3V3 Source # Ethernet SFP J14 Connection for: I2C Link to the I2C Fan-Out Ch #2 NET 'SFP_ENet_SCL' R1608-2 U1601-10 # ENet SFP I2C SCLK to Fan-Out Channel 2 NET 'SFP_ENet_SDA' R1609-2 U1601-9 # ENet SFP I2C SDATA to Fan-Out Channel 2 NET 'BULK_3V3' R1608-1 R1609-1 # Pull-Up 3V3 Source # # I2C Fan-Out Channel Ch #0 Connection to the Timing Generator U901 # --------------------------------------------------------------------------- # # This Net List file just defines the Channel #0 pins on the # I2C Fan-Out chip that provide the I2C Bus to setup and monitor # the AD9546 Timing Generator. The pull-up resistors for this # I2C link and the connections to the Timing Generator are all # made in the Net List file: timing_generator_nets.txt NET 'TG_I2C_SCLK' U1601-5 # I2C Fan-Out Ch #0 SCLK to the Timing Generator NET 'TG_I2C_SDATA' U1601-4 # I2C Fan-Out Ch #0 SDATA to the Timing Generator # # Pull-Up Resistors for the Un-Used I2C Fan-Out Channel Ch #3 # --------------------------------------------------------------------------- # NET 'I2C_CTRL_0_FAN_Ch_3_SCL' R1613-2 U1601-12 # Un-Used I2C_Fan-Out Channel 3 SCLK NET 'I2C_CTRL_0_FAN_Ch_3_SDA' R1614-2 U1601-11 # Un-Used I2C_Fan-Out Channel 3 SDATA NET 'BULK_3V3' R1613-1 R1614-1 # Pull-Up 3V3 Source # # Pull-Up Resistors and Connection for the: FPGA/CPU <--> I2C Fan-Out I2C Link # ----------------------------------------------------------------------------------- # NET 'CPU_I2C_Ctrl_0_SCL' R1611-2 U1601-14 # FPGA/CPU Controller 0 I2C SCLK to Fan-Out NET 'CPU_I2C_Ctrl_0_SDA' R1612-2 U1601-15 # FPGA/CPU Controller 0 I2C SDATA to Fan-Out NET 'BULK_3V3' R1611-1 R1612-1 # Pull-Up 3V3 Source # # I2C Fan-Out Address Pins # --------------------------------------------------------------------------- # # The 3 Address pins on the PCA9546A I2C Fan-out chip are # all tied to ground. These connections are made on the PCB # with sufficiently long runs so that they may be changed in # an emergency. # # This gives the I2C Fan-Out chip itself an Address of 0x70 # when written as 3 MS Bit and 4 LS Bit expressed in hex. # NET 'GROUND' U1601-1 U1601-2 U1601-13 # Ground all 3 Address pins # # I2C Fan-Out RESET_B Pin # --------------------------------------------------------------------------- # # The RESET_B pin on the PCA9546A is controlled by the signal # from a GPIO pin on the FPGA/CPU. This connection is to a # Floating pin on the FPGA/CPU NET 'CPU_I2C_Ctrl_0_Fan_Out_RESET_B' U1601-3 # I2C Fanout Reset_B from FPGA/CPU GPIO # # Power and Ground to the I2C Fan-Out: # ------------------------------------------------------------------------- # NET 'BULK_3V3' C1614-2 C1613-2 U1601-16 # Bulk_3V3 Bypass and Power NET 'GROUND' C1614-1 C1613-1 U1601-8 # Ground the Bypass and Chip # # Timing SFP J13 Connector Pins # --------------------------------- # NET 'GROUND' J13-1 # Module Transmitter Ground NET 'SFP_Time_TX_Fault' J13-2 # Module Transmitter Fault NET 'SFP_Time_TX_Disable' J13-3 # Transmitter Disabled NET 'SFP_Time_SDA' J13-4 # 2-wire Serial Data NET 'SFP_Time_SCL' J13-5 # 2-wire Serial Clock NET 'SFP_Time_MOD_ABS' J13-6 # Module Absent NET 'SFP_Time_RS_0' J13-7 # Rate Select 0 NET 'SFP_Time_RX_LOS' J13-8 # Receiver Loss of Signal Indication NET 'SFP_Time_RS_1' J13-9 # Rate Select 1 NET 'GROUND' J13-10 # Module Receiver Ground NET 'GROUND' J13-11 # Module Receiver Ground NET 'SFP_Time_RD_CMP' J13-12 # Receiver Inverted Data Output NET 'SFP_Time_RD_DIR' J13-13 # Receiver NonInverted Data Output NET 'GROUND' J13-14 # Module Receiver Ground NET 'SFP_Time_VccR' J13-15 # Module Receiver 3.3 V Supply NET 'SFP_Time_VccT' J13-16 # Module Transmitter 3.3 V Supply NET 'GROUND' J13-17 # Module Transmitter Ground NET 'SFP_Time_TD_DIR' J13-18 # Transmitter NonInverted Data Input NET 'SFP_Time_TD_CMP' J13-19 # Transmitter Inverted Data Input NET 'GROUND' J13-20 # Module Transmitter Ground # # EtherNet SFP J14 Connector Pins # ----------------------------------- # NET 'GROUND' J14-1 # Module Transmitter Ground NET 'SFP_ENet_TX_Fault' J14-2 # Module Transmitter Fault NET 'SFP_ENet_TX_Disable' J14-3 # Transmitter Disabled NET 'SFP_ENet_SDA' J14-4 # 2-wire serial Data NET 'SFP_ENet_SCL' J14-5 # 2-wire serial Clock NET 'SFP_ENet_MOD_ABS' J14-6 # Module Absent NET 'SFP_ENet_RS_0' J14-7 # Rate Select 0 NET 'SFP_ENet_RX_LOS' J14-8 # Receiver Loss of Signal Indication NET 'SFP_ENet_RS_1' J14-9 # Rate Select 1 NET 'GROUND' J14-10 # Module Receiver Ground NET 'GROUND' J14-11 # Module Receiver Ground NET 'SFP_ENet_RD_CMP' J14-12 # Receiver Inverted Data Output NET 'SFP_ENet_RD_DIR' J14-13 # Receiver NonInverted Data Output NET 'GROUND' J14-14 # Module Receiver Ground NET 'SFP_ENet_VccR' J14-15 # Module Receiver 3.3 V Supply NET 'SFP_ENet_VccT' J14-16 # Module Transmitter 3.3 V Supply NET 'GROUND' J14-17 # Module Transmitter Ground NET 'SFP_ENet_TD_DIR' J14-18 # Transmitter NonInverted Data Input NET 'SFP_ENet_TD_CMP' J14-19 # Transmitter Inverted Data Input NET 'GROUND' J14-20 # Module Transmitter Ground # # Power Feeds to the SFP Connectors # ------------------------------------- # # Timing SFP J13 Receiver NET 'BULK_3V3' L1601-1 C1601-1 # Power Feed to Rx Filter NET 'GROUND' C1601-2 # Ground this Bypass Cap NET 'SFP_Time_VccR' L1601-2 # Power Feed to J13 Rx NET 'SFP_Time_VccR' C1605-2 C1606-2 # Bypass on J13 Rx NET 'GROUND' C1605-1 C1606-1 # Ground these Bypass Caps # Timing SFP J13 Transmitter NET 'BULK_3V3' L1602-1 C1602-1 # Power Feed to Tx Filter NET 'GROUND' C1602-2 # Ground this Bypass Cap NET 'SFP_Time_VccT' L1602-2 # Power Feed to J13 Tx NET 'SFP_Time_VccT' C1607-2 C1608-2 # Bypass on J13 Tx NET 'GROUND' C1607-1 C1608-1 # Ground these Bypass Caps # Ethernet SFP J14 Receiver NET 'BULK_3V3' L1603-1 C1603-1 # Power Feed to Rx Filter NET 'GROUND' C1603-2 # Ground this Bypass Cap NET 'SFP_ENet_VccR' L1603-2 # Power Feed to J14 Rx NET 'SFP_ENet_VccR' C1609-2 C1610-2 # Bypass on J14 Rx NET 'GROUND' C1609-1 C1610-1 # Ground these Bypass Caps # Ethernet SFP J14 Transmitter NET 'BULK_3V3' L1604-1 C1604-1 # Power Feed to Tx Filter NET 'GROUND' C1604-2 # Ground this Bypass Cap NET 'SFP_ENet_VccT' L1604-2 # Power Feed to J14 Tx NET 'SFP_ENet_VccT' C1611-2 C1612-2 # Bypass on J14 Tx NET 'GROUND' C1611-1 C1612-1 # Ground these Bypass Caps # # SFP Twin Cage Ground Pins # ----------------------------- # NET 'GROUND' CAGE_1-1 CAGE_1-2 CAGE_1-3 CAGE_1-4 CAGE_1-5 NET 'GROUND' CAGE_1-6 CAGE_1-7 CAGE_1-8 CAGE_1-9 CAGE_1-10 NET 'GROUND' CAGE_1-11 CAGE_1-12 CAGE_1-13 CAGE_1-14 CAGE_1-15 NET 'GROUND' CAGE_1-16 CAGE_1-17 CAGE_1-18 CAGE_1-19 CAGE_1-20 NET 'GROUND' CAGE_1-21 CAGE_1-22 CAGE_1-23 CAGE_1-24 CAGE_1-25 # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are 3V3 signals: SFP Control and Monitor and # FPGA/CPU I2C Controller #0 # --------------------------------------------------------------------------- # # # NET 'SFP_Time_TX_Fault' # Time SFP Tx Fault to FPGA/CPU GPIO Input # NET 'SFP_Time_MOD_ABS' # Time SFP Module Absent to FPGA/CPU GPIO Input # NET 'SFP_Time_RX_LOS' # Time SFP Rx Signal Loss to FPGA/CPU GPIO Input # # NET 'SFP_Time_Trans_Enable' # Time SFP Tx Enable from FPGA/CPU GPIO Output # # NET 'SFP_Time_RS_0' # Time SFP Rate Select 0 <--> FPGA/CPU GPIO I/O # NET 'SFP_Time_RS_1' # Time SFP Rate Select 1 <--> FPGA/CPU GPIO I/O # # # NET 'SFP_ENet_TX_Fault' # ENet SFP Tx Fault to FPGA/CPU GPIO Input # NET 'SFP_ENet_MOD_ABS' # ENet SFP Module Absent to FPGA/CPU GPIO Input # NET 'SFP_ENet_RX_LOS' # ENet SFP Rx Signal Loss to FPGA/CPU GPIO Input # # NET 'SFP_ENet_Trans_Enable' # ENET SFP Tx Enable from FPGA/CPU GPIO Output # # NET 'SFP_ENet_RS_0' # Time SFP Rate Select 0 <--> FPGA/CPU GPIO I/O # NET 'SFP_ENet_RS_1' # Time SFP Rate Select 1 <--> FPGA/CPU GPIO I/O # # # NET 'CPU_I2C_Ctrl_0_SCL' # FPGA/CPU Controller 0 I2C SCLK to Fan-Out # NET 'CPU_I2C_Ctrl_0_SDA' # FPGA/CPU Controller 0 I2C SDATA to Fan-Out # # NET 'CPU_I2C_Ctrl_0_Fan_Out_RESET_B' # I2C Fanout Reset_B from FPGA/CPU GPIO # # # Below here is some SFP reference information # ---------------------------------------------- # # # Note that Pin #9 has a different function # in the SFP vs SFP+ pinouts # # # SFP Network Port Connector Pinout # --------------------------------- # # 1 VeeT Module transmitter ground # 2 TX_Fault Module transmitter fault # 3 TX_Disable Transmitter disabled # 4 SDA 2-wire serial interface data line # 5 SCL 2-wire serial interface clock # # 6 MOD_ABS Module absent # 7 RS Rate select # 8 RX_LOS Receiver loss of signal indication # 9 VeeR Module receiver ground # 10 VeeR Module receiver ground # # 11 VeeR Module receiver ground # 12 RD- Receiver inverted data output # 13 RD+ Receiver noninverted data output # 14 VeeR Module receiver ground # 15 VccR Module receiver 3.3 V supply # # 16 VccT Module transmitter 3.3 V supply # 17 VeeT Module transmitter ground # 18 TD+ Transmitter noninverted data input # 19 TD- Transmitter inverted data input # 20 VeeT Module transmitter ground # # # # SFP+ Network Port Connector Pinout # ---------------------------------- # # 1 VeeT Module transmitter ground # 2 TX_Fault Module transmitter fault # 3 TX_Disable Transmitter disabled # 4 SDA 2-wire serial interface data line # 5 SCL 2-wire serial interface clock # # 6 MOD_ABS Module absent # 7 RS0 Rate select 0, optionally controls SFP+ module receiver # 8 RX_LOS Receiver loss of signal indication # 9 RS1 Rate select 1, optionally controls SFP+ transmitter # 10 VeeR Module receiver ground # # 11 VeeR Module receiver ground # 12 RD- Receiver inverted data output # 13 RD+ Receiver noninverted data output # 14 VeeR Module receiver ground # 15 VccR Module receiver 3.3-V supply # # 16 VccT Module transmitter 3.3-V supply # 17 VeeT Module transmitter ground # 18 TD+ Transmitter noninverted data input # 19 TD- Transmitter inverted data input # 20 VeeT Module transmitter ground # # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #1/6 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # DCDC Converter Net List Template File # ----------------========--========------- # # # Original Rev. 5-Feb-2023 # Most Recent Rev. 17-Nov-2023 # # # # This Template file holds the nets for the DK # DC/DC Power Converters. These converters run # from the BULK_5V0 bus and it make the 6 BULK # power rails that are used by the DK board itself. # # # For reference recall the 6 DCDC Converters on DK: # # Output # Converter Ref. Power Output Expected Output Power Trends # Name Desig Bus Voltage Load Capacity Model Number # --------- ----- --------- ------- ----------- -------- ------------ # # DCDC1 1701 Bulk_1V00 1.00 V about 1.4 A 3 A PTH04T260WAD # DCDC2 1731 Bulk_1V05 1.05 V under 3.0 A 6 A PTH04T230WAD # DCDC3 1761 Bulk_1V2 1.20 V about 4.0 A 6 A PTH04T230WAD # DCDC4 1791 Bulk_1V8 1.80 V under 1.5 A 3 A PTH04T260WAD # DCDC5 1821 Bulk_2V5 2.50 V about 1.4 A 3 A PTH04T260WAD # DCDC6 1851 Bulk_3V3 3.30 V under 1.5 A 3 A PTH04T260WAD # # # # Define the Connections within the DCDC Power Converter # --------------------------------------------------------- # # # Input Power to the Converter: NET 'BULK_5V0' R1701-2 # Power to the Current Sense Resistor NET 'DCDC1_CSR_TO_L' R1701-3 # Power from the Current Sense NET 'DCDC1_CSR_TO_L' L1701-1 # Resistor to the Filter Inductor NET 'DCDC1_INPUT' L1701-2 # Power feed to the Converter NET 'DCDC1_INPUT' C1701-1 C1702-1 # Tantalum Input Caps NET 'DCDC1_INPUT' C1703-1 C1704-1 # Tantalum Input Caps NET 'DCDC1_INPUT' C1705-2 C1706-1 # Ceramic Input Caps NET 'DCDC1_INPUT' C1707-2 C1708-2 # Ceramic Input Caps NET 'DCDC1_INPUT' DCDC1-2 # Power Input to the Converter - Pin #2 NET 'GROUND' C1701-2 C1702-2 # Tantalum Cap Grounds NET 'GROUND' C1703-2 C1704-2 # Taltalum Cap Grounds NET 'GROUND' C1705-1 C1706-2 # Ceramic Cap Grounds NET 'GROUND' C1707-1 C1708-1 # Ceramic Cap Grounds # # Power Output from the Converter: NET 'BULK_1V00' DCDC1-4 # Output Power from the Converter - Pin #4 NET 'BULK_1V00' C1709-1 C1710-1 # Ceramic Output Caps NET 'BULK_1V00' C1711-2 C1712-1 # Ceramic Output Caps NET 'BULK_1V00' C1713-1 C1714-1 # Tantalum Output Caps NET 'BULK_1V00' C1715-1 C1716-1 # Tantalum Output Caps NET 'BULK_1V00' DZ1701-1 # Output Zener Clamp NET 'GROUND' C1709-2 C1710-2 # Ceramic Cap Grounds NET 'GROUND' C1711-1 C1712-2 # Ceramic Cap Grounds NET 'GROUND' C1713-2 C1714-2 # Tantalum Cap Grounds NET 'GROUND' C1715-2 C1716-2 # Tantalum Cap Grounds NET 'GROUND' DZ1701-2 # Zener Clamp Ground # # DC/DC Converter GROUND Pins NET 'GROUND' DCDC1-3 # Converter Ground Pin - Pin #3 NET 'GROUND' DCDC1-31 DCDC1-32 # Converter Auxiliary Ground Pins # # DC/DC Converter Tracking Pin NET 'DCDC_CONV_TRACK' DCDC1-9 # TRACK Pin of this DCDC Converter - Pin #9 # # DC/DC Converter Feedback Remote Sense Pins NET 'BULK_1V00' AKA1701-2 # Positive SENSE Remote Connection NET 'DCDC1_SEN_POS' AKA1701-1 DCDC1-5 # Positive SENSE input pin - Pin #5 NET 'GROUND' AKA1702-2 # Negative SENSE Remote Connection NET 'DCDC1_SEN_NEG' AKA1702-1 DCDC1-6 # Negative SENSE input pin - Pin #6 # # DC/DC Converter Output Voltage Rset Resistor # with capacitor across the variable part of the Vout Rset Resistor # # NOTE: Ground Reference not Negative Sense Reference NET 'GROUND' R1703-1 R1703-2 # Want Trim Pot CW Truning to: NET 'DCDC1_VAR_FIX' R1703-3 # Reduce the Resistance and NET 'DCDC1_VAR_FIX' R1702-2 # Increase the Output Voltage NET 'DCDC1_VO_ADJ' R1702-1 DCDC1-7 # Converter Rset Vout Adj pin - Pin #7 NET 'DCDC1_VAR_FIX' C1717-1 # Capacitor across the NET 'GROUND' C1717-2 # Vout Trim Pot Resistor # # DC/DC Converter Transient Response Control Pin NET 'DCDC1_TRC_PIN' R1704-2 DCDC1-8 # Transient Response Control pin - Pin #8 NET 'DCDC1_SEN_POS' R1704-1 # Transient Response Resistor # # DC/DC Converter INH-UVLO Pin and Resistor NET 'DCDC1_INH_UVLO' R1705-1 DCDC1-10 # INH-UVLO Pin #10 NET 'GROUND' R1705-2 # Ground end of UVLO Resistor # # DC/DC Converter Sync Pin tied to Ground via trace NET 'DCDC1_SYNC' AKA1703-1 DCDC1-1 # Converter's SYNC Pin - Pin #1 NET 'GROUND' AKA1703-2 # Tie SYNC Pin to Ground # # Current Sense Resistor to Filter and to Current Monitor Connector Pins NET 'DCDC1_CS_POS' R1701-4 R1706-1 # Current Sense Res. to Filter Res. NET 'DCDC1_CS_NEG' R1701-1 R1707-1 # Current Sense Res. to Filter Res. NET 'IMON_POS_BULK_1V00' R1706-2 C1718-1 # Current Monitor Filter Res Cap Pin NET 'IMON_NEG_BULK_1V00' R1707-2 C1720-2 # Current Monitor Filter Res Cap Pin NET 'IMON_POS_BULK_1V00' C1719-1 # Current Monitor Shunt Cap NET 'IMON_NEG_BULK_1V00' C1719-2 # Current Monitor Shunt Cap NET 'GROUND' C1718-2 C1720-1 # Current Monitor Filter Cap Grounds # # Voltage Monitor Filter and to Voltage Monitor Connector Pin NET 'BULK_1V00' R1708-1 # Voltage Monitor Filter Resistor NET 'VMON_BULK_1V00' R1708-2 C1721-1 # Voltage Monitor Filter Res Cap Pin NET 'GROUND' C1721-2 # Voltage Monitor Filter Cap Ground # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #2/6 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # DCDC Converter Net List Template File # ----------------========--========------- # # # Original Rev. 5-Feb-2023 # Most Recent Rev. 17-Nov-2023 # # # # This Template file holds the nets for the DK # DC/DC Power Converters. These converters run # from the BULK_5V0 bus and it make the 6 BULK # power rails that are used by the DK board itself. # # # For reference recall the 6 DCDC Converters on DK: # # Output # Converter Ref. Power Output Expected Output Power Trends # Name Desig Bus Voltage Load Capacity Model Number # --------- ----- --------- ------- ----------- -------- ------------ # # DCDC1 1701 Bulk_1V00 1.00 V about 1.4 A 3 A PTH04T260WAD # DCDC2 1731 Bulk_1V05 1.05 V under 3.0 A 6 A PTH04T230WAD # DCDC3 1761 Bulk_1V2 1.20 V about 4.0 A 6 A PTH04T230WAD # DCDC4 1791 Bulk_1V8 1.80 V under 1.5 A 3 A PTH04T260WAD # DCDC5 1821 Bulk_2V5 2.50 V about 1.4 A 3 A PTH04T260WAD # DCDC6 1851 Bulk_3V3 3.30 V under 1.5 A 3 A PTH04T260WAD # # # # Define the Connections within the DCDC Power Converter # --------------------------------------------------------- # # # Input Power to the Converter: NET 'BULK_5V0' R1731-2 # Power to the Current Sense Resistor NET 'DCDC2_CSR_TO_L' R1731-3 # Power from the Current Sense NET 'DCDC2_CSR_TO_L' L1731-1 # Resistor to the Filter Inductor NET 'DCDC2_INPUT' L1731-2 # Power feed to the Converter NET 'DCDC2_INPUT' C1731-1 C1732-1 # Tantalum Input Caps NET 'DCDC2_INPUT' C1733-1 C1734-1 # Tantalum Input Caps NET 'DCDC2_INPUT' C1735-2 C1736-1 # Ceramic Input Caps NET 'DCDC2_INPUT' C1737-2 C1738-2 # Ceramic Input Caps NET 'DCDC2_INPUT' DCDC2-2 # Power Input to the Converter - Pin #2 NET 'GROUND' C1731-2 C1732-2 # Tantalum Cap Grounds NET 'GROUND' C1733-2 C1734-2 # Taltalum Cap Grounds NET 'GROUND' C1735-1 C1736-2 # Ceramic Cap Grounds NET 'GROUND' C1737-1 C1738-1 # Ceramic Cap Grounds # # Power Output from the Converter: NET 'Bulk_1V05' DCDC2-4 # Output Power from the Converter - Pin #4 NET 'Bulk_1V05' C1739-1 C1740-1 # Ceramic Output Caps NET 'Bulk_1V05' C1741-2 C1742-1 # Ceramic Output Caps NET 'Bulk_1V05' C1743-1 C1744-1 # Tantalum Output Caps NET 'Bulk_1V05' C1745-1 C1746-1 # Tantalum Output Caps NET 'Bulk_1V05' DZ1731-1 # Output Zener Clamp NET 'GROUND' C1739-2 C1740-2 # Ceramic Cap Grounds NET 'GROUND' C1741-1 C1742-2 # Ceramic Cap Grounds NET 'GROUND' C1743-2 C1744-2 # Tantalum Cap Grounds NET 'GROUND' C1745-2 C1746-2 # Tantalum Cap Grounds NET 'GROUND' DZ1731-2 # Zener Clamp Ground # # DC/DC Converter GROUND Pins NET 'GROUND' DCDC2-3 # Converter Ground Pin - Pin #3 NET 'GROUND' DCDC2-31 DCDC2-32 # Converter Auxiliary Ground Pins # # DC/DC Converter Tracking Pin NET 'DCDC_CONV_TRACK' DCDC2-9 # TRACK Pin of this DCDC Converter - Pin #9 # # DC/DC Converter Feedback Remote Sense Pins NET 'Bulk_1V05' AKA1731-2 # Positive SENSE Remote Connection NET 'DCDC2_SEN_POS' AKA1731-1 DCDC2-5 # Positive SENSE input pin - Pin #5 NET 'GROUND' AKA1732-2 # Negative SENSE Remote Connection NET 'DCDC2_SEN_NEG' AKA1732-1 DCDC2-6 # Negative SENSE input pin - Pin #6 # # DC/DC Converter Output Voltage Rset Resistor # with capacitor across the variable part of the Vout Rset Resistor # # NOTE: Ground Reference not Negative Sense Reference NET 'GROUND' R1733-1 R1733-2 # Want Trim Pot CW Truning to: NET 'DCDC2_VAR_FIX' R1733-3 # Reduce the Resistance and NET 'DCDC2_VAR_FIX' R1732-2 # Increase the Output Voltage NET 'DCDC2_VO_ADJ' R1732-1 DCDC2-7 # Converter Rset Vout Adj pin - Pin #7 NET 'DCDC2_VAR_FIX' C1747-1 # Capacitor across the NET 'GROUND' C1747-2 # Vout Trim Pot Resistor # # DC/DC Converter Transient Response Control Pin NET 'DCDC2_TRC_PIN' R1734-2 DCDC2-8 # Transient Response Control pin - Pin #8 NET 'DCDC2_SEN_POS' R1734-1 # Transient Response Resistor # # DC/DC Converter INH-UVLO Pin and Resistor NET 'DCDC2_INH_UVLO' R1735-1 DCDC2-10 # INH-UVLO Pin #10 NET 'GROUND' R1735-2 # Ground end of UVLO Resistor # # DC/DC Converter Sync Pin tied to Ground via trace NET 'DCDC2_SYNC' AKA1733-1 DCDC2-1 # Converter's SYNC Pin - Pin #1 NET 'GROUND' AKA1733-2 # Tie SYNC Pin to Ground # # Current Sense Resistor to Filter and to Current Monitor Connector Pins NET 'DCDC2_CS_POS' R1731-4 R1736-1 # Current Sense Res. to Filter Res. NET 'DCDC2_CS_NEG' R1731-1 R1737-1 # Current Sense Res. to Filter Res. NET 'IMON_POS_BULK_1V05' R1736-2 C1748-1 # Current Monitor Filter Res Cap Pin NET 'IMON_NEG_BULK_1V05' R1737-2 C1750-2 # Current Monitor Filter Res Cap Pin NET 'IMON_POS_BULK_1V05' C1749-1 # Current Monitor Shunt Cap NET 'IMON_NEG_BULK_1V05' C1749-2 # Current Monitor Shunt Cap NET 'GROUND' C1748-2 C1750-1 # Current Monitor Filter Cap Grounds # # Voltage Monitor Filter and to Voltage Monitor Connector Pin NET 'Bulk_1V05' R1738-1 # Voltage Monitor Filter Resistor NET 'VMON_BULK_1V05' R1738-2 C1751-1 # Voltage Monitor Filter Res Cap Pin NET 'GROUND' C1751-2 # Voltage Monitor Filter Cap Ground # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:40 2020 # MIGT> begin substituting from -- instance #3/6 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # DCDC Converter Net List Template File # ----------------========--========------- # # # Original Rev. 5-Feb-2023 # Most Recent Rev. 17-Nov-2023 # # # # This Template file holds the nets for the DK # DC/DC Power Converters. These converters run # from the BULK_5V0 bus and it make the 6 BULK # power rails that are used by the DK board itself. # # # For reference recall the 6 DCDC Converters on DK: # # Output # Converter Ref. Power Output Expected Output Power Trends # Name Desig Bus Voltage Load Capacity Model Number # --------- ----- --------- ------- ----------- -------- ------------ # # DCDC1 1701 Bulk_1V00 1.00 V about 1.4 A 3 A PTH04T260WAD # DCDC2 1731 Bulk_1V05 1.05 V under 3.0 A 6 A PTH04T230WAD # DCDC3 1761 Bulk_1V2 1.20 V about 4.0 A 6 A PTH04T230WAD # DCDC4 1791 Bulk_1V8 1.80 V under 1.5 A 3 A PTH04T260WAD # DCDC5 1821 Bulk_2V5 2.50 V about 1.4 A 3 A PTH04T260WAD # DCDC6 1851 Bulk_3V3 3.30 V under 1.5 A 3 A PTH04T260WAD # # # # Define the Connections within the DCDC Power Converter # --------------------------------------------------------- # # # Input Power to the Converter: NET 'BULK_5V0' R1761-2 # Power to the Current Sense Resistor NET 'DCDC3_CSR_TO_L' R1761-3 # Power from the Current Sense NET 'DCDC3_CSR_TO_L' L1761-1 # Resistor to the Filter Inductor NET 'DCDC3_INPUT' L1761-2 # Power feed to the Converter NET 'DCDC3_INPUT' C1761-1 C1762-1 # Tantalum Input Caps NET 'DCDC3_INPUT' C1763-1 C1764-1 # Tantalum Input Caps NET 'DCDC3_INPUT' C1765-2 C1766-1 # Ceramic Input Caps NET 'DCDC3_INPUT' C1767-2 C1768-2 # Ceramic Input Caps NET 'DCDC3_INPUT' DCDC3-2 # Power Input to the Converter - Pin #2 NET 'GROUND' C1761-2 C1762-2 # Tantalum Cap Grounds NET 'GROUND' C1763-2 C1764-2 # Taltalum Cap Grounds NET 'GROUND' C1765-1 C1766-2 # Ceramic Cap Grounds NET 'GROUND' C1767-1 C1768-1 # Ceramic Cap Grounds # # Power Output from the Converter: NET 'Bulk_1V2' DCDC3-4 # Output Power from the Converter - Pin #4 NET 'Bulk_1V2' C1769-1 C1770-1 # Ceramic Output Caps NET 'Bulk_1V2' C1771-2 C1772-1 # Ceramic Output Caps NET 'Bulk_1V2' C1773-1 C1774-1 # Tantalum Output Caps NET 'Bulk_1V2' C1775-1 C1776-1 # Tantalum Output Caps NET 'Bulk_1V2' DZ1761-1 # Output Zener Clamp NET 'GROUND' C1769-2 C1770-2 # Ceramic Cap Grounds NET 'GROUND' C1771-1 C1772-2 # Ceramic Cap Grounds NET 'GROUND' C1773-2 C1774-2 # Tantalum Cap Grounds NET 'GROUND' C1775-2 C1776-2 # Tantalum Cap Grounds NET 'GROUND' DZ1761-2 # Zener Clamp Ground # # DC/DC Converter GROUND Pins NET 'GROUND' DCDC3-3 # Converter Ground Pin - Pin #3 NET 'GROUND' DCDC3-31 DCDC3-32 # Converter Auxiliary Ground Pins # # DC/DC Converter Tracking Pin NET 'DCDC_CONV_TRACK' DCDC3-9 # TRACK Pin of this DCDC Converter - Pin #9 # # DC/DC Converter Feedback Remote Sense Pins NET 'Bulk_1V2' AKA1761-2 # Positive SENSE Remote Connection NET 'DCDC3_SEN_POS' AKA1761-1 DCDC3-5 # Positive SENSE input pin - Pin #5 NET 'GROUND' AKA1762-2 # Negative SENSE Remote Connection NET 'DCDC3_SEN_NEG' AKA1762-1 DCDC3-6 # Negative SENSE input pin - Pin #6 # # DC/DC Converter Output Voltage Rset Resistor # with capacitor across the variable part of the Vout Rset Resistor # # NOTE: Ground Reference not Negative Sense Reference NET 'GROUND' R1763-1 R1763-2 # Want Trim Pot CW Truning to: NET 'DCDC3_VAR_FIX' R1763-3 # Reduce the Resistance and NET 'DCDC3_VAR_FIX' R1762-2 # Increase the Output Voltage NET 'DCDC3_VO_ADJ' R1762-1 DCDC3-7 # Converter Rset Vout Adj pin - Pin #7 NET 'DCDC3_VAR_FIX' C1777-1 # Capacitor across the NET 'GROUND' C1777-2 # Vout Trim Pot Resistor # # DC/DC Converter Transient Response Control Pin NET 'DCDC3_TRC_PIN' R1764-2 DCDC3-8 # Transient Response Control pin - Pin #8 NET 'DCDC3_SEN_POS' R1764-1 # Transient Response Resistor # # DC/DC Converter INH-UVLO Pin and Resistor NET 'DCDC3_INH_UVLO' R1765-1 DCDC3-10 # INH-UVLO Pin #10 NET 'GROUND' R1765-2 # Ground end of UVLO Resistor # # DC/DC Converter Sync Pin tied to Ground via trace NET 'DCDC3_SYNC' AKA1763-1 DCDC3-1 # Converter's SYNC Pin - Pin #1 NET 'GROUND' AKA1763-2 # Tie SYNC Pin to Ground # # Current Sense Resistor to Filter and to Current Monitor Connector Pins NET 'DCDC3_CS_POS' R1761-4 R1766-1 # Current Sense Res. to Filter Res. NET 'DCDC3_CS_NEG' R1761-1 R1767-1 # Current Sense Res. to Filter Res. NET 'IMON_POS_BULK_1V2' R1766-2 C1778-1 # Current Monitor Filter Res Cap Pin NET 'IMON_NEG_BULK_1V2' R1767-2 C1780-2 # Current Monitor Filter Res Cap Pin NET 'IMON_POS_BULK_1V2' C1779-1 # Current Monitor Shunt Cap NET 'IMON_NEG_BULK_1V2' C1779-2 # Current Monitor Shunt Cap NET 'GROUND' C1778-2 C1780-1 # Current Monitor Filter Cap Grounds # # Voltage Monitor Filter and to Voltage Monitor Connector Pin NET 'Bulk_1V2' R1768-1 # Voltage Monitor Filter Resistor NET 'VMON_BULK_1V2' R1768-2 C1781-1 # Voltage Monitor Filter Res Cap Pin NET 'GROUND' C1781-2 # Voltage Monitor Filter Cap Ground # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:40 2020 # MIGT> begin substituting from -- instance #4/6 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # DCDC Converter Net List Template File # ----------------========--========------- # # # Original Rev. 5-Feb-2023 # Most Recent Rev. 17-Nov-2023 # # # # This Template file holds the nets for the DK # DC/DC Power Converters. These converters run # from the BULK_5V0 bus and it make the 6 BULK # power rails that are used by the DK board itself. # # # For reference recall the 6 DCDC Converters on DK: # # Output # Converter Ref. Power Output Expected Output Power Trends # Name Desig Bus Voltage Load Capacity Model Number # --------- ----- --------- ------- ----------- -------- ------------ # # DCDC1 1701 Bulk_1V00 1.00 V about 1.4 A 3 A PTH04T260WAD # DCDC2 1731 Bulk_1V05 1.05 V under 3.0 A 6 A PTH04T230WAD # DCDC3 1761 Bulk_1V2 1.20 V about 4.0 A 6 A PTH04T230WAD # DCDC4 1791 Bulk_1V8 1.80 V under 1.5 A 3 A PTH04T260WAD # DCDC5 1821 Bulk_2V5 2.50 V about 1.4 A 3 A PTH04T260WAD # DCDC6 1851 Bulk_3V3 3.30 V under 1.5 A 3 A PTH04T260WAD # # # # Define the Connections within the DCDC Power Converter # --------------------------------------------------------- # # # Input Power to the Converter: NET 'BULK_5V0' R1791-2 # Power to the Current Sense Resistor NET 'DCDC4_CSR_TO_L' R1791-3 # Power from the Current Sense NET 'DCDC4_CSR_TO_L' L1791-1 # Resistor to the Filter Inductor NET 'DCDC4_INPUT' L1791-2 # Power feed to the Converter NET 'DCDC4_INPUT' C1791-1 C1792-1 # Tantalum Input Caps NET 'DCDC4_INPUT' C1793-1 C1794-1 # Tantalum Input Caps NET 'DCDC4_INPUT' C1795-2 C1796-1 # Ceramic Input Caps NET 'DCDC4_INPUT' C1797-2 C1798-2 # Ceramic Input Caps NET 'DCDC4_INPUT' DCDC4-2 # Power Input to the Converter - Pin #2 NET 'GROUND' C1791-2 C1792-2 # Tantalum Cap Grounds NET 'GROUND' C1793-2 C1794-2 # Taltalum Cap Grounds NET 'GROUND' C1795-1 C1796-2 # Ceramic Cap Grounds NET 'GROUND' C1797-1 C1798-1 # Ceramic Cap Grounds # # Power Output from the Converter: NET 'Bulk_1V8' DCDC4-4 # Output Power from the Converter - Pin #4 NET 'Bulk_1V8' C1799-1 C1800-1 # Ceramic Output Caps NET 'Bulk_1V8' C1801-2 C1802-1 # Ceramic Output Caps NET 'Bulk_1V8' C1803-1 C1804-1 # Tantalum Output Caps NET 'Bulk_1V8' C1805-1 C1806-1 # Tantalum Output Caps NET 'Bulk_1V8' DZ1791-1 # Output Zener Clamp NET 'GROUND' C1799-2 C1800-2 # Ceramic Cap Grounds NET 'GROUND' C1801-1 C1802-2 # Ceramic Cap Grounds NET 'GROUND' C1803-2 C1804-2 # Tantalum Cap Grounds NET 'GROUND' C1805-2 C1806-2 # Tantalum Cap Grounds NET 'GROUND' DZ1791-2 # Zener Clamp Ground # # DC/DC Converter GROUND Pins NET 'GROUND' DCDC4-3 # Converter Ground Pin - Pin #3 NET 'GROUND' DCDC4-31 DCDC4-32 # Converter Auxiliary Ground Pins # # DC/DC Converter Tracking Pin NET 'DCDC_CONV_TRACK' DCDC4-9 # TRACK Pin of this DCDC Converter - Pin #9 # # DC/DC Converter Feedback Remote Sense Pins NET 'Bulk_1V8' AKA1791-2 # Positive SENSE Remote Connection NET 'DCDC4_SEN_POS' AKA1791-1 DCDC4-5 # Positive SENSE input pin - Pin #5 NET 'GROUND' AKA1792-2 # Negative SENSE Remote Connection NET 'DCDC4_SEN_NEG' AKA1792-1 DCDC4-6 # Negative SENSE input pin - Pin #6 # # DC/DC Converter Output Voltage Rset Resistor # with capacitor across the variable part of the Vout Rset Resistor # # NOTE: Ground Reference not Negative Sense Reference NET 'GROUND' R1793-1 R1793-2 # Want Trim Pot CW Truning to: NET 'DCDC4_VAR_FIX' R1793-3 # Reduce the Resistance and NET 'DCDC4_VAR_FIX' R1792-2 # Increase the Output Voltage NET 'DCDC4_VO_ADJ' R1792-1 DCDC4-7 # Converter Rset Vout Adj pin - Pin #7 NET 'DCDC4_VAR_FIX' C1807-1 # Capacitor across the NET 'GROUND' C1807-2 # Vout Trim Pot Resistor # # DC/DC Converter Transient Response Control Pin NET 'DCDC4_TRC_PIN' R1794-2 DCDC4-8 # Transient Response Control pin - Pin #8 NET 'DCDC4_SEN_POS' R1794-1 # Transient Response Resistor # # DC/DC Converter INH-UVLO Pin and Resistor NET 'DCDC4_INH_UVLO' R1795-1 DCDC4-10 # INH-UVLO Pin #10 NET 'GROUND' R1795-2 # Ground end of UVLO Resistor # # DC/DC Converter Sync Pin tied to Ground via trace NET 'DCDC4_SYNC' AKA1793-1 DCDC4-1 # Converter's SYNC Pin - Pin #1 NET 'GROUND' AKA1793-2 # Tie SYNC Pin to Ground # # Current Sense Resistor to Filter and to Current Monitor Connector Pins NET 'DCDC4_CS_POS' R1791-4 R1796-1 # Current Sense Res. to Filter Res. NET 'DCDC4_CS_NEG' R1791-1 R1797-1 # Current Sense Res. to Filter Res. NET 'IMON_POS_BULK_1V8' R1796-2 C1808-1 # Current Monitor Filter Res Cap Pin NET 'IMON_NEG_BULK_1V8' R1797-2 C1810-2 # Current Monitor Filter Res Cap Pin NET 'IMON_POS_BULK_1V8' C1809-1 # Current Monitor Shunt Cap NET 'IMON_NEG_BULK_1V8' C1809-2 # Current Monitor Shunt Cap NET 'GROUND' C1808-2 C1810-1 # Current Monitor Filter Cap Grounds # # Voltage Monitor Filter and to Voltage Monitor Connector Pin NET 'Bulk_1V8' R1798-1 # Voltage Monitor Filter Resistor NET 'VMON_BULK_1V8' R1798-2 C1811-1 # Voltage Monitor Filter Res Cap Pin NET 'GROUND' C1811-2 # Voltage Monitor Filter Cap Ground # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:40 2020 # MIGT> begin substituting from -- instance #5/6 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # DCDC Converter Net List Template File # ----------------========--========------- # # # Original Rev. 5-Feb-2023 # Most Recent Rev. 17-Nov-2023 # # # # This Template file holds the nets for the DK # DC/DC Power Converters. These converters run # from the BULK_5V0 bus and it make the 6 BULK # power rails that are used by the DK board itself. # # # For reference recall the 6 DCDC Converters on DK: # # Output # Converter Ref. Power Output Expected Output Power Trends # Name Desig Bus Voltage Load Capacity Model Number # --------- ----- --------- ------- ----------- -------- ------------ # # DCDC1 1701 Bulk_1V00 1.00 V about 1.4 A 3 A PTH04T260WAD # DCDC2 1731 Bulk_1V05 1.05 V under 3.0 A 6 A PTH04T230WAD # DCDC3 1761 Bulk_1V2 1.20 V about 4.0 A 6 A PTH04T230WAD # DCDC4 1791 Bulk_1V8 1.80 V under 1.5 A 3 A PTH04T260WAD # DCDC5 1821 Bulk_2V5 2.50 V about 1.4 A 3 A PTH04T260WAD # DCDC6 1851 Bulk_3V3 3.30 V under 1.5 A 3 A PTH04T260WAD # # # # Define the Connections within the DCDC Power Converter # --------------------------------------------------------- # # # Input Power to the Converter: NET 'BULK_5V0' R1821-2 # Power to the Current Sense Resistor NET 'DCDC5_CSR_TO_L' R1821-3 # Power from the Current Sense NET 'DCDC5_CSR_TO_L' L1821-1 # Resistor to the Filter Inductor NET 'DCDC5_INPUT' L1821-2 # Power feed to the Converter NET 'DCDC5_INPUT' C1821-1 C1822-1 # Tantalum Input Caps NET 'DCDC5_INPUT' C1823-1 C1824-1 # Tantalum Input Caps NET 'DCDC5_INPUT' C1825-2 C1826-1 # Ceramic Input Caps NET 'DCDC5_INPUT' C1827-2 C1828-2 # Ceramic Input Caps NET 'DCDC5_INPUT' DCDC5-2 # Power Input to the Converter - Pin #2 NET 'GROUND' C1821-2 C1822-2 # Tantalum Cap Grounds NET 'GROUND' C1823-2 C1824-2 # Taltalum Cap Grounds NET 'GROUND' C1825-1 C1826-2 # Ceramic Cap Grounds NET 'GROUND' C1827-1 C1828-1 # Ceramic Cap Grounds # # Power Output from the Converter: NET 'Bulk_2V5' DCDC5-4 # Output Power from the Converter - Pin #4 NET 'Bulk_2V5' C1829-1 C1830-1 # Ceramic Output Caps NET 'Bulk_2V5' C1831-2 C1832-1 # Ceramic Output Caps NET 'Bulk_2V5' C1833-1 C1834-1 # Tantalum Output Caps NET 'Bulk_2V5' C1835-1 C1836-1 # Tantalum Output Caps NET 'Bulk_2V5' DZ1821-1 # Output Zener Clamp NET 'GROUND' C1829-2 C1830-2 # Ceramic Cap Grounds NET 'GROUND' C1831-1 C1832-2 # Ceramic Cap Grounds NET 'GROUND' C1833-2 C1834-2 # Tantalum Cap Grounds NET 'GROUND' C1835-2 C1836-2 # Tantalum Cap Grounds NET 'GROUND' DZ1821-2 # Zener Clamp Ground # # DC/DC Converter GROUND Pins NET 'GROUND' DCDC5-3 # Converter Ground Pin - Pin #3 NET 'GROUND' DCDC5-31 DCDC5-32 # Converter Auxiliary Ground Pins # # DC/DC Converter Tracking Pin NET 'DCDC_CONV_TRACK' DCDC5-9 # TRACK Pin of this DCDC Converter - Pin #9 # # DC/DC Converter Feedback Remote Sense Pins NET 'Bulk_2V5' AKA1821-2 # Positive SENSE Remote Connection NET 'DCDC5_SEN_POS' AKA1821-1 DCDC5-5 # Positive SENSE input pin - Pin #5 NET 'GROUND' AKA1822-2 # Negative SENSE Remote Connection NET 'DCDC5_SEN_NEG' AKA1822-1 DCDC5-6 # Negative SENSE input pin - Pin #6 # # DC/DC Converter Output Voltage Rset Resistor # with capacitor across the variable part of the Vout Rset Resistor # # NOTE: Ground Reference not Negative Sense Reference NET 'GROUND' R1823-1 R1823-2 # Want Trim Pot CW Truning to: NET 'DCDC5_VAR_FIX' R1823-3 # Reduce the Resistance and NET 'DCDC5_VAR_FIX' R1822-2 # Increase the Output Voltage NET 'DCDC5_VO_ADJ' R1822-1 DCDC5-7 # Converter Rset Vout Adj pin - Pin #7 NET 'DCDC5_VAR_FIX' C1837-1 # Capacitor across the NET 'GROUND' C1837-2 # Vout Trim Pot Resistor # # DC/DC Converter Transient Response Control Pin NET 'DCDC5_TRC_PIN' R1824-2 DCDC5-8 # Transient Response Control pin - Pin #8 NET 'DCDC5_SEN_POS' R1824-1 # Transient Response Resistor # # DC/DC Converter INH-UVLO Pin and Resistor NET 'DCDC5_INH_UVLO' R1825-1 DCDC5-10 # INH-UVLO Pin #10 NET 'GROUND' R1825-2 # Ground end of UVLO Resistor # # DC/DC Converter Sync Pin tied to Ground via trace NET 'DCDC5_SYNC' AKA1823-1 DCDC5-1 # Converter's SYNC Pin - Pin #1 NET 'GROUND' AKA1823-2 # Tie SYNC Pin to Ground # # Current Sense Resistor to Filter and to Current Monitor Connector Pins NET 'DCDC5_CS_POS' R1821-4 R1826-1 # Current Sense Res. to Filter Res. NET 'DCDC5_CS_NEG' R1821-1 R1827-1 # Current Sense Res. to Filter Res. NET 'IMON_POS_BULK_2V5' R1826-2 C1838-1 # Current Monitor Filter Res Cap Pin NET 'IMON_NEG_BULK_2V5' R1827-2 C1840-2 # Current Monitor Filter Res Cap Pin NET 'IMON_POS_BULK_2V5' C1839-1 # Current Monitor Shunt Cap NET 'IMON_NEG_BULK_2V5' C1839-2 # Current Monitor Shunt Cap NET 'GROUND' C1838-2 C1840-1 # Current Monitor Filter Cap Grounds # # Voltage Monitor Filter and to Voltage Monitor Connector Pin NET 'Bulk_2V5' R1828-1 # Voltage Monitor Filter Resistor NET 'VMON_BULK_2V5' R1828-2 C1841-1 # Voltage Monitor Filter Res Cap Pin NET 'GROUND' C1841-2 # Voltage Monitor Filter Cap Ground # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:40 2020 # MIGT> begin substituting from -- instance #6/6 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # DCDC Converter Net List Template File # ----------------========--========------- # # # Original Rev. 5-Feb-2023 # Most Recent Rev. 17-Nov-2023 # # # # This Template file holds the nets for the DK # DC/DC Power Converters. These converters run # from the BULK_5V0 bus and it make the 6 BULK # power rails that are used by the DK board itself. # # # For reference recall the 6 DCDC Converters on DK: # # Output # Converter Ref. Power Output Expected Output Power Trends # Name Desig Bus Voltage Load Capacity Model Number # --------- ----- --------- ------- ----------- -------- ------------ # # DCDC1 1701 Bulk_1V00 1.00 V about 1.4 A 3 A PTH04T260WAD # DCDC2 1731 Bulk_1V05 1.05 V under 3.0 A 6 A PTH04T230WAD # DCDC3 1761 Bulk_1V2 1.20 V about 4.0 A 6 A PTH04T230WAD # DCDC4 1791 Bulk_1V8 1.80 V under 1.5 A 3 A PTH04T260WAD # DCDC5 1821 Bulk_2V5 2.50 V about 1.4 A 3 A PTH04T260WAD # DCDC6 1851 Bulk_3V3 3.30 V under 1.5 A 3 A PTH04T260WAD # # # # Define the Connections within the DCDC Power Converter # --------------------------------------------------------- # # # Input Power to the Converter: NET 'BULK_5V0' R1851-2 # Power to the Current Sense Resistor NET 'DCDC6_CSR_TO_L' R1851-3 # Power from the Current Sense NET 'DCDC6_CSR_TO_L' L1851-1 # Resistor to the Filter Inductor NET 'DCDC6_INPUT' L1851-2 # Power feed to the Converter NET 'DCDC6_INPUT' C1851-1 C1852-1 # Tantalum Input Caps NET 'DCDC6_INPUT' C1853-1 C1854-1 # Tantalum Input Caps NET 'DCDC6_INPUT' C1855-2 C1856-1 # Ceramic Input Caps NET 'DCDC6_INPUT' C1857-2 C1858-2 # Ceramic Input Caps NET 'DCDC6_INPUT' DCDC6-2 # Power Input to the Converter - Pin #2 NET 'GROUND' C1851-2 C1852-2 # Tantalum Cap Grounds NET 'GROUND' C1853-2 C1854-2 # Taltalum Cap Grounds NET 'GROUND' C1855-1 C1856-2 # Ceramic Cap Grounds NET 'GROUND' C1857-1 C1858-1 # Ceramic Cap Grounds # # Power Output from the Converter: NET 'Bulk_3V3' DCDC6-4 # Output Power from the Converter - Pin #4 NET 'Bulk_3V3' C1859-1 C1860-1 # Ceramic Output Caps NET 'Bulk_3V3' C1861-2 C1862-1 # Ceramic Output Caps NET 'Bulk_3V3' C1863-1 C1864-1 # Tantalum Output Caps NET 'Bulk_3V3' C1865-1 C1866-1 # Tantalum Output Caps NET 'Bulk_3V3' DZ1851-1 # Output Zener Clamp NET 'GROUND' C1859-2 C1860-2 # Ceramic Cap Grounds NET 'GROUND' C1861-1 C1862-2 # Ceramic Cap Grounds NET 'GROUND' C1863-2 C1864-2 # Tantalum Cap Grounds NET 'GROUND' C1865-2 C1866-2 # Tantalum Cap Grounds NET 'GROUND' DZ1851-2 # Zener Clamp Ground # # DC/DC Converter GROUND Pins NET 'GROUND' DCDC6-3 # Converter Ground Pin - Pin #3 NET 'GROUND' DCDC6-31 DCDC6-32 # Converter Auxiliary Ground Pins # # DC/DC Converter Tracking Pin NET 'DCDC_CONV_TRACK' DCDC6-9 # TRACK Pin of this DCDC Converter - Pin #9 # # DC/DC Converter Feedback Remote Sense Pins NET 'Bulk_3V3' AKA1851-2 # Positive SENSE Remote Connection NET 'DCDC6_SEN_POS' AKA1851-1 DCDC6-5 # Positive SENSE input pin - Pin #5 NET 'GROUND' AKA1852-2 # Negative SENSE Remote Connection NET 'DCDC6_SEN_NEG' AKA1852-1 DCDC6-6 # Negative SENSE input pin - Pin #6 # # DC/DC Converter Output Voltage Rset Resistor # with capacitor across the variable part of the Vout Rset Resistor # # NOTE: Ground Reference not Negative Sense Reference NET 'GROUND' R1853-1 R1853-2 # Want Trim Pot CW Truning to: NET 'DCDC6_VAR_FIX' R1853-3 # Reduce the Resistance and NET 'DCDC6_VAR_FIX' R1852-2 # Increase the Output Voltage NET 'DCDC6_VO_ADJ' R1852-1 DCDC6-7 # Converter Rset Vout Adj pin - Pin #7 NET 'DCDC6_VAR_FIX' C1867-1 # Capacitor across the NET 'GROUND' C1867-2 # Vout Trim Pot Resistor # # DC/DC Converter Transient Response Control Pin NET 'DCDC6_TRC_PIN' R1854-2 DCDC6-8 # Transient Response Control pin - Pin #8 NET 'DCDC6_SEN_POS' R1854-1 # Transient Response Resistor # # DC/DC Converter INH-UVLO Pin and Resistor NET 'DCDC6_INH_UVLO' R1855-1 DCDC6-10 # INH-UVLO Pin #10 NET 'GROUND' R1855-2 # Ground end of UVLO Resistor # # DC/DC Converter Sync Pin tied to Ground via trace NET 'DCDC6_SYNC' AKA1853-1 DCDC6-1 # Converter's SYNC Pin - Pin #1 NET 'GROUND' AKA1853-2 # Tie SYNC Pin to Ground # # Current Sense Resistor to Filter and to Current Monitor Connector Pins NET 'DCDC6_CS_POS' R1851-4 R1856-1 # Current Sense Res. to Filter Res. NET 'DCDC6_CS_NEG' R1851-1 R1857-1 # Current Sense Res. to Filter Res. NET 'IMON_POS_BULK_3V3' R1856-2 C1868-1 # Current Monitor Filter Res Cap Pin NET 'IMON_NEG_BULK_3V3' R1857-2 C1870-2 # Current Monitor Filter Res Cap Pin NET 'IMON_POS_BULK_3V3' C1869-1 # Current Monitor Shunt Cap NET 'IMON_NEG_BULK_3V3' C1869-2 # Current Monitor Shunt Cap NET 'GROUND' C1868-2 C1870-1 # Current Monitor Filter Cap Grounds # # Voltage Monitor Filter and to Voltage Monitor Connector Pin NET 'Bulk_3V3' R1858-1 # Voltage Monitor Filter Resistor NET 'VMON_BULK_3V3' R1858-2 C1871-1 # Voltage Monitor Filter Res Cap Pin NET 'GROUND' C1871-2 # Voltage Monitor Filter Cap Ground # MIGT>---------------------------------------------- # MIGT> done substituting from # # Power Input Net List # ----------------------- # # Initial Rev. 7-Feb-2023 # Current Rev. 25-Nov-2023 # # This net list file contains all of the connections within # the Power Input Filter and within the +100 V to +5 V # Converter. # # This net list file also assigns net names to all # 26 pins in the Main Cable Connector J1. # # # Power Input Filter Nets # NET 'Power_Input' C1651-2 C1652-2 L1651-1 # Input to the NET 'Power Return' C1651-1 C1652-1 L1651-4 # Common Mode Choke NET 'Inter_Choke_Pos' L1651-2 C1653-1 # Inter Choke NET 'Inter_Choke_Pos' C1654-2 C1655-2 L1652-2 # Positive NET 'Fltrd_Power_Pos' L1652-1 C1656-2 # Filtered NET 'Fltrd_Power_Pos' C1657-2 C1658-2 # +100 V Power NET 'Fltrd_Rtn_Power' L1651-3 C1653-2 # Filtered NET 'Fltrd_Rtn_Power' C1654-1 C1655-1 # Return NET 'Fltrd_Rtn_Power' C1656-1 # Power NET 'Fltrd_Rtn_Power' C1657-1 C1658-1 # # # Input Power Return to Signal Ground Link (If Wanted) # # If needed, NET 'Power Return' R1651-1 # Control the Potential Difference NET 'GROUND' R1651-2 # between Power Return & Signal Ground # # Power Into the 100 V to 5 V Converter # NET 'Fltrd_Power_Pos' DCDC20-1 # Positive 100V to Converter NET 'Fltrd_Rtn_Power' DCDC20-2 # Power Return from Converter # # Remote ON/OFF Control of the 100 V to 5 V Converter # NET 'NO_CONN_dcdc20_pin_6' DCDC20-6 # Float this pin for Always ON # # Output from the 100 V to 5 V Converter # NET 'BULK_5V0' DCDC20-3 # Converter's Positive NET 'BULK_5V0' C1659-2 C1660-2 # Output and Ceramic NET 'BULK_5V0' C1661-2 C1662-2 # Filter Capacitors NET 'GROUND' DCDC20-5 # Converter's Negative NET 'GROUND' C1659-1 C1660-1 # Output and Ceramic NET 'GROUND' C1661-1 C1662-1 # Filter Capacitors # # Voltage Trim Resistors on the 100 V to 5 V Converter # NET 'BULK_5V0' R1652-2 # Resistors to NET 'TRIM_BULK_5V0' R1652-1 DCDC20-4 # Trim the NET 'TRIM_BULK_5V0' R1653-2 # BULK_5V0 NET 'GROUND' R1653-1 # Voltage # # Voltage Monitor Filter on the 100 V to 5 V Converter # NET 'BULK_5V0' R1654-1 # Voltage Monitor NET 'VMON_BULK_5V0' R1654-2 C1663-2 # Filter on the NET 'GROUND' C1663-1 # BULK_5V0 # # Assign Net_Names to all Pin on the Main Cable J1 Connector # NET 'GROUND' J1-1 # Module Signal Ground NET 'GROUND' J1-2 # Module Signal Ground NET 'NO_CONN_J1_pin_3' J1-3 # Open Guard Around 100V NET 'NO_CONN_J1_pin_4' J1-4 # Open Guard Around 100V NET 'Power_Input' J1-5 # +100 Volt Input Power NET 'NO_CONN_J1_pin_6' J1-6 # Open Guard Around 100V NET 'NO_CONN_J1_pin_7' J1-7 # Open Guard Around 100V NET 'Power Return' J1-8 # Return Conductor for Input Power NET 'NO_CONN_J1_pin_9' J1-9 # Open Guard Around 100V NET 'NO_CONN_J1_pin_10' J1-10 # Open Guard Around 100V NET 'GROUND' J1-11 # Module Signal Ground NET 'GROUND' J1-12 # Module Signal Ground NET 'RS485_DOWN_DIR' J1-13 # Re-Programm RS-485 NET 'RS485_DOWN_CMP' J1-14 # Down NET 'NO_CONN_J1_pin_15' J1-15 # Spare Pin - No Connection NET 'NO_CONN_J1_pin_16' J1-16 # Spare Pin - No Connection NET 'NO_CONN_J1_pin_17' J1-17 # Spare Pin - No Connection NET 'NO_CONN_J1_pin_18' J1-18 # Spare Pin - No Connection NET 'NO_CONN_J1_pin_19' J1-19 # Spare Pin - No Connection NET 'NO_CONN_J1_pin_20' J1-20 # Spare Pin - No Connection NET 'GROUND' J1-21 # Module Signal Ground NET 'GROUND' J1-22 # Module Signal Ground NET 'RS485_UP_DIR' J1-23 # Re-Programm RS-485 NET 'RS485_UP_CMP' J1-24 # Up NET 'GROUND' J1-25 # Module Signal Ground NET 'GROUND' J1-26 # Module Signal Ground NET 'GROUND' J1-27 # Mounting Screw Ground NET 'GROUND' J1-28 # Mounting Screw Ground # # Always ON 3V3 Power Supply Net List # --------------------------------------------- # # # Initial Rev. 14-Nov-2022 # Current Rev. 15-Nov-2023 # # # This net list holds the Always ON 3V3 Power Supply # Net List. # # # The components for the Always ON 3V3 Power Supply # are in the range 1971 to 1976. # # # Bulk_5V0 power into the Always ON 3V3 Power Supply # NET 'BULK_5V0' L1971-2 # Bulk Power Into Filter NET 'CNST_FLTR_POW' L1971-1 # Filtered Bulk Power NET 'CNST_FLTR_POW' C1971-2 C1972-1 U1971-5 # Filtered Power Into Regulator NET 'GROUND' C1971-1 C1972-2 # Ground Side of Filter Caps NET 'GROUND' U1971-2 U1971-3 U1971-4 # Regulator Grounds and Thermals NET 'CNST_FLTR_POW' U1971-1 # Enable Regulator # # Always_ON_3V3 Power Output # NET 'CNST_3V3' C1973-1 C1974-2 U1971-6 # Power Output NET 'GROUND' C1973-2 C1974-1 # # Always_ON_3V3 Feedback Resistors # NET 'CNST_3V3' R1971-2 NET 'CNST_3V3_FB' R1971-1 R1972-1 U1971-7 # Feedback to Regulator NET 'GROUND' R1972-2 # # Regulator Start-Up Timing # NET 'CNST_3V3_START' C1975-1 U1971-8 # Regulator Start-Up Timing Cap NET 'GROUND' C1975-2 # # Monitor for the Always ON 3V3 Power Supply # NET 'CNST_3V3' R1973-2 NET 'VMON_CNST_3V3' R1973-1 C1976-1 NET 'GROUND' C1976-2 # # Power Supply Monitor Net List # --------------------------------------------- # # # Initial Rev. 8-Nov-2022 # Current Rev. 17-Nov-2023 # # # This net list holds the Power Supply Monitor nets # (both Voltage and Current) that run to the J11 # Power Supply Monitor Connector. # # Pinout of the J11 Power Supply Monitor Connector: # # # Currently pins 33:40 are not assigned to # to a Monitor Function or have an assigned Net. # # # # Now the nets that run to J11: # # # Monitor for the 100 V to 5 V Comverter Output: # NET 'VMON_BULK_5V0' J11-1 NET 'GROUND' J11-2 # # Now monitor the Voltage Output and the Current Input # of the 6 DCDC Converters: # NET 'VMON_BULK_1V00' J11-3 NET 'GROUND' J11-4 NET 'IMON_POS_BULK_1V00' J11-5 NET 'IMON_NEG_BULK_1V00' J11-6 NET 'VMON_BULK_1V05' J11-7 NET 'GROUND' J11-8 NET 'IMON_POS_BULK_1V05' J11-9 NET 'IMON_NEG_BULK_1V05' J11-10 NET 'VMON_BULK_1V2' J11-11 NET 'GROUND' J11-12 NET 'IMON_POS_BULK_1V2' J11-13 NET 'IMON_NEG_BULK_1V2' J11-14 NET 'VMON_BULK_1V8' J11-15 NET 'GROUND' J11-16 NET 'IMON_POS_BULK_1V8' J11-17 NET 'IMON_NEG_BULK_1V8' J11-18 NET 'VMON_BULK_2V5' J11-19 NET 'GROUND' J11-20 NET 'IMON_POS_BULK_2V5' J11-21 NET 'IMON_NEG_BULK_2V5' J11-22 NET 'VMON_BULK_3V3' J11-23 NET 'GROUND' J11-24 NET 'IMON_POS_BULK_3V3' J11-25 NET 'IMON_NEG_BULK_3V3' J11-26 # # Now Monitor the Voltage Output of the # - Constant ON 3V3 Regulator # - Termination Supply for the FPGA DDR4 Reference # - Termination Supply for the CPU DDR4 Reference # NET 'VMON_CNST_3V3' J11-27 NET 'GROUND' J11-28 NET 'VMON_FPGA_DDR4_TERM' J11-29 NET 'GROUND' J11-30 NET 'VMON_CPU_DDR4_TERM' J11-31 NET 'GROUND' J11-32 # # For Now the rest of the J11 Pins # are No Connect nets. # NET 'NO_CONN_J11_pin_33' J11-33 NET 'NO_CONN_J11_pin_34' J11-34 NET 'NO_CONN_J11_pin_35' J11-35 NET 'NO_CONN_J11_pin_36' J11-36 NET 'NO_CONN_J11_pin_37' J11-37 NET 'NO_CONN_J11_pin_38' J11-38 NET 'NO_CONN_J11_pin_39' J11-39 NET 'NO_CONN_J11_pin_40' J11-40 # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #1/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH1_Input_Dir' TRN1-6 # Coax Input Center Conductor NET 'CH1_Input_Cmp' TRN1-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH1_Input_Cmp' JMP1-1 # Coax Input Shield to Jumper NET 'GROUND' JMP1-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH1_In_Split_Dir' TRN1-1 TVS1-1 # Input Sec to ESD Diode Dir NET 'CH1_In_Split_Cmp' TRN1-3 TVS1-2 # Input Sec to ESD Diode Cmp NET 'CH1_In_Split_Dir' TRN17-1 # Input Sec to Split Pri Dir NET 'CH1_In_Split_Cmp' TRN17-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN1-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH1_ADC_IN_Dir' TRN17-5 # Term and ADC In DIR NET 'CH1_ADC_IN_Dir' R683-1 # Term and ADC In DIR NET 'CH1_TERM_Dir' R683-2 # Terminator DIR NET 'CH1_TERM_Dir' C685-1 # Terminator DIR NET 'CH1_TERM_Dir' C686-2 # Terminator DIR NET 'GROUND' C685-2 C686-1 # Ground NET 'CH1_ADC_IN_Cmp' TRN17-3 # Term and ADC In CMP NET 'CH1_ADC_IN_Cmp' R684-1 # Term and ADC In CMP NET 'CH1_TERM_Cmp' R684-2 # Terminator CMP NET 'CH1_TERM_Cmp' C687-1 # Terminator CMP NET 'CH1_TERM_Cmp' C688-2 # Terminator CMP NET 'GROUND' C687-2 C688-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH1_Bias_Dir' TRN17-2 # Winding Low NET 'CH1_Bias_Dir' R682-2 # Winding Low to Res NET 'CH1_Bias_Dir' C683-2 # Winding Low to Cap NET 'CH1_Bias_Dir' C684-2 # Winding Low to Cap NET 'GROUND' R682-1 # Ground Res NET 'GROUND' C683-1 # Ground Cap NET 'GROUND' C684-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH1_Bias_Cmp' TRN17-4 # Winding Low NET 'CH1_Bias_Cmp' C681-1 # Winding Low to Cap NET 'CH1_Bias_Cmp' C682-1 # Winding Low to Cap NET 'CH1_Bias_Cmp' R681-1 # Winding Low to Res NET 'GROUND' C681-2 # Ground Cap NET 'GROUND' C682-2 # Ground Cap NET 'GROUND' R681-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #2/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH2_Input_Dir' TRN2-6 # Coax Input Center Conductor NET 'CH2_Input_Cmp' TRN2-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH2_Input_Cmp' JMP2-1 # Coax Input Shield to Jumper NET 'GROUND' JMP2-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH2_In_Split_Dir' TRN2-1 TVS2-1 # Input Sec to ESD Diode Dir NET 'CH2_In_Split_Cmp' TRN2-3 TVS2-2 # Input Sec to ESD Diode Cmp NET 'CH2_In_Split_Dir' TRN18-1 # Input Sec to Split Pri Dir NET 'CH2_In_Split_Cmp' TRN18-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN2-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH2_ADC_IN_Dir' TRN18-5 # Term and ADC In DIR NET 'CH2_ADC_IN_Dir' R693-1 # Term and ADC In DIR NET 'CH2_TERM_Dir' R693-2 # Terminator DIR NET 'CH2_TERM_Dir' C695-1 # Terminator DIR NET 'CH2_TERM_Dir' C696-2 # Terminator DIR NET 'GROUND' C695-2 C696-1 # Ground NET 'CH2_ADC_IN_Cmp' TRN18-3 # Term and ADC In CMP NET 'CH2_ADC_IN_Cmp' R694-1 # Term and ADC In CMP NET 'CH2_TERM_Cmp' R694-2 # Terminator CMP NET 'CH2_TERM_Cmp' C697-1 # Terminator CMP NET 'CH2_TERM_Cmp' C698-2 # Terminator CMP NET 'GROUND' C697-2 C698-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH2_Bias_Dir' TRN18-2 # Winding Low NET 'CH2_Bias_Dir' R692-2 # Winding Low to Res NET 'CH2_Bias_Dir' C693-2 # Winding Low to Cap NET 'CH2_Bias_Dir' C694-2 # Winding Low to Cap NET 'GROUND' R692-1 # Ground Res NET 'GROUND' C693-1 # Ground Cap NET 'GROUND' C694-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH2_Bias_Cmp' TRN18-4 # Winding Low NET 'CH2_Bias_Cmp' C691-1 # Winding Low to Cap NET 'CH2_Bias_Cmp' C692-1 # Winding Low to Cap NET 'CH2_Bias_Cmp' R691-1 # Winding Low to Res NET 'GROUND' C691-2 # Ground Cap NET 'GROUND' C692-2 # Ground Cap NET 'GROUND' R691-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #3/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH3_Input_Dir' TRN3-6 # Coax Input Center Conductor NET 'CH3_Input_Cmp' TRN3-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH3_Input_Cmp' JMP3-1 # Coax Input Shield to Jumper NET 'GROUND' JMP3-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH3_In_Split_Dir' TRN3-1 TVS3-1 # Input Sec to ESD Diode Dir NET 'CH3_In_Split_Cmp' TRN3-3 TVS3-2 # Input Sec to ESD Diode Cmp NET 'CH3_In_Split_Dir' TRN19-1 # Input Sec to Split Pri Dir NET 'CH3_In_Split_Cmp' TRN19-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN3-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH3_ADC_IN_Dir' TRN19-5 # Term and ADC In DIR NET 'CH3_ADC_IN_Dir' R703-1 # Term and ADC In DIR NET 'CH3_TERM_Dir' R703-2 # Terminator DIR NET 'CH3_TERM_Dir' C705-1 # Terminator DIR NET 'CH3_TERM_Dir' C706-2 # Terminator DIR NET 'GROUND' C705-2 C706-1 # Ground NET 'CH3_ADC_IN_Cmp' TRN19-3 # Term and ADC In CMP NET 'CH3_ADC_IN_Cmp' R704-1 # Term and ADC In CMP NET 'CH3_TERM_Cmp' R704-2 # Terminator CMP NET 'CH3_TERM_Cmp' C707-1 # Terminator CMP NET 'CH3_TERM_Cmp' C708-2 # Terminator CMP NET 'GROUND' C707-2 C708-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH3_Bias_Dir' TRN19-2 # Winding Low NET 'CH3_Bias_Dir' R702-2 # Winding Low to Res NET 'CH3_Bias_Dir' C703-2 # Winding Low to Cap NET 'CH3_Bias_Dir' C704-2 # Winding Low to Cap NET 'GROUND' R702-1 # Ground Res NET 'GROUND' C703-1 # Ground Cap NET 'GROUND' C704-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH3_Bias_Cmp' TRN19-4 # Winding Low NET 'CH3_Bias_Cmp' C701-1 # Winding Low to Cap NET 'CH3_Bias_Cmp' C702-1 # Winding Low to Cap NET 'CH3_Bias_Cmp' R701-1 # Winding Low to Res NET 'GROUND' C701-2 # Ground Cap NET 'GROUND' C702-2 # Ground Cap NET 'GROUND' R701-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #4/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH4_Input_Dir' TRN4-6 # Coax Input Center Conductor NET 'CH4_Input_Cmp' TRN4-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH4_Input_Cmp' JMP4-1 # Coax Input Shield to Jumper NET 'GROUND' JMP4-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH4_In_Split_Dir' TRN4-1 TVS4-1 # Input Sec to ESD Diode Dir NET 'CH4_In_Split_Cmp' TRN4-3 TVS4-2 # Input Sec to ESD Diode Cmp NET 'CH4_In_Split_Dir' TRN20-1 # Input Sec to Split Pri Dir NET 'CH4_In_Split_Cmp' TRN20-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN4-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH4_ADC_IN_Dir' TRN20-5 # Term and ADC In DIR NET 'CH4_ADC_IN_Dir' R713-1 # Term and ADC In DIR NET 'CH4_TERM_Dir' R713-2 # Terminator DIR NET 'CH4_TERM_Dir' C715-1 # Terminator DIR NET 'CH4_TERM_Dir' C716-2 # Terminator DIR NET 'GROUND' C715-2 C716-1 # Ground NET 'CH4_ADC_IN_Cmp' TRN20-3 # Term and ADC In CMP NET 'CH4_ADC_IN_Cmp' R714-1 # Term and ADC In CMP NET 'CH4_TERM_Cmp' R714-2 # Terminator CMP NET 'CH4_TERM_Cmp' C717-1 # Terminator CMP NET 'CH4_TERM_Cmp' C718-2 # Terminator CMP NET 'GROUND' C717-2 C718-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH4_Bias_Dir' TRN20-2 # Winding Low NET 'CH4_Bias_Dir' R712-2 # Winding Low to Res NET 'CH4_Bias_Dir' C713-2 # Winding Low to Cap NET 'CH4_Bias_Dir' C714-2 # Winding Low to Cap NET 'GROUND' R712-1 # Ground Res NET 'GROUND' C713-1 # Ground Cap NET 'GROUND' C714-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH4_Bias_Cmp' TRN20-4 # Winding Low NET 'CH4_Bias_Cmp' C711-1 # Winding Low to Cap NET 'CH4_Bias_Cmp' C712-1 # Winding Low to Cap NET 'CH4_Bias_Cmp' R711-1 # Winding Low to Res NET 'GROUND' C711-2 # Ground Cap NET 'GROUND' C712-2 # Ground Cap NET 'GROUND' R711-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #5/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH5_Input_Dir' TRN5-6 # Coax Input Center Conductor NET 'CH5_Input_Cmp' TRN5-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH5_Input_Cmp' JMP5-1 # Coax Input Shield to Jumper NET 'GROUND' JMP5-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH5_In_Split_Dir' TRN5-1 TVS5-1 # Input Sec to ESD Diode Dir NET 'CH5_In_Split_Cmp' TRN5-3 TVS5-2 # Input Sec to ESD Diode Cmp NET 'CH5_In_Split_Dir' TRN21-1 # Input Sec to Split Pri Dir NET 'CH5_In_Split_Cmp' TRN21-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN5-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH5_ADC_IN_Dir' TRN21-5 # Term and ADC In DIR NET 'CH5_ADC_IN_Dir' R723-1 # Term and ADC In DIR NET 'CH5_TERM_Dir' R723-2 # Terminator DIR NET 'CH5_TERM_Dir' C725-1 # Terminator DIR NET 'CH5_TERM_Dir' C726-2 # Terminator DIR NET 'GROUND' C725-2 C726-1 # Ground NET 'CH5_ADC_IN_Cmp' TRN21-3 # Term and ADC In CMP NET 'CH5_ADC_IN_Cmp' R724-1 # Term and ADC In CMP NET 'CH5_TERM_Cmp' R724-2 # Terminator CMP NET 'CH5_TERM_Cmp' C727-1 # Terminator CMP NET 'CH5_TERM_Cmp' C728-2 # Terminator CMP NET 'GROUND' C727-2 C728-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH5_Bias_Dir' TRN21-2 # Winding Low NET 'CH5_Bias_Dir' R722-2 # Winding Low to Res NET 'CH5_Bias_Dir' C723-2 # Winding Low to Cap NET 'CH5_Bias_Dir' C724-2 # Winding Low to Cap NET 'GROUND' R722-1 # Ground Res NET 'GROUND' C723-1 # Ground Cap NET 'GROUND' C724-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH5_Bias_Cmp' TRN21-4 # Winding Low NET 'CH5_Bias_Cmp' C721-1 # Winding Low to Cap NET 'CH5_Bias_Cmp' C722-1 # Winding Low to Cap NET 'CH5_Bias_Cmp' R721-1 # Winding Low to Res NET 'GROUND' C721-2 # Ground Cap NET 'GROUND' C722-2 # Ground Cap NET 'GROUND' R721-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #6/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH6_Input_Dir' TRN6-6 # Coax Input Center Conductor NET 'CH6_Input_Cmp' TRN6-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH6_Input_Cmp' JMP6-1 # Coax Input Shield to Jumper NET 'GROUND' JMP6-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH6_In_Split_Dir' TRN6-1 TVS6-1 # Input Sec to ESD Diode Dir NET 'CH6_In_Split_Cmp' TRN6-3 TVS6-2 # Input Sec to ESD Diode Cmp NET 'CH6_In_Split_Dir' TRN22-1 # Input Sec to Split Pri Dir NET 'CH6_In_Split_Cmp' TRN22-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN6-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH6_ADC_IN_Dir' TRN22-5 # Term and ADC In DIR NET 'CH6_ADC_IN_Dir' R733-1 # Term and ADC In DIR NET 'CH6_TERM_Dir' R733-2 # Terminator DIR NET 'CH6_TERM_Dir' C735-1 # Terminator DIR NET 'CH6_TERM_Dir' C736-2 # Terminator DIR NET 'GROUND' C735-2 C736-1 # Ground NET 'CH6_ADC_IN_Cmp' TRN22-3 # Term and ADC In CMP NET 'CH6_ADC_IN_Cmp' R734-1 # Term and ADC In CMP NET 'CH6_TERM_Cmp' R734-2 # Terminator CMP NET 'CH6_TERM_Cmp' C737-1 # Terminator CMP NET 'CH6_TERM_Cmp' C738-2 # Terminator CMP NET 'GROUND' C737-2 C738-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH6_Bias_Dir' TRN22-2 # Winding Low NET 'CH6_Bias_Dir' R732-2 # Winding Low to Res NET 'CH6_Bias_Dir' C733-2 # Winding Low to Cap NET 'CH6_Bias_Dir' C734-2 # Winding Low to Cap NET 'GROUND' R732-1 # Ground Res NET 'GROUND' C733-1 # Ground Cap NET 'GROUND' C734-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH6_Bias_Cmp' TRN22-4 # Winding Low NET 'CH6_Bias_Cmp' C731-1 # Winding Low to Cap NET 'CH6_Bias_Cmp' C732-1 # Winding Low to Cap NET 'CH6_Bias_Cmp' R731-1 # Winding Low to Res NET 'GROUND' C731-2 # Ground Cap NET 'GROUND' C732-2 # Ground Cap NET 'GROUND' R731-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #7/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH7_Input_Dir' TRN7-6 # Coax Input Center Conductor NET 'CH7_Input_Cmp' TRN7-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH7_Input_Cmp' JMP7-1 # Coax Input Shield to Jumper NET 'GROUND' JMP7-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH7_In_Split_Dir' TRN7-1 TVS7-1 # Input Sec to ESD Diode Dir NET 'CH7_In_Split_Cmp' TRN7-3 TVS7-2 # Input Sec to ESD Diode Cmp NET 'CH7_In_Split_Dir' TRN23-1 # Input Sec to Split Pri Dir NET 'CH7_In_Split_Cmp' TRN23-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN7-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH7_ADC_IN_Dir' TRN23-5 # Term and ADC In DIR NET 'CH7_ADC_IN_Dir' R743-1 # Term and ADC In DIR NET 'CH7_TERM_Dir' R743-2 # Terminator DIR NET 'CH7_TERM_Dir' C745-1 # Terminator DIR NET 'CH7_TERM_Dir' C746-2 # Terminator DIR NET 'GROUND' C745-2 C746-1 # Ground NET 'CH7_ADC_IN_Cmp' TRN23-3 # Term and ADC In CMP NET 'CH7_ADC_IN_Cmp' R744-1 # Term and ADC In CMP NET 'CH7_TERM_Cmp' R744-2 # Terminator CMP NET 'CH7_TERM_Cmp' C747-1 # Terminator CMP NET 'CH7_TERM_Cmp' C748-2 # Terminator CMP NET 'GROUND' C747-2 C748-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH7_Bias_Dir' TRN23-2 # Winding Low NET 'CH7_Bias_Dir' R742-2 # Winding Low to Res NET 'CH7_Bias_Dir' C743-2 # Winding Low to Cap NET 'CH7_Bias_Dir' C744-2 # Winding Low to Cap NET 'GROUND' R742-1 # Ground Res NET 'GROUND' C743-1 # Ground Cap NET 'GROUND' C744-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH7_Bias_Cmp' TRN23-4 # Winding Low NET 'CH7_Bias_Cmp' C741-1 # Winding Low to Cap NET 'CH7_Bias_Cmp' C742-1 # Winding Low to Cap NET 'CH7_Bias_Cmp' R741-1 # Winding Low to Res NET 'GROUND' C741-2 # Ground Cap NET 'GROUND' C742-2 # Ground Cap NET 'GROUND' R741-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #8/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH8_Input_Dir' TRN8-6 # Coax Input Center Conductor NET 'CH8_Input_Cmp' TRN8-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH8_Input_Cmp' JMP8-1 # Coax Input Shield to Jumper NET 'GROUND' JMP8-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH8_In_Split_Dir' TRN8-1 TVS8-1 # Input Sec to ESD Diode Dir NET 'CH8_In_Split_Cmp' TRN8-3 TVS8-2 # Input Sec to ESD Diode Cmp NET 'CH8_In_Split_Dir' TRN24-1 # Input Sec to Split Pri Dir NET 'CH8_In_Split_Cmp' TRN24-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN8-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH8_ADC_IN_Dir' TRN24-5 # Term and ADC In DIR NET 'CH8_ADC_IN_Dir' R753-1 # Term and ADC In DIR NET 'CH8_TERM_Dir' R753-2 # Terminator DIR NET 'CH8_TERM_Dir' C755-1 # Terminator DIR NET 'CH8_TERM_Dir' C756-2 # Terminator DIR NET 'GROUND' C755-2 C756-1 # Ground NET 'CH8_ADC_IN_Cmp' TRN24-3 # Term and ADC In CMP NET 'CH8_ADC_IN_Cmp' R754-1 # Term and ADC In CMP NET 'CH8_TERM_Cmp' R754-2 # Terminator CMP NET 'CH8_TERM_Cmp' C757-1 # Terminator CMP NET 'CH8_TERM_Cmp' C758-2 # Terminator CMP NET 'GROUND' C757-2 C758-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH8_Bias_Dir' TRN24-2 # Winding Low NET 'CH8_Bias_Dir' R752-2 # Winding Low to Res NET 'CH8_Bias_Dir' C753-2 # Winding Low to Cap NET 'CH8_Bias_Dir' C754-2 # Winding Low to Cap NET 'GROUND' R752-1 # Ground Res NET 'GROUND' C753-1 # Ground Cap NET 'GROUND' C754-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH8_Bias_Cmp' TRN24-4 # Winding Low NET 'CH8_Bias_Cmp' C751-1 # Winding Low to Cap NET 'CH8_Bias_Cmp' C752-1 # Winding Low to Cap NET 'CH8_Bias_Cmp' R751-1 # Winding Low to Res NET 'GROUND' C751-2 # Ground Cap NET 'GROUND' C752-2 # Ground Cap NET 'GROUND' R751-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #9/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH9_Input_Dir' TRN9-6 # Coax Input Center Conductor NET 'CH9_Input_Cmp' TRN9-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH9_Input_Cmp' JMP9-1 # Coax Input Shield to Jumper NET 'GROUND' JMP9-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH9_In_Split_Dir' TRN9-1 TVS9-1 # Input Sec to ESD Diode Dir NET 'CH9_In_Split_Cmp' TRN9-3 TVS9-2 # Input Sec to ESD Diode Cmp NET 'CH9_In_Split_Dir' TRN25-1 # Input Sec to Split Pri Dir NET 'CH9_In_Split_Cmp' TRN25-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN9-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH9_ADC_IN_Dir' TRN25-5 # Term and ADC In DIR NET 'CH9_ADC_IN_Dir' R763-1 # Term and ADC In DIR NET 'CH9_TERM_Dir' R763-2 # Terminator DIR NET 'CH9_TERM_Dir' C765-1 # Terminator DIR NET 'CH9_TERM_Dir' C766-2 # Terminator DIR NET 'GROUND' C765-2 C766-1 # Ground NET 'CH9_ADC_IN_Cmp' TRN25-3 # Term and ADC In CMP NET 'CH9_ADC_IN_Cmp' R764-1 # Term and ADC In CMP NET 'CH9_TERM_Cmp' R764-2 # Terminator CMP NET 'CH9_TERM_Cmp' C767-1 # Terminator CMP NET 'CH9_TERM_Cmp' C768-2 # Terminator CMP NET 'GROUND' C767-2 C768-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH9_Bias_Dir' TRN25-2 # Winding Low NET 'CH9_Bias_Dir' R762-2 # Winding Low to Res NET 'CH9_Bias_Dir' C763-2 # Winding Low to Cap NET 'CH9_Bias_Dir' C764-2 # Winding Low to Cap NET 'GROUND' R762-1 # Ground Res NET 'GROUND' C763-1 # Ground Cap NET 'GROUND' C764-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH9_Bias_Cmp' TRN25-4 # Winding Low NET 'CH9_Bias_Cmp' C761-1 # Winding Low to Cap NET 'CH9_Bias_Cmp' C762-1 # Winding Low to Cap NET 'CH9_Bias_Cmp' R761-1 # Winding Low to Res NET 'GROUND' C761-2 # Ground Cap NET 'GROUND' C762-2 # Ground Cap NET 'GROUND' R761-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #10/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH10_Input_Dir' TRN10-6 # Coax Input Center Conductor NET 'CH10_Input_Cmp' TRN10-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH10_Input_Cmp' JMP10-1 # Coax Input Shield to Jumper NET 'GROUND' JMP10-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH10_In_Split_Dir' TRN10-1 TVS10-1 # Input Sec to ESD Diode Dir NET 'CH10_In_Split_Cmp' TRN10-3 TVS10-2 # Input Sec to ESD Diode Cmp NET 'CH10_In_Split_Dir' TRN26-1 # Input Sec to Split Pri Dir NET 'CH10_In_Split_Cmp' TRN26-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN10-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH10_ADC_IN_Dir' TRN26-5 # Term and ADC In DIR NET 'CH10_ADC_IN_Dir' R773-1 # Term and ADC In DIR NET 'CH10_TERM_Dir' R773-2 # Terminator DIR NET 'CH10_TERM_Dir' C775-1 # Terminator DIR NET 'CH10_TERM_Dir' C776-2 # Terminator DIR NET 'GROUND' C775-2 C776-1 # Ground NET 'CH10_ADC_IN_Cmp' TRN26-3 # Term and ADC In CMP NET 'CH10_ADC_IN_Cmp' R774-1 # Term and ADC In CMP NET 'CH10_TERM_Cmp' R774-2 # Terminator CMP NET 'CH10_TERM_Cmp' C777-1 # Terminator CMP NET 'CH10_TERM_Cmp' C778-2 # Terminator CMP NET 'GROUND' C777-2 C778-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH10_Bias_Dir' TRN26-2 # Winding Low NET 'CH10_Bias_Dir' R772-2 # Winding Low to Res NET 'CH10_Bias_Dir' C773-2 # Winding Low to Cap NET 'CH10_Bias_Dir' C774-2 # Winding Low to Cap NET 'GROUND' R772-1 # Ground Res NET 'GROUND' C773-1 # Ground Cap NET 'GROUND' C774-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH10_Bias_Cmp' TRN26-4 # Winding Low NET 'CH10_Bias_Cmp' C771-1 # Winding Low to Cap NET 'CH10_Bias_Cmp' C772-1 # Winding Low to Cap NET 'CH10_Bias_Cmp' R771-1 # Winding Low to Res NET 'GROUND' C771-2 # Ground Cap NET 'GROUND' C772-2 # Ground Cap NET 'GROUND' R771-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #11/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH11_Input_Dir' TRN11-6 # Coax Input Center Conductor NET 'CH11_Input_Cmp' TRN11-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH11_Input_Cmp' JMP11-1 # Coax Input Shield to Jumper NET 'GROUND' JMP11-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH11_In_Split_Dir' TRN11-1 TVS11-1 # Input Sec to ESD Diode Dir NET 'CH11_In_Split_Cmp' TRN11-3 TVS11-2 # Input Sec to ESD Diode Cmp NET 'CH11_In_Split_Dir' TRN27-1 # Input Sec to Split Pri Dir NET 'CH11_In_Split_Cmp' TRN27-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN11-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH11_ADC_IN_Dir' TRN27-5 # Term and ADC In DIR NET 'CH11_ADC_IN_Dir' R783-1 # Term and ADC In DIR NET 'CH11_TERM_Dir' R783-2 # Terminator DIR NET 'CH11_TERM_Dir' C785-1 # Terminator DIR NET 'CH11_TERM_Dir' C786-2 # Terminator DIR NET 'GROUND' C785-2 C786-1 # Ground NET 'CH11_ADC_IN_Cmp' TRN27-3 # Term and ADC In CMP NET 'CH11_ADC_IN_Cmp' R784-1 # Term and ADC In CMP NET 'CH11_TERM_Cmp' R784-2 # Terminator CMP NET 'CH11_TERM_Cmp' C787-1 # Terminator CMP NET 'CH11_TERM_Cmp' C788-2 # Terminator CMP NET 'GROUND' C787-2 C788-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH11_Bias_Dir' TRN27-2 # Winding Low NET 'CH11_Bias_Dir' R782-2 # Winding Low to Res NET 'CH11_Bias_Dir' C783-2 # Winding Low to Cap NET 'CH11_Bias_Dir' C784-2 # Winding Low to Cap NET 'GROUND' R782-1 # Ground Res NET 'GROUND' C783-1 # Ground Cap NET 'GROUND' C784-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH11_Bias_Cmp' TRN27-4 # Winding Low NET 'CH11_Bias_Cmp' C781-1 # Winding Low to Cap NET 'CH11_Bias_Cmp' C782-1 # Winding Low to Cap NET 'CH11_Bias_Cmp' R781-1 # Winding Low to Res NET 'GROUND' C781-2 # Ground Cap NET 'GROUND' C782-2 # Ground Cap NET 'GROUND' R781-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #12/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH12_Input_Dir' TRN12-6 # Coax Input Center Conductor NET 'CH12_Input_Cmp' TRN12-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH12_Input_Cmp' JMP12-1 # Coax Input Shield to Jumper NET 'GROUND' JMP12-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH12_In_Split_Dir' TRN12-1 TVS12-1 # Input Sec to ESD Diode Dir NET 'CH12_In_Split_Cmp' TRN12-3 TVS12-2 # Input Sec to ESD Diode Cmp NET 'CH12_In_Split_Dir' TRN28-1 # Input Sec to Split Pri Dir NET 'CH12_In_Split_Cmp' TRN28-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN12-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH12_ADC_IN_Dir' TRN28-5 # Term and ADC In DIR NET 'CH12_ADC_IN_Dir' R793-1 # Term and ADC In DIR NET 'CH12_TERM_Dir' R793-2 # Terminator DIR NET 'CH12_TERM_Dir' C795-1 # Terminator DIR NET 'CH12_TERM_Dir' C796-2 # Terminator DIR NET 'GROUND' C795-2 C796-1 # Ground NET 'CH12_ADC_IN_Cmp' TRN28-3 # Term and ADC In CMP NET 'CH12_ADC_IN_Cmp' R794-1 # Term and ADC In CMP NET 'CH12_TERM_Cmp' R794-2 # Terminator CMP NET 'CH12_TERM_Cmp' C797-1 # Terminator CMP NET 'CH12_TERM_Cmp' C798-2 # Terminator CMP NET 'GROUND' C797-2 C798-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH12_Bias_Dir' TRN28-2 # Winding Low NET 'CH12_Bias_Dir' R792-2 # Winding Low to Res NET 'CH12_Bias_Dir' C793-2 # Winding Low to Cap NET 'CH12_Bias_Dir' C794-2 # Winding Low to Cap NET 'GROUND' R792-1 # Ground Res NET 'GROUND' C793-1 # Ground Cap NET 'GROUND' C794-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH12_Bias_Cmp' TRN28-4 # Winding Low NET 'CH12_Bias_Cmp' C791-1 # Winding Low to Cap NET 'CH12_Bias_Cmp' C792-1 # Winding Low to Cap NET 'CH12_Bias_Cmp' R791-1 # Winding Low to Res NET 'GROUND' C791-2 # Ground Cap NET 'GROUND' C792-2 # Ground Cap NET 'GROUND' R791-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #13/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH13_Input_Dir' TRN13-6 # Coax Input Center Conductor NET 'CH13_Input_Cmp' TRN13-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH13_Input_Cmp' JMP13-1 # Coax Input Shield to Jumper NET 'GROUND' JMP13-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH13_In_Split_Dir' TRN13-1 TVS13-1 # Input Sec to ESD Diode Dir NET 'CH13_In_Split_Cmp' TRN13-3 TVS13-2 # Input Sec to ESD Diode Cmp NET 'CH13_In_Split_Dir' TRN29-1 # Input Sec to Split Pri Dir NET 'CH13_In_Split_Cmp' TRN29-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN13-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH13_ADC_IN_Dir' TRN29-5 # Term and ADC In DIR NET 'CH13_ADC_IN_Dir' R803-1 # Term and ADC In DIR NET 'CH13_TERM_Dir' R803-2 # Terminator DIR NET 'CH13_TERM_Dir' C805-1 # Terminator DIR NET 'CH13_TERM_Dir' C806-2 # Terminator DIR NET 'GROUND' C805-2 C806-1 # Ground NET 'CH13_ADC_IN_Cmp' TRN29-3 # Term and ADC In CMP NET 'CH13_ADC_IN_Cmp' R804-1 # Term and ADC In CMP NET 'CH13_TERM_Cmp' R804-2 # Terminator CMP NET 'CH13_TERM_Cmp' C807-1 # Terminator CMP NET 'CH13_TERM_Cmp' C808-2 # Terminator CMP NET 'GROUND' C807-2 C808-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH13_Bias_Dir' TRN29-2 # Winding Low NET 'CH13_Bias_Dir' R802-2 # Winding Low to Res NET 'CH13_Bias_Dir' C803-2 # Winding Low to Cap NET 'CH13_Bias_Dir' C804-2 # Winding Low to Cap NET 'GROUND' R802-1 # Ground Res NET 'GROUND' C803-1 # Ground Cap NET 'GROUND' C804-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH13_Bias_Cmp' TRN29-4 # Winding Low NET 'CH13_Bias_Cmp' C801-1 # Winding Low to Cap NET 'CH13_Bias_Cmp' C802-1 # Winding Low to Cap NET 'CH13_Bias_Cmp' R801-1 # Winding Low to Res NET 'GROUND' C801-2 # Ground Cap NET 'GROUND' C802-2 # Ground Cap NET 'GROUND' R801-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #14/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH14_Input_Dir' TRN14-6 # Coax Input Center Conductor NET 'CH14_Input_Cmp' TRN14-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH14_Input_Cmp' JMP14-1 # Coax Input Shield to Jumper NET 'GROUND' JMP14-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH14_In_Split_Dir' TRN14-1 TVS14-1 # Input Sec to ESD Diode Dir NET 'CH14_In_Split_Cmp' TRN14-3 TVS14-2 # Input Sec to ESD Diode Cmp NET 'CH14_In_Split_Dir' TRN30-1 # Input Sec to Split Pri Dir NET 'CH14_In_Split_Cmp' TRN30-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN14-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH14_ADC_IN_Dir' TRN30-5 # Term and ADC In DIR NET 'CH14_ADC_IN_Dir' R813-1 # Term and ADC In DIR NET 'CH14_TERM_Dir' R813-2 # Terminator DIR NET 'CH14_TERM_Dir' C815-1 # Terminator DIR NET 'CH14_TERM_Dir' C816-2 # Terminator DIR NET 'GROUND' C815-2 C816-1 # Ground NET 'CH14_ADC_IN_Cmp' TRN30-3 # Term and ADC In CMP NET 'CH14_ADC_IN_Cmp' R814-1 # Term and ADC In CMP NET 'CH14_TERM_Cmp' R814-2 # Terminator CMP NET 'CH14_TERM_Cmp' C817-1 # Terminator CMP NET 'CH14_TERM_Cmp' C818-2 # Terminator CMP NET 'GROUND' C817-2 C818-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH14_Bias_Dir' TRN30-2 # Winding Low NET 'CH14_Bias_Dir' R812-2 # Winding Low to Res NET 'CH14_Bias_Dir' C813-2 # Winding Low to Cap NET 'CH14_Bias_Dir' C814-2 # Winding Low to Cap NET 'GROUND' R812-1 # Ground Res NET 'GROUND' C813-1 # Ground Cap NET 'GROUND' C814-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH14_Bias_Cmp' TRN30-4 # Winding Low NET 'CH14_Bias_Cmp' C811-1 # Winding Low to Cap NET 'CH14_Bias_Cmp' C812-1 # Winding Low to Cap NET 'CH14_Bias_Cmp' R811-1 # Winding Low to Res NET 'GROUND' C811-2 # Ground Cap NET 'GROUND' C812-2 # Ground Cap NET 'GROUND' R811-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #15/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH15_Input_Dir' TRN15-6 # Coax Input Center Conductor NET 'CH15_Input_Cmp' TRN15-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH15_Input_Cmp' JMP15-1 # Coax Input Shield to Jumper NET 'GROUND' JMP15-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH15_In_Split_Dir' TRN15-1 TVS15-1 # Input Sec to ESD Diode Dir NET 'CH15_In_Split_Cmp' TRN15-3 TVS15-2 # Input Sec to ESD Diode Cmp NET 'CH15_In_Split_Dir' TRN31-1 # Input Sec to Split Pri Dir NET 'CH15_In_Split_Cmp' TRN31-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN15-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH15_ADC_IN_Dir' TRN31-5 # Term and ADC In DIR NET 'CH15_ADC_IN_Dir' R823-1 # Term and ADC In DIR NET 'CH15_TERM_Dir' R823-2 # Terminator DIR NET 'CH15_TERM_Dir' C825-1 # Terminator DIR NET 'CH15_TERM_Dir' C826-2 # Terminator DIR NET 'GROUND' C825-2 C826-1 # Ground NET 'CH15_ADC_IN_Cmp' TRN31-3 # Term and ADC In CMP NET 'CH15_ADC_IN_Cmp' R824-1 # Term and ADC In CMP NET 'CH15_TERM_Cmp' R824-2 # Terminator CMP NET 'CH15_TERM_Cmp' C827-1 # Terminator CMP NET 'CH15_TERM_Cmp' C828-2 # Terminator CMP NET 'GROUND' C827-2 C828-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH15_Bias_Dir' TRN31-2 # Winding Low NET 'CH15_Bias_Dir' R822-2 # Winding Low to Res NET 'CH15_Bias_Dir' C823-2 # Winding Low to Cap NET 'CH15_Bias_Dir' C824-2 # Winding Low to Cap NET 'GROUND' R822-1 # Ground Res NET 'GROUND' C823-1 # Ground Cap NET 'GROUND' C824-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH15_Bias_Cmp' TRN31-4 # Winding Low NET 'CH15_Bias_Cmp' C821-1 # Winding Low to Cap NET 'CH15_Bias_Cmp' C822-1 # Winding Low to Cap NET 'CH15_Bias_Cmp' R821-1 # Winding Low to Res NET 'GROUND' C821-2 # Ground Cap NET 'GROUND' C822-2 # Ground Cap NET 'GROUND' R821-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # MIGT>---------------------------------------------- # MIGT> V1.0 -- Sun Jan 12 14:40:39 2020 # MIGT> begin substituting from -- instance #16/16 # MIGT>---------------------------------------------- # # Disco-Kraken Module # # PMT Analog Input Net List Template File # --------------------========--========-------- # # # Original Rev. 21-Feb-2023 # Most Recent Rev. 14-Nov-2023 # # # This file includes the Transformer and DC Bias components # for the PMT Signal Analog Input Components in a Channel Pair. # # Net List # # Input Connector to INPUT Transformer Primary NET 'CH16_Input_Dir' TRN16-6 # Coax Input Center Conductor NET 'CH16_Input_Cmp' TRN16-4 # Coax Input Shield # Zero Ohm Jumper to connect the Coax Input Shield to Ground NET 'CH16_Input_Cmp' JMP16-1 # Coax Input Shield to Jumper NET 'GROUND' JMP16-2 # Ground # INPUT Transformer Secondary to ESD Diode then to SPLIT Transformer Primary NET 'CH16_In_Split_Dir' TRN16-1 TVS16-1 # Input Sec to ESD Diode Dir NET 'CH16_In_Split_Cmp' TRN16-3 TVS16-2 # Input Sec to ESD Diode Cmp NET 'CH16_In_Split_Dir' TRN32-1 # Input Sec to Split Pri Dir NET 'CH16_In_Split_Cmp' TRN32-6 # Input Sec to Split Pri Cmp NET 'GROUND' TRN16-2 # Ground Input Sec Center Tap # SPLIT Transformer Secondary to Terminator and to ADC Input NET 'CH16_ADC_IN_Dir' TRN32-5 # Term and ADC In DIR NET 'CH16_ADC_IN_Dir' R833-1 # Term and ADC In DIR NET 'CH16_TERM_Dir' R833-2 # Terminator DIR NET 'CH16_TERM_Dir' C835-1 # Terminator DIR NET 'CH16_TERM_Dir' C836-2 # Terminator DIR NET 'GROUND' C835-2 C836-1 # Ground NET 'CH16_ADC_IN_Cmp' TRN32-3 # Term and ADC In CMP NET 'CH16_ADC_IN_Cmp' R834-1 # Term and ADC In CMP NET 'CH16_TERM_Cmp' R834-2 # Terminator CMP NET 'CH16_TERM_Cmp' C837-1 # Terminator CMP NET 'CH16_TERM_Cmp' C838-2 # Terminator CMP NET 'GROUND' C837-2 C838-1 # Ground # SPLIT Transformer Secondary DIR Winding Bias and AC Ground NET 'CH16_Bias_Dir' TRN32-2 # Winding Low NET 'CH16_Bias_Dir' R832-2 # Winding Low to Res NET 'CH16_Bias_Dir' C833-2 # Winding Low to Cap NET 'CH16_Bias_Dir' C834-2 # Winding Low to Cap NET 'GROUND' R832-1 # Ground Res NET 'GROUND' C833-1 # Ground Cap NET 'GROUND' C834-1 # Ground Cap # SPLIT Transformer Secondary CMP Winding Bias and AC Ground NET 'CH16_Bias_Cmp' TRN32-4 # Winding Low NET 'CH16_Bias_Cmp' C831-1 # Winding Low to Cap NET 'CH16_Bias_Cmp' C832-1 # Winding Low to Cap NET 'CH16_Bias_Cmp' R831-1 # Winding Low to Res NET 'GROUND' C831-2 # Ground Cap NET 'GROUND' C832-2 # Ground Cap NET 'GROUND' R831-2 # Ground Cap and Res # MIGT>---------------------------------------------- # MIGT> done substituting from # # PMT ADC Net List # ---------------------- # # # Original Rev. 19-Feb-2023 # Current Rev. 6-Dec-2023 # # # This Net List file assigns net names to all 100 # of the AD9083 ADC pins. # # # Analog Signal Input Pins # -------------------------- # NET 'CH1_ADC_IN_DIR' U601-A5 NET 'CH1_ADC_IN_CMP' U601-B5 NET 'CH2_ADC_IN_DIR' U601-A6 NET 'CH2_ADC_IN_CMP' U601-B6 NET 'CH3_ADC_IN_DIR' U601-A7 NET 'CH3_ADC_IN_CMP' U601-B7 NET 'CH4_ADC_IN_DIR' U601-A8 NET 'CH4_ADC_IN_CMP' U601-B8 NET 'CH5_ADC_IN_DIR' U601-A9 NET 'CH5_ADC_IN_CMP' U601-B9 NET 'CH6_ADC_IN_DIR' U601-C10 NET 'CH6_ADC_IN_CMP' U601-C9 NET 'CH7_ADC_IN_DIR' U601-D10 NET 'CH7_ADC_IN_CMP' U601-D9 NET 'CH8_ADC_IN_DIR' U601-E10 NET 'CH8_ADC_IN_CMP' U601-E9 NET 'CH9_ADC_IN_DIR' U601-F10 NET 'CH9_ADC_IN_CMP' U601-F9 NET 'CH10_ADC_IN_DIR' U601-G10 NET 'CH10_ADC_IN_CMP' U601-G9 NET 'CH11_ADC_IN_DIR' U601-H10 NET 'CH11_ADC_IN_CMP' U601-H9 NET 'CH12_ADC_IN_DIR' U601-K9 NET 'CH12_ADC_IN_CMP' U601-J9 NET 'CH13_ADC_IN_DIR' U601-K8 NET 'CH13_ADC_IN_CMP' U601-J8 NET 'CH14_ADC_IN_DIR' U601-K7 NET 'CH14_ADC_IN_CMP' U601-J7 NET 'CH15_ADC_IN_DIR' U601-K6 NET 'CH15_ADC_IN_CMP' U601-J6 NET 'CH16_ADC_IN_DIR' U601-K5 NET 'CH16_ADC_IN_CMP' U601-J5 # # Power Supply Pins # ------------------- # # Analog 1V0 NET 'ADC_ANALOG_1V0' U601-D6 U601-E6 U601-E7 NET 'ADC_ANALOG_1V0' U601-F6 U601-F7 U601-G6 # Analog Clock 1V0 NET 'ADC_ANALOG_1V0' U601-F5 # Analog PLL 1V0 NET 'ADC_ANALOG_1V0' U601-J4 # Analog 1V8 NET 'ADC_ANALOG_1V8' U601-C8 U601-D8 U601-G8 NET 'ADC_ANALOG_1V8' U601-H6 U601-H8 # Digital 1V0 NET 'ADC_Digital_1V0' U601-D3 U601-E3 U601-F3 U601-G3 # Digital Driver 1V0 NET 'ADC_Digital_1V0' U601-B3 U601-C3 U601-H3 # Digital Driver 1V8 NET 'ADC_Digital_1V8' U601-B1 # Digital SPI and I/O 1V8 NET 'ADC_Digital_1V8' U601-B2 # # GROUND Pins # ------------- # # Analog GROUND Pins 9x NET 'GROUND' U601-C6 U601-C7 U601-D7 U601-E8 U601-F8 NET 'GROUND' U601-G7 U601-H5 U601-H7 U601-K10 # Analog AVDD GROUND Reference Pins 2x NET 'GROUND' U601-E5 U601-K4 # Digital GROUND Pins 4x NET 'GROUND' U601-D4 U601-E4 U601-F4 U601-G4 # Digital Driver GROUND Pins 4x NET 'GROUND' U601-A1 U601-C1 U601-C2 U601-H2 # # The four JESD204B ADC Serial Data Links # NET 'ADC_SEROUT0_DIR' U601-D2 # FPGA XCVR_1_RX0_DIR NET 'ADC_SEROUT0_CMP' U601-D1 # FPGA XCVR_1_RX0_CMP NET 'ADC_SEROUT1_DIR' U601-E2 # FPGA XCVR_1_RX1_DIR NET 'ADC_SEROUT1_CMP' U601-E1 # FPGA XCVR_1_RX1_CMP NET 'ADC_SEROUT2_DIR' U601-F2 # FPGA XCVR_1_RX2_DIR NET 'ADC_SEROUT2_CMP' U601-F1 # FPGA XCVR_1_RX2_CMP NET 'ADC_SEROUT3_DIR' U601-G2 # FPGA XCVR_1_RX3_DIR NET 'ADC_SEROUT3_CMP' U601-G1 # FPGA XCVR_1_RX3_CMP # # Four Clock and Timing Signal Inputs # NET 'PMT_ADC_CLOCK_DIR' U601-K3 # ADC Converter Clock DIR NET 'PMT_ADC_CLOCK_CMP' U601-J3 # ADC Converter Clock CMP ##NET 'PMT_ADC_SYS_REF_DIR' U601-K2 # ADC System Reference DIR NET 'TG_Output_0B_Dir' U601-K2 # Connect System Reference DIR to Time Generator ##NET 'PMT_ADC_SYS_REF_CMP' U601-J2 # ADC System Reference CMP NET 'TG_Output_0B_Cmp' U601-J2 # Connect System Reference CMP to Time Generator NET 'PMT_ADC_SYNC_ENB_B_DIR' U601-A2 # ADC JESD204B Sync Enb B DIR NET 'PMT_ADC_SYNC_ENB_B_CMP' U601-A3 # ADC JESD204B Sync Enb B CMP NET 'PMT_ADC_Trigger_DIR' U601-H1 # ADC Trigger Dir Input Float if not used NET 'PMT_ADC_Trigger_CMP' U601-J1 # ADC Trigger Cmp Input Float if not used # # Five ADC Digital Controls mostly inputs and one I/O # ##NET 'ADC_POW_DWN_STBY' U601-C5 # ADC Power Down - Standby Active HI NET 'GROUND' U601-C5 # Ground the ADC_POW_DWN_STBY signal NET 'PMT_ADC_RESET_B' U601-D5 # ADC Reset Active LOW NET 'PMT_ADC_CHIP_SELECT_B' U601-A4 # ADC SPI Chip Select Active LOW NET 'PMT_ADC_SPI_CLOCK' U601-B4 # ADC SPI Clock NET 'PMT_ADC_SPI_DATA_IO' U601-C4 # ADC SPI Data I/O # # Six ADC Static Control pins # NET 'PMT_ADC_Temp_Diode' U601-B10 # ADC Temperature Diode NET 'ADC_CURRENT_REFERENCE' U601-J10 # ADC Current Reference Resistor NET 'ADC_PLL_REG_BYPASS' U601-H4 # ADC PLL VCO Voltage Regulator Bypass Cap NET 'ADC_PLL_COARSE_FILTER' U601-G5 # ADC PLL Coarse Filter Capacitor NET 'NO_CONN_U601_PIN_A10' U601-A10 # ADC Do NOT Connect Pin NET 'NO_CONN_U601_PIN_K1' U601-K1 # ADC Do NOT Connect Pin # # Didsco-Kraken PMT Input Connector3 Nets File # -----------------====================------------- # # # Original Rev. 14-Feb-2023 # Most Recent Rev. 7-Aug-2023 # # PMT Input Connectors Pin Nets # # Now using Harwin M80-MH313M5-08 connectors. # # # PMT Signal Input Connector J2 PMT Channels 1:8 # NET 'CH1_Input_Dir' J2-1 # Coax Input Center Conductor NET 'CH1_Input_Cmp' J2-9 J2-10 # Coax Input Shield NET 'CH2_Input_Dir' J2-2 # Coax Input Center Conductor NET 'CH2_Input_Cmp' J2-11 J2-12 # Coax Input Shield NET 'CH3_Input_Dir' J2-3 # Coax Input Center Conductor NET 'CH3_Input_Cmp' J2-13 J2-14 # Coax Input Shield NET 'CH4_Input_Dir' J2-4 # Coax Input Center Conductor NET 'CH4_Input_Cmp' J2-15 J2-16 # Coax Input Shield NET 'CH5_Input_Dir' J2-5 # Coax Input Center Conductor NET 'CH5_Input_Cmp' J2-17 J2-18 # Coax Input Shield NET 'CH6_Input_Dir' J2-6 # Coax Input Center Conductor NET 'CH6_Input_Cmp' J2-19 J2-20 # Coax Input Shield NET 'CH7_Input_Dir' J2-7 # Coax Input Center Conductor NET 'CH7_Input_Cmp' J2-21 J2-22 # Coax Input Shield NET 'CH8_Input_Dir' J2-8 # Coax Input Center Conductor NET 'CH8_Input_Cmp' J2-23 J2-24 # Coax Input Shield # # PMT Signal Input Connector J3 PMT Channels 9:16 # NET 'CH9_Input_Dir' J3-1 # Coax Input Center Conductor NET 'CH9_Input_Cmp' J3-9 J3-10 # Coax Input Shield NET 'CH10_Input_Dir' J3-2 # Coax Input Center Conductor NET 'CH10_Input_Cmp' J3-11 J3-12 # Coax Input Shield NET 'CH11_Input_Dir' J3-3 # Coax Input Center Conductor NET 'CH11_Input_Cmp' J3-13 J3-14 # Coax Input Shield NET 'CH12_Input_Dir' J3-4 # Coax Input Center Conductor NET 'CH12_Input_Cmp' J3-15 J3-16 # Coax Input Shield NET 'CH13_Input_Dir' J3-5 # Coax Input Center Conductor NET 'CH13_Input_Cmp' J3-17 J3-18 # Coax Input Shield NET 'CH14_Input_Dir' J3-6 # Coax Input Center Conductor NET 'CH14_Input_Cmp' J3-19 J3-20 # Coax Input Shield NET 'CH15_Input_Dir' J3-7 # Coax Input Center Conductor NET 'CH15_Input_Cmp' J3-21 J3-22 # Coax Input Shield NET 'CH16_Input_Dir' J3-8 # Coax Input Center Conductor NET 'CH16_Input_Cmp' J3-23 J3-24 # Coax Input Shield # # Finally GROUND the Mounting Screws on both J2 and J3 # NET 'GROUND' J2-25 J2-26 # J2 Mounting Screws NET 'GROUND' J3-25 J3-26 # J3 Mounting Screws # # PMT ADC Power Filter & Bypass Capacitor Net List # ---------------------------------------------------- # # # Original Rev. 22-Feb-2023 # Current Rev. 16-Nov-2023 # # # This Net List file covers the ADC Power Filters # and the ADC Bypass Capacitors. # # # ADC_ANALOG_1V0 Power Filter & Bypass Caps aka AVDD # NET 'Bulk_1V00' L601-1 NET 'ADC_ANALOG_1V0' L601-2 NET 'ADC_ANALOG_1V0' C601-1 C602-1 C603-1 C604-1 C605-1 NET 'GROUND' C601-2 C602-2 C603-2 C604-2 C605-2 NET 'ADC_ANALOG_1V0' C606-1 C607-1 C608-1 C609-1 C610-1 NET 'GROUND' C606-2 C607-2 C608-2 C609-2 C610-2 NET 'ADC_ANALOG_1V0' C611-1 C612-1 C613-1 C614-1 C615-1 NET 'GROUND' C611-2 C612-2 C613-2 C614-2 C615-2 NET 'ADC_ANALOG_1V0' C616-1 C617-1 NET 'GROUND' C616-2 C617-2 # ADC_ANALOG_1V8 Power Filter & Bypass Caps aka AVDD1P8V NET 'BULK_1V8' L602-2 NET 'ADC_ANALOG_1V8' L602-1 NET 'ADC_ANALOG_1V8' C618-1 C619-1 C620-1 C621-1 C622-1 NET 'GROUND' C618-2 C619-2 C620-2 C621-2 C622-2 NET 'ADC_ANALOG_1V8' C623-1 C624-1 C625-1 C626-1 C627-1 NET 'GROUND' C623-2 C624-2 C625-2 C626-2 C627-2 NET 'ADC_ANALOG_1V8' C628-1 C629-1 C630-1 C631-1 C632-1 NET 'GROUND' C628-2 C629-2 C630-2 C631-2 C632-2 NET 'ADC_ANALOG_1V8' C633-1 NET 'GROUND' C633-2 # ADC_DIGITAL_1V0 Power Filter & Bypass Caps aka DVDD NET 'Bulk_1V00' L603-1 NET 'ADC_DIGITAL_1V0' L603-2 NET 'ADC_DIGITAL_1V0' C634-1 C635-1 C636-1 C637-1 C638-1 NET 'GROUND' C634-2 C635-2 C636-2 C637-2 C638-2 NET 'ADC_DIGITAL_1V0' C639-1 C640-1 C641-1 C642-1 C643-1 NET 'GROUND' C639-2 C640-2 C641-2 C642-2 C643-2 NET 'ADC_DIGITAL_1V0' C644-1 C645-1 C646-1 C647-1 C648-1 NET 'GROUND' C644-2 C645-2 C646-2 C647-2 C648-2 NET 'ADC_DIGITAL_1V0' C649-1 C650-1 C651-1 C652-1 C653-1 NET 'GROUND' C649-2 C650-2 C651-2 C652-2 C653-2 NET 'ADC_DIGITAL_1V0' C654-1 C655-1 NET 'GROUND' C654-2 C655-2 # ADC_DIGITAL_1V8 Power Filter & Bypass Caps aka DVDD1P8V NET 'BULK_1V8' L604-2 NET 'ADC_DIGITAL_1V8' L604-1 NET 'ADC_DIGITAL_1V8' C658-1 C659-1 C660-1 C661-1 C662-1 NET 'GROUND' C658-2 C659-2 C660-2 C661-2 C662-2 NET 'ADC_DIGITAL_1V8' C663-1 C664-1 C665-1 C666-1 C667-1 NET 'GROUND' C663-2 C664-2 C665-2 C666-2 C667-2 NET 'ADC_DIGITAL_1V8' C668-1 NET 'GROUND' C668-2 # # PMT ADC Sundry Net List # --------------------------- # # # Original Rev. 23-Feb-2023 # Current Rev. 6-Dec-2023 # # PMT ADC Sundry Nets # # # PMT ADC Temperature Diode and Power Down / Standby # --------------------------------------------------------- # NET 'PMT_ADC_Temp_Diode' TP601-1 # Temp Diode Signal to Single SMD Pad # The HI Active PMT ADC Power_Down/Standby pin # is Grounded in the Net List file for the ADC itself. # # SPI Bus Connection between FPGA/CPU and PMT ADC 3-Wire SPI # ----------------------------------------------------------------- # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are 1V8 signals: PMT ADC SPI Bus # -------------------------------------------------- # # NET 'PMT_ADC_CHIP_SELECT_B' # ADC SPI Chip Select Active LOW # NET 'PMT_ADC_SPI_CLOCK' # ADC SPI Clock # NET 'PMT_ADC_SPI_DATA_IO' # ADC SPI Data I/O # # # CLOCK Type Signals that are sent to the PMT ADC from Timing Generator & FPGA # ----------------------------------------------------------------------------------- # # # Review of the Clock type signals that are inputs to the AD9083 # # See pages: 10, 15, 25, 26 of the AD9083 Datasheet # # Clock is 100 Ohm internally terminated, Clamp is 1 diode above AVDD, # ------- the input has a weak self DC Biased of 0.5 Volts, # the input should be AC coupled, # the Input Amplitude should be 800 to 1800 mV pk-pk # # System_Reference is 100 Ohm internally terminated, Clamp is 1 diode above AVDD, # ---------------- the input has a weak self DC Biased of 0.5 Volts, # the Input Common Mode should be 0.5 V # the Input Amplitude should be 700 to 1100 mV pk-pk # AD says this input is LVDS compatable # # Trigger is 100 Ohm internally terminated, Clamp is 1 diode above AVDD, # ------- the input has a weak self DC Biased of 0.5 Volts, # the Input Common Mode should be 0.5 V # the Input Amplitude should be 700 to 1100 mV pk-pk # AD says this input is LVDS compatable # # Sync_Enb_B is 100K Ohm internally terminated, Clamp is 2 diodes above DVDD1P8, # ---------- the Input Common Mode should be 0.45 V # in its the Input Amplitude should be 700 to 1900 mV pk-pk # Diff Mode AD says this input is LVDS compatable # # # Concerns: AD calls the System_Reference and Trigger inputs "LVDS" # but they are not normal LVDS because their Common Mode is # too Low. Concern - are the 3V3 LVDS outputs from the FPGA/CPU # really true 3 mA Current Mode outputs or are they some # LVDS Like volltage mode thing that will over drive these # AD9083 inputs ? E.G. should I use series resistors ? # # Sync_Enb_B needs an external 100 Ohm terminator - R602. # # The PMT ADC CLOCK signal is AC coupled and # comes from the Timing Generator Output 0-A NET 'PMT_ADC_CLOCK_DIR' C941-2 # ADC Converter Clock DIR Timing Generator Output NET 'PMT_ADC_CLOCK_CMP' C942-2 # ADC Converter Clock CMP 0-A AC Cooupling Caps # The PMT ADC SYSTEM REFERENCE signal is DC coupled # and comes from the Timing Generator Output 0-B # # This connection is made in the Net List file for the ADC itself. # # 'ADC System Reference DIR' U601-K2 # DC Coupled signal from the # 'ADC System Reference CMP' U601-J2 # Timing Generator Output 0-B # The PMT ADC SYNC_Enb_B signal is DC coupled # and comes from a LVDS output on the FPGA/CPU. # # Note that SYNC_Enb_B needs an external 100 Ohm Terminator # when this input is used in its LVDS mode. This 100 Ohm # terminator, R602, is connected here. # # 'PMT_ADC_SYNC_ENB_B_DIR' U601-A2 # ADC JESD204B Sync Enb B DIR # 'PMT_ADC_SYNC_ENB_B_CMP' U601-A3 # ADC JESD204B Sync Enb B CMP # NET 'PMT_ADC_SYNC_ENB_B_DIR' R602-1 # Terminator on Sync_Enb_B NET 'PMT_ADC_SYNC_ENB_B_CMP' R602-2 # Terminator on Sync_Enb_B # The PMT ADC TRIGGER signal is DC coupled and # comes from a LVDS output on the FPGA/CPU. # # 'PMT_ADC_Trigger_DIR' U601-H1 # ADC Trigger Dir Input # 'PMT_ADC_Trigger_CMP' U601-J1 # ADC Trigger Cmp Input # # Clock type Signals from the FPGA/CPU to the PMT ADC # ----------------------------------------------------------- # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are LVDS signals: PMT ADC Clock Type Signals # -------------------------------------------------------------- # # NET 'PMT_ADC_SYNC_ENB_B_DIR' # ADC JESD204B Sync Enb B DIR # NET 'PMT_ADC_SYNC_ENB_B_CMP' # ADC JESD204B Sync Enb B CMP # # NET 'PMT_ADC_Trigger_DIR' # ADC Trigger Dir Input # NET 'PMT_ADC_Trigger_CMP' # ADC Trigger Cmp Input # # # End of this big section about CLOCK Type Signals # ----------------------------------------------------- # # # Clock Multiplier PLL Voltage Regulator Bypass Capacitors # NET 'ADC_PLL_REG_BYPASS' C689-1 C699-1 # Clock Multiplier PLL NET 'GROUND' C689-2 C699-2 # Voltage Regulator # Bypass Capacitors # # Clock Multiplier PLL Coarse Tuning Loop Filter Capacitor # NET 'ADC_PLL_COARSE_FILTER' C709-1 # Clock Multiplier PLL NET 'GROUND' C709-2 # Coarse Tuning Loop # Filter Capacitor # # Current Reference Resistor # NET 'ADC_CURRENT_REFERENCE' R601-1 # ADC Current Reference NET 'GROUND' R601-2 # Resistor # # Environment Sensors Net List # ------------------------------------ # # # Initial Rev. 15-Nov-2022 # Current Rev. 12-Jan-2024 # # # This net list holds the Environment Sensors # Net List. # # # The components for the Environment Sensors # are in the range 851 to 856. # # # Power and Ground to the 2x Environment Sensors # NET 'BULK_1V8' L851-2 # Bulk Power Into Filter NET 'SENSOR_1V8' L851-1 # Filtered Sensor Power NET 'SENSOR_1V8' C851-1 C852-2 C853-2 # Filter Caps on TPH Sensor NET 'GROUND' C851-2 C852-1 C853-1 # Ground Side of Filter Caps NET 'SENSOR_1V8' U851-2 U851-6 U851-8 # Filtered Power to TPH Sensor NET 'GROUND' U851-1 U851-7 # Grounds to TPH Sensor NET 'SENSOR_1V8' C854-2 C855-1 C856-1 # Filter Caps on Accel-Mag Sensor NET 'GROUND' C854-1 C855-2 C856-2 # Ground Side of Filter Caps NET 'SENSOR_1V8' U852-2 U852-9 U852-10 # Filtered Power to Accel-Mag Sensor NET 'GROUND' U852-3 U852-6 U852-8 # Grounds to Accel-Mag Sensor # # CAP on the Acceleration - Magnetic Field Sensor # NET 'ACC_SENSOR_CAP' U852-5 C857-1 NET 'GROUND' C857-2 # # Ground Jumper on the TPH Sensor's SDO pin #5 # NET 'JMP_SENSOR' U851-5 JMP851-2 NET 'GROUND' JMP851-1 # # I2C Bus and Pull-Up Resistors for # the 2x Sensors and the BB Audio ADC # NET 'I2C_DATA_SENSOR_BB_ADC' U851-3 U852-4 R851-1 # Sensor & BB ADC I2C Bus Data NET 'I2C_SCLK_SENSOR_BB_ADC' U851-4 U852-1 R852-1 # Sensor & BB ADC I2C Bus Clock NET 'SENSOR_1V8' R851-2 R852-2 # # No Connect Pins on the Acceleration - Magnetic Field Sensor # NET 'NO_CONN_ACC_SENSOR_7' U852-7 NET 'NO_CONN_ACC_SENSOR_11' U852-11 NET 'NO_CONN_ACC_SENSOR_12' U852-12 # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are 1V8 signals: Sensor & BB Audio ADC I2C Bus # --------------------------------------------------------------------- # # # NET 'I2C_DATA_SENSOR_BB_ADC' # Sensor & BB ADC I2C Bus Data # # NET 'I2C_SCLK_SENSOR_BB_ADC' # Sensor & BB ADC I2C Bus Clock # # # # Timing Generator Net List # --------------------------------- # # # Initial Rev. 15-Nov-2022 # Current Rev. 12-Jan-2024 # # # This net list holds the Timing Generator # Net List. # # # The components for the Timing Generator # are in the range 901 to 949. # # # Timing Generator: Main Timing Inputs: # ------------------------------------------ # # Reference Input "A" Differential is # DK design pin names: TG_Ref_IN_A_Dir and TG_Ref_IN_A_Cmp # # Timing Generator Reference Input A is driven by the # output of the Timing SFP Receiver in SFP connector J13. # # An external 100 Ohm terminator is required # at this Timing Generator Input (R921) and this # Timing Generator Input must be set for AC Coupled # so that it supplies its own Common Mode voltage. # No External AC Coupling Capacitors are used. NET 'SFP_Time_RD_DIR' R921-1 U901-47 # Input TG_Ref_IN_A_Dir NET 'SFP_Time_RD_CMP' R921-2 U901-46 # Input TG_Ref_IN_A_Cmp NET 'TG_Ref_IN_B_Dir' U901-38 R925-1 # Unused REFB Input - Tie it Off NET 'TG_Ref_IN_B_Cmp' U901-39 R926-1 # Unused REFBB Input - Tie it Off # # The Timing Generator Reference Input B is not used. # Tie it Off so that this Differential Input is a valid Low. # NET 'TIME_GEN_1V8' R925-2 # 1V8 Source for the Tie Off Pull-Up NET 'GROUND' R926-2 # Ground Anchor on the Tie Off Pull-Down # # Timing Generator: Auxiliary Inputs: # ---------------------------------------- # # The VDDIOA and VDDIOB power feeds to the AD9546 Timing Generator # are 3V3 so these single ended inputs are 3V3 CMOS logic level. # # M0 is not used and is Tied Off Low # M1 is for Timing the FPGA "Flash Now" signal # M2 is for Timing the "Flash Seen" signal from Interposer #1 # M3 is for Timing the "Flash Seen" signal from Interposer #2 NET 'TG_Aux_IN_M0' U901-32 R924-1 # Tie Off Pull-Down connection to M0 NET 'TG_Aux_IN_M1' U901-33 NET 'TG_Aux_IN_M2' U901-35 NET 'TG_Aux_IN_M3' U901-36 NET 'GROUND' R924-2 # Ground Anchor on the Tie Off Pull-Down # # Timing Generator: Crystal Oscillator: # -------------------------------------- # NET 'TG_Crystal_XOA' U901-42 Y901-1 C951-1 # TG XOA Pin NET 'TG_Crystal_XOB' U901-43 Y901-3 C952-1 # TG XOA Pin NET 'GROUND' Y901-2 Y901-4 # Ground XTAL Pkg Pins NET 'GROUND' C951-2 C952-2 # Ground Tuning Caps # # Timing Generator: I2C Control Bus and Pull-Ups: # ------------------------------------------------------ # # The I2C bus for the Timing Generator comes from # the FPGA/CPU I2C Controller #0 Fan-Out (U1601) # and it is Channel #0 on this I2C Fan-Out chip. # NET 'TG_I2C_SCLK' U901-2 R922-1 # SCLK with I2C Controller #0 Fan-Out Ch #0 NET 'TG_I2C_SDATA' U901-4 R923-1 # SDATA with I2C Controller #0 Fan-Out Ch #0 NET 'BULK_3V3' R922-2 R923-2 # Pull-Up 3V3 Source # # Timing Generator: RESET Pin # ---------------------------- NET 'Clock_Gen_Reset_B' U901-48 # # Timing Generator: Do Not Connect Pins: # --------------------------------------- NET 'NO_CONN_TG_DNC_16' U901-16 NET 'NO_CONN_TG_DNC_21' U901-21 NET 'NO_CONN_TG_DNC_44' U901-44 # # Timing Generator: Outputs, Pull-Up Rs, and AC Coupling Cs: # -------------------------------------------------------------- # NET 'TG_Output_0A_Dir' U901-11 R911-1 C941-1 # Output 0A Dir NET 'TG_Output_0A_Cmp' U901-12 R912-1 C942-1 # Output 0A Cmp NET 'TG_Output_0B_Dir' U901-14 R913-1 # Output 0B Dir NET 'TG_Output_0B_Cmp' U901-15 R914-1 # Output 0B Cmp # Timing Generator Output 0-C is connected to the # Timing SFP Transmitter. This is the Return signal # to the Source of timing for the AD9546 Timing Generator. # No External AC Coupling Capacitors are used, no C945, C946. NET 'SFP_Time_TD_DIR' U901-17 R915-1 # Output 0C Dir TG_Output_0C_Dir NET 'SFP_Time_TD_CMP' U901-18 R916-1 # Output 0C Cmp TG_Output_0C_Cmp NET 'TG_Output_1A_Dir' U901-25 R917-1 C947-1 # Output 1A Dir NET 'TG_Output_1A_Cmp' U901-26 R918-1 C948-1 # Output 1A Cmp NET 'TG_Output_1B_Dir' U901-22 R919-1 C949-1 # Output 1B Dir NET 'TG_Output_1B_Cmp' U901-23 R920-1 C950-1 # Output 1B Cmp # # Connect the Timing Generator Outputs 1A and 1B to: AC Coupled # # Time Gen Output 1A to XCVR_1A_REF_CLK_IN L23, L24 JESD Clock # # Time Gen Output 1B to CCC_SE_CLK_IN_S_9 J14, H14 a Spare Clk # GPIO11PB1/CLKIN_S_9 Bank #1 # NET 'XCVR_1A_REF_CLK_IN_Dir' C947-2 U1-L23 # XCVR_1A_REF_CLK_IN_Dir JESD Clock NET 'XCVR_1A_REF_CLK_IN_Cmp' C948-2 U1-L24 # XCVR_1A_REF_CLK_IN_Cmp JESD Clock NET 'FPGA_CCC_SE_CLK_IN_S_9_Dir' C949-2 U1-J14 # Spare Clock Time Gen to FPGA Dir NET 'FPGA_CCC_SE_CLK_IN_S_9_Cmp' C950-2 U1-H14 # Spare Clock Time Gen to FPGA Cmp NET 'TIME_GEN_1V8' R911-2 R912-2 # Connect the NET 'TIME_GEN_1V8' R913-2 R914-2 # Output Pull-Up NET 'TIME_GEN_1V8' R915-2 R916-2 # Resistors to the NET 'TIME_GEN_1V8' R917-2 R918-2 # Timing_Generator NET 'TIME_GEN_1V8' R919-2 R920-2 # 1V8 Power Rail # # Rs and Cs for: Setup, Internal Supplies, and Loop Filters: # ---------------------------------------------------------- # NET 'Time_Gen_M4_Pull_Up' R901-1 U901-37 # Pull-Up the M4 pin NET 'Time_Gen_M5_Pull_Dn' R902-1 U901-1 # Pull-Down the M5 pin NET 'Time_Gen_M6_Pull_Dn' R903-1 U901-5 # Pull-Down the M6 pin NET 'TIME_GEN_3V3' R901-2 # Pull-Uo 3V3 Power NET 'GROUND' R902-2 R903-2 # Pull-Down Ground NET 'Time_Gen_LF_0' C932-1 U901-8 # 3.9 nFd Cap to LF_0 NET 'Time_Gen_LDO_0' C931-1 C932-2 U901-7 # Both Caps to LDO_0 NET 'GROUND' C931-2 # 220 nFd Cap to Ground NET 'Time_Gen_LF_1' C934-1 U901-29 # 3.9 nFd Cap to LF_1 NET 'Time_Gen_LDO_1' C933-1 C934-2 U901-30 # Both Caps to LDO_1 NET 'GROUND' C933-2 # 220 nFd Cap to Ground # # 1.8 Volt Power to the AD9546: # NET 'BULK_1V8' L901-2 # Bulk_1V8 Power to Filter NET 'TIME_GEN_1V8' L901-1 # Filtered Timing Gen 1V8 Power NET 'TIME_GEN_1V8' C901-1 C902-1 C903-1 C904-1 # 1V8 Bypass Caps NET 'GROUND' C901-2 C902-2 C903-2 C904-2 # Ground Side of Filter Caps NET 'TIME_GEN_1V8' C905-1 C906-1 C907-1 C908-1 # 1V8 Bypass Caps NET 'GROUND' C905-2 C906-2 C907-2 C908-2 # Ground Side of Filter Caps NET 'TIME_GEN_1V8' C909-1 C910-1 C911-1 C912-1 # 1V8 Bypass Caps NET 'GROUND' C909-2 C910-2 C911-2 C912-2 # Ground Side of Filter Caps NET 'TIME_GEN_1V8' C913-1 C914-1 C915-1 C916-1 # 1V8 Bypass Caps NET 'GROUND' C913-2 C914-2 C915-2 C916-2 # Ground Side of Filter Caps NET 'TIME_GEN_1V8' U901-6 U901-9 U901-20 U901-28 # 1V8 to the Timing Generator NET 'TIME_GEN_1V8' U901-31 U901-40 U901-41 U901-45 # 1V8 to the Timing Generator # # 1.8 Volt Power to the AD9546's Differential Output Drivers: # NET 'TIME_GEN_1V8' L903-1 L904-1 L905-1 # 1V8 power to Diff Output Inductors NET 'TIME_GEN_1V8' L906-1 L907-1 # 1V8 power to Diff Output Inductors NET 'Diff_Out_0A_Power' L903-2 U901-10 # 1V8 power to Diff Output 0A NET 'Diff_Out_0B_Power' L904-2 U901-13 # 1V8 power to Diff Output 0B NET 'Diff_Out_0C_Power' L905-2 U901-19 # 1V8 power to Diff Output 0C NET 'Diff_Out_1A_Power' L906-2 U901-27 # 1V8 power to Diff Output 1A NET 'Diff_Out_1B_Power' L907-2 U901-24 # 1V8 power to Diff Output 1B # # 3.3 Volt Power to the AD9546: # NET 'BULK_3V3' L902-2 # Bulk_3V3 Power to Filter NET 'TIME_GEN_3V3' L902-1 # Filtered Timing Gen 1V8 Power NET 'TIME_GEN_3V3' C921-1 C922-1 C923-1 C924-1 # 3V3 Bypass Caps NET 'GROUND' C921-2 C922-2 C923-2 C924-2 # Ground Side of Filter Caps NET 'TIME_GEN_3V3' C925-1 # 3V3 Bypass Caps NET 'GROUND' C925-2 # Ground Side of Filter Caps NET 'TIME_GEN_3V3' U901-3 U901-34 # 3V3 to the Timing Generator # # Grounds to the AD9546's Thermal Pad 25 ground connections: # NET 'GROUND' U901-51 U901-52 U901-53 U901-54 # Grounds to the AD9546 NET 'GROUND' U901-55 U901-56 U901-57 U901-58 # Grounds to the AD9546 NET 'GROUND' U901-59 U901-60 U901-61 U901-62 # Grounds to the AD9546 NET 'GROUND' U901-63 U901-64 U901-65 U901-66 # Grounds to the AD9546 NET 'GROUND' U901-67 U901-68 U901-69 U901-70 # Grounds to the AD9546 NET 'GROUND' U901-71 U901-72 U901-73 U901-74 # Grounds to the AD9546 NET 'GROUND' U901-75 # Grounds to the AD9546 # # Emergency Rescue uProcessor & RS-485 Transceiver # --------------------------------------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 20-Nov-2022 # Current Rev. 22-Dec-2023 # # # This net list holds the Rescue uProc & RS-485 Transceiver # Net List. # # # The components for the Rescue uProc & RS-485 Transceiver # are in the range 1001 to 1049. # # # NOTE: These Emergency Rescue functions use 1 section # of the U1551 hex inverter that is officially # part of the Barnacle Interface circuit. # # # Connect the RS-485 Transceiver to the DOWN Main Cable: # -------------------------------------------------------- # NET 'RS485_DOWN_DIR' U1002-6 # Transceiver DIR to Down Cable NET 'RS485_DOWN_CMP' U1002-7 # Transceiver CMP to Down Cable # # Jumpers to Connect the RS-485 Up & DOWN Main Cables: # -------------------------------------------------------- # NET 'RS485_DOWN_DIR' JMP1001-1 # Jumper to connect Up & Down DIR NET 'RS485_UP_DIR' JMP1001-2 # NET 'RS485_DOWN_CMP' JMP1002-1 # Jumper to connect Up & Down CMP NET 'RS485_UP_CMP' JMP1002-2 # # # Jumpers to Connect the RS-485 DOWN Cable to the Biased Terminator: # ------------------------------------------------------------------------ # NET 'RS485_DOWN_DIR' JMP1003-2 # Jumper for Down DIR to Terminator NET 'RS485_DOWN_CMP' JMP1004-2 # Jumper for DOWN CMP to Terminator NET 'RS485_TERM_DIR' JMP1003-1 R1005-2 R1006-2 # Terminator DIR NET 'RS485_TERM_CMP' JMP1004-1 R1007-2 R1008-2 # Terminator CMP NET 'RS485_TERM_MID' R1006-1 R1007-1 C1011-2 # Terminator Middle with # Common Mode Clamp Capacitor NET 'RESCUE_3V3' R1005-1 C1012-1 # Bias UP supply NET 'GROUND' R1008-1 # Bias DOWN Anchor NET 'GROUND' C1011-1 C1012-2 # Ground the Caps # # Connect the RS-485 Transceiver to the ER uProcessor: # ----------------------------------------------------- # NET 'GROUND' U1002-2 # Transceiver Receiver Enable_B NET 'RESCUE_UART_0_Rx' U1002-1 U1001-14 R1002-2 # Received Data from RS-485 NET 'RESCUE_3V3' R1002-1 # Pull-Up Supply NET 'RESCUE_UART_0_Tx' U1001-13 U1002-4 # Transmited Data to RS-485 NET 'RESCUE_RS_485_Tx_Enb' U1002-3 R1004-2 # Transceiver Transmitter Enable NET 'GROUND' R1004-1 # Pull-Down Anchor # # Connect the J8 DeBug Connector to the ER uProcessor: # ------------------------------------------------------- # NET 'RESCUE_PIO_0_0_TDO' U1001-24 J8-6 # TDO Connection to the ER uProcessor NET 'RESCUE_PIO_0_1_TDI' U1001-16 J8-8 # TDI Connection to the ER uProcessor NET 'RESCUE_PIO_0_2_TMS_SWDIO' U1001-7 J8-2 # TMS SWDIO Connection to the ER uProcessor NET 'RESCUE_PIO_0_3_TCK_SWCLK' U1001-6 J8-4 # TCK SWCLK Connection to the ER uProcessor NET 'RESCUE_PIO_0_4_TRST' U1001-4 J8-7 # TRST Connection to the ER uProcessor NET 'RESCUE_PIO_0_5_RESET' U1001-3 J8-10 # RESET Connection to the ER uProcessor NET 'RESCUE_PIO_0_0_TDO' R1009-2 # Pull-Up on the TDO JTAG NET 'RESCUE_3V3' R1009-1 # signal for the ER uProcessor NET 'RESCUE_PIO_0_1_TDI' R1010-2 # Pull-Up on the TDI JTAG NET 'RESCUE_3V3' R1010-1 # signal for the ER uProcessor NET 'RESCUE_PIO_0_2_TMS_SWDIO' R1011-2 # Pull-Up on the TMS JTAG NET 'RESCUE_3V3' R1011-1 # SWDIO signal for the ER uProcessor NET 'RESCUE_PIO_0_3_TCK_SWCLK' R1012-2 # Pull-Up on the TCK JTAG NET 'RESCUE_3V3' R1012-1 # SWCLK signal for the ER uProcessor NET 'RESCUE_PIO_0_4_TRST' R1013-2 # Pull-Up on the TRST JTAG NET 'RESCUE_3V3' R1013-1 # signal for the ER uProcessor NET 'RESCUE_PIO_0_5_RESET' R1001-2 # Pull-Up on the RESET NET 'RESCUE_3V3' R1001-1 # for the ER uProcessor NET 'BULK_3V3' F1001-1 # FUSED 3V3 Power for the Rescue NET 'FUSED_RESCUE_DEBUG_3V3' F1001-2 J8-1 # uProcessor DeBug Connector pin 1 NET 'GROUND' J8-3 J8-5 J8-9 # Ground Pins in the DeBug Connector # # ER uProcessor ISP_Mode_B Jumper and Its Default Pull-Up Resistor: # --------------------------------------------------------------------- # NET 'RESCUE_PIO_0_12_ISP_Mode_B' U1001-2 JMP1005-2 # ER uProcessor ISP Mode B Jumper NET 'GROUND' JMP1005-1 # Jumper to Ground NET 'RESCUE_PIO_0_12_ISP_Mode_B' R1014-2 # Pull-Up on the ISP Mode pin NET 'RESCUE_3V3' R1014-1 # Pull-Up supply # # ER uProcessor Interface Signals to the DK Board: # ------------------------------------------------- # NET 'RESCUE_PIO_0_16_UART_0_RST' U1001-10 # UART 0 RST - Request to Enable the RS485 # Driver. Special High Drive Output Pin NET 'RESCUE_PIO_0_27_Take_Over_Cmd' U1001-11 # Command to Take Control of the SPI Bus # to the DK's FPGA/CPU Boot Memory NET 'RESCUE_PIO_0_26_AWAKE' U1001-12 # Asserted High AWAKE NET 'RESCUE_PIO_0_15_AWAKE_B' U1001-15 # Asserted Low AWAKE NET 'RESCUE_PIO_0_14_SPI_SCK' U1001-25 # Serial Clock \ # | SPI Bus to NET 'RESCUE_PIO_0_23_SPI_MOSI' U1001-26 # Master Data to Slave | the DK's # | FPGA/CPU NET 'RESCUE_PIO_0_22_SPI_MISO' U1001-27 # Slave Data to Master | Boot # | Memory NET 'RESCUE_PIO_0_21_SPI_SSEL0' U1001-28 # Slave Select 0 / NET 'RESCUE_PIO_0_7_UART_1_Tx' U1001-22 # ER UART 1 Data to Header Pins NET 'RESCUE_PIO_0_6_UART_1_Rx' U1001-23 # Header Pin Data to ER UART 1 NET 'RESCUE_PIO_0_20_UART_2_Tx' U1001-29 # ER UART 2 Data to DK's FPGA/CPU UART NET 'RESCUE_PIO_0_19_UART_2_Rx' U1001-30 # DK's FPGA/CPU UART Data to ER UART 2 NET 'RESCUE_PIO_0_18_UART_3_Tx' U1001-31 # ER UART 3 Data to (TOMCat ?) NET 'RESCUE_PIO_0_13_UART_3_Rx' U1001-1 # (TOMCat ?) Data to the ER UART 3 # # ER uProcessor NO Connect Pins: # ------------------------------- # NET 'NO_CONN_RESCUE_Pin_5' U1001-5 # ER uProcessor No Connect WKTCLKIN NET 'NO_CONN_RESCUE_Pin_8' U1001-8 # ER uProcessor No Connect I2C0_SDA NET 'NO_CONN_RESCUE_Pin_9' U1001-9 # ER uProcessor No Connect I2C0_SCL NET 'NO_CONN_RESCUE_Pin_17' U1001-17 # ER uProcessor No Connect XTAL_OUT NET 'NO_CONN_RESCUE_Pin_18' U1001-18 # ER uProcessor No Connect XTAL_IN NET 'NO_CONN_RESCUE_Pin_32' U1001-32 # ER uProcessor No Connect DACOUT_0 # # Hardwired Logic to Enable "Take Over" and Enable RS-485 Transmitter: # ---------------------------------------------------------------------------- # # NOTE: These functions use 1 section of the U1551 # hex inverter that is officially part of the # Barnacle Interface circuit. # # Do not get confused - there are separate SANE signals # for the DK's CPU and for the Emergency Rescue uProcessor. # # # Generate the Rescue uProcessor Is Sane Signal # NET 'RESCUE_PIO_0_15_AWAKE_B' U1551-1 R1017-1 # ER AWAKE_B signal to inverter NET 'RESCUE_3V3' R1017-2 # Default Pull-Up Supply NET 'ER_uProc_Awake_B_Inv' U1551-2 U1003-4 # Inverted ER uProc AWAKE_B NET 'RESCUE_PIO_0_26_AWAKE' U1003-5 R1018-1 # ER AWAKE signal NET 'GROUND' R1018-2 # Default Pull-Down Anchor NET 'ER_uProc_Is_Sane' U1003-6 # ER uProcessor Is Sane # # Generate the RS-485 Driver Enable Signal RST AND ER_Sane --> Drv_Enb # NET 'RESCUE_PIO_0_16_UART_0_RST' U1003-1 R1003-1 # ER uProc UART 0 RTS signal NET 'GROUND' R1003-2 # Default Pull-Down Anchor NET 'ER_uProc_Is_Sane' U1003-2 # ER uProcessor Is Sane NET 'RESCUE_RS_485_Tx_Enb' U1003-3 # Rescue RS-485 Driver Enable # # Generate the Emergency Rescue Takes Control of the BOOT Memory SPI Bus Signal # NET 'RESCUE_PIO_0_27_Take_Over_Cmd' U1003-13 R1016-1 # Command Take Control of the SPI Bus # for the DK's FPGA/CPU Boot Memory NET 'GROUND' R1016-2 # Its default Pull-Down Anchor NET 'DK_CPU_IS_SANE_B' JMP1011-1 # DK_CPU_Is_Sane_B to Jumper # DK_CPU_Is_Sane_B comes from # U1602 in the SFP Module circuits NET 'RESCUE_3V3' JMP1012-1 # Jumper used to Force the ER HW Logic # to Ignore the Sane/Not_Sane state # of the DK's CPU NET 'Sel_DK_CPU_State_OR_HW' JMP1011-2 JMP1012-2 # Jumper Common - used to Select: NET 'Sel_DK_CPU_State_OR_HW' U1003-12 # DK CPU's Real State OR # Ignore the DK's CPU State NET 'ER_Command_AND_CPU_State' U1003-11 # Take Over Command AND DK CPU's State # Its Real State OR Ignore Its State NET 'ER_uProc_Is_Sane' U1003-9 # ER uProcessor Is Sane NET 'ER_Command_AND_CPU_State' U1003-10 # This step makes the AND of: # Take Over Command # AND ER_uProc_Is_Sane # AND DK CPU's State - # Its Real State OR Ignore Its State NET 'ER_Controls_Boot_SPI' U1003-8 # Control Signal to the Boot # Memory SPI Bus Multiplexer # # 3.3 Volt Power and Grounds to U1001 ER uProcessor: # ---------------------------------------------------- # NET 'BULK_3V3' L1001-2 # Bulk_3V3 Power to Filter NET 'RESCUE_3V3' L1001-1 # Filtered Rescue 3V3 Power NET 'RESCUE_3V3' C1001-1 C1002-1 C1003-1 # 3V3 Bypass Caps NET 'GROUND' C1001-2 C1002-2 C1003-2 # Ground Side of Filter Caps NET 'RESCUE_3V3' U1001-19 U1001-21 # 3V3 Power to the Rescue uProcessor NET 'GROUND' U1001-33 U1001-20 # Grounds to the Rescue uProcesssor # # 3V3 power to the VDD and VREFP pins # Grounds to the GND and VREFN pins # # # Now Grounds to the other 3 Center Pad Thermal Vias # NET 'GROUND' U1001-34 U1001-35 U1001-36 # Ground the other 3 Thermal Vias # # 3.3 Volt Power and Grounds to U1002 RS-485 Transceiver: # --------------------------------------------------------- # NET 'BULK_3V3' C1004-2 C1005-2 # 3V3 Bypass Caps NET 'GROUND' C1004-1 C1005-1 # Ground Side of Filter Caps NET 'BULK_3V3' U1002-8 # 3V3 Power to the RS-485 Transceiver NET 'GROUND' U1002-5 # Ground to the RS-485 Transceiver # # 3.3 Volt Power and Grounds to U1003 Hardwired Logic: # -------------------------------------------------------------- # NET 'BULK_3V3' U1003-14 C1006-2 # 3V3 Power to the Hardwired Logic NET 'GROUND' U1003-7 C1006-1 # Ground to the Hardwired Logic # # USB Phy Nets and Connection to the DK's CPU # ----------------------------------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 24-Nov-2022 # Current Rev. 5-Dec-2023 # # # This net list holds the USB Phy and Its Connection # to the DK's CPU and the USB Power nets. # # # The components for the USB Phy and Its Power and # connection to the DK's CPU are in the range 1051 to 1099. # # # USB Phy to/from DK CPU Connections this is the ULPI Interface: # ---------------------------------------------------------------------- # NET 'CPU_USB_CLK' U1-N2 R1051-2 # CPU USB_CLK to Term Resistor NET 'USB_PHY_CLK' U1051-1 R1051-1 # Phy USB_CLK from Term Resistor NET 'CPU_USB_DIR' U1-N3 R1052-2 # CPU USB_DIR to Term Resistor NET 'USB_PHY_DIR' U1051-31 R1052-1 # Phy USB_RIR from Term Resistor NET 'CPU_USB_NXT' U1-M4 R1053-2 # CPU USB_NXT to Term Resistor NET 'USB_PHY_NXT' U1051-2 R1053-1 # Phy USB_NXT from Term Resistor NET 'CPU_USB_STP' U1-M5 R1054-2 # CPU USB_STP to Term Resistor NET 'USB_PHY_STP' U1051-29 R1054-1 # Phy USB_STP from Term Resistor NET 'CPU_USB_DATA_0' U1-N1 R1055-2 # CPU USB_DATA_0 to Term Resistor NET 'USB_PHY_DATA_0' U1051-3 R1055-1 # Phy USB_DATA_0 from Term Resistor NET 'CPU_USB_DATA_1' U1-M1 R1056-2 # CPU USB_DATA_1 to Term Resistor NET 'USB_PHY_DATA_1' U1051-4 R1056-1 # Phy USB_DATA_1 from Term Resistor NET 'CPU_USB_DATA_2' U1-L3 R1057-2 # CPU USB_DATA_2 to Term Resistor NET 'USB_PHY_DATA_2' U1051-5 R1057-1 # Phy USB_DATA_2 from Term Resistor NET 'CPU_USB_DATA_3' U1-L4 R1058-2 # CPU USB_DATA_3 to Term Resistor NET 'USB_PHY_DATA_3' U1051-6 R1058-1 # Phy USB_DATA_3 from Term Resistor NET 'CPU_USB_DATA_4' U1-M2 R1059-2 # CPU USB_DATA_4 to Term Resistor NET 'USB_PHY_DATA_4' U1051-7 R1059-1 # Phy USB_DATA_4 from Term Resistor NET 'CPU_USB_DATA_5' U1-L2 R1060-2 # CPU USB_DATA_5 to Term Resistor NET 'USB_PHY_DATA_5' U1051-9 R1060-1 # Phy USB_DATA_5 from Term Resistor NET 'CPU_USB_DATA_6' U1-L5 R1061-2 # CPU USB_DATA_6 to Term Resistor NET 'USB_PHY_DATA_6' U1051-10 R1061-1 # Phy USB_DATA_6 from Term Resistor NET 'CPU_USB_DATA_7' U1-M6 R1062-2 # CPU USB_DATA_7 to Term Resistor NET 'USB_PHY_DATA_7' U1051-13 R1062-1 # Phy USB_DATA_7 from Term Resistor # # Reference Clock from a PLL in the FPGA to the USB Phy Reference Clock Input Pin: # ------------------------------------------------------------------------------------ NET 'FPGA_Ref_Clk_to_USB_Phy' R1063-2 # FPGA USB Phy Ref Clk to Series Term NET 'USB_PHY_Ref_Clk_Input' U1051-26 R1063-1 # Series Term to USB Phy Ref Clk Input # # USB RESET Signal: # ------------------- # NET 'USB_RESET_B' U1051-27 # USB_Reset_B signal to USB Phy chip NET 'USB_RESET_B' U1052-1 # USB_Reset_B signal to USB High Side Switch # # USB Phy Chip - No_Conn and Pad Pins: # -------------------------------------- # NET 'NO_CONN_USB_Pin_12' U1051-12 # USB No_Conn Pin 12 NC NET 'NO_CONN_USB_Pin_15' U1051-15 # USB No_Conn Pin 15 SPK_L NET 'NO_CONN_USB_Pin_16' U1051-16 # USB No_Conn Pin 16 SPK_R NET 'NO_CONN_USB_Pin_25' U1051-25 # USB No_Conn Pin 25 XO NET 'NO_CONN_USB_Pin_30' U1051-30 # USB No_Conn Pin 30 NC NET 'USB_PHY_CPEN_OUTPUT' U1051-17 TP1051-1 # USB Phy Pin 17 CPEN Output # routed to a Test Point Pad # # USB Phy Chip - Jumper Setup and Control Pins: # ----------------------------------------------- # # USB Phy Reference Frequency Select Jumpers NET 'USB_PHY_REF_SEL_0' U1051-8 # USB Phy Ref Select 0 Pin NET 'USB_PHY_REF_SEL_1' U1051-11 # USB Phy Ref Select 1 Pin NET 'USB_PHY_REF_SEL_2' U1051-14 # USB Phy Ref Select 2 Pin NET 'USB_PHY_REF_SEL_0' JMP1051-1 JMP1052-2 # USB Phy Reference Frequency Select 0 NET 'USB_PHY_REF_SEL_1' JMP1053-1 JMP1054-2 # USB Phy Reference Frequency Select 1 NET 'USB_PHY_REF_SEL_2' JMP1055-1 JMP1056-2 # USB Phy Reference Frequency Select 2 NET 'USB_PHY_3V3' JMP1051-2 JMP1053-2 JMP1055-2 # Pull-Up Source to Jumpers NET 'GROUND' JMP1052-1 JMP1054-1 JMP1056-1 # Ground Anchor to Jumpers # USB Phy ID Select Jumpers NET 'USB_PHY_ID_SEL' U1051-23 # USB Phy ID Pin NET 'USB_PHY_ID_SEL' JMP1057-1 JMP1058-2 # USB Phy ID Select Jumpers NET 'USB_PHY_3V3' JMP1057-2 # Pull-Up Source to Jumpers NET 'GROUND' JMP1058-1 # Ground Anchor to Jumpers # USB Phy VBUS Select Resistors NET 'USB_PHY_VBUS_SEL' U1051-22 # USB Phy VBUS Select Pin NET 'USB_PHY_VBUS_SEL' R1065-1 R1066-2 # USB Phy VBUS Select Resistors NET 'USB_PHY_3V3' R1065-2 # Pull-Up Source to Resistor NET 'GROUND' R1066-1 # Ground Anchor to Resistor # # USB Connector Pin Connections: # -------------------------------- # NET 'USB_Data_Dir' J15-3 # USB Data Direct NET 'USB_Data_Cmp' J15-2 # USB Data Complement NET 'USB_Switched_Pos_Power' J15-1 # USB Switched Positive Power NET 'GROUND' J15-4 # USB Power Return NET 'GROUND' J15-5 J15-6 # USB Connector Shield NET 'GROUND' J15-7 J15-8 # USB Connector Shield # # USB Phy Chip Data to/from USB Connector: # -------------------------------------------- # NET 'USB_Data_Dir' U1051-18 TVS1052-1 # USB Direct Data NET 'USB_Data_Cmp' U1051-19 TVS1051-1 # USB Complement Data NET 'GROUND' TVS1051-2 TVS1052-2 # Ground the ESD Suppressors # # USB High Side Switch Input Power & Control: # ---------------------------------------------- # NET 'BULK_5V0' F1051-1 # Bulk Power Fuse to High-Side Swch NET 'USB_HS_5V0' F1051-2 L1052-2 # Fused Power to High-Side Swch Filter NET 'USB_FLTR_5V0' C1057-1 L1052-1 U1052-7 # Filtered Power to High-Side Swch NET 'GROUND' C1057-2 # Gnd the Filter Bypass Cap for HS Swch NET 'GROUND' U1052-3 # Gnd of the USB High-Side Switch NET 'USB_HS_SWCH_FLAG' R1068-2 U1052-2 # USB High-Side Swch FLAG pin NET 'USB_FLTR_5V0' R1068-1 # Pull-Up Source for FLAG PU Resistor NET 'USB_HS_SWCH_ILIM' R1067-2 U1052-4 # USB HS Swch I_Limit Resistor NET 'GROUND' R1067-1 # Ground the I_Limit Resistor NET 'NO_CONN_USB_HS_SWCH_5' U1052-5 # No_Conn Pin 5 on the USB HS Swch # # USB High Side Switch Power to USB Connector: # ------------------------------------------------ # NET 'USB_SWITCHED_POS_POWER' U1052-6 U1052-8 # Switched USB Power to Connector NET 'USB_SWITCHED_POS_POWER' C1058-1 # Switched USB Power to Connector NET 'GROUND' C1058-2 # Ground the USB Conn Power Cap # # Internal PS and Bias Connections for the USB Phy Chip: # --------------------------------------------------------- # NET 'USB_PHY_Int_3V3' U1051-20 C1055-1 # Bypass USB Phy Internal 3V3 NET 'USB_PHY_Int_1V8' U1051-28 C1056-1 # Bypass USB Phy Internal 1V8 NET 'GROUND' C1055-2 C1056-2 # Ground Side of Bypass Caps NET 'USB_PHY_Int_BIAS' U1051-24 R1064-2 # USB Phy BIAS Set Resistor NET 'GROUND' R1064-1 # Ground Side of Bias Set Resistor # # 3.3 Volt Power and Grounds to USB Phy Chip: # ----------------------------------------------- # NET 'BULK_3V3' L1051-1 # Bulk_3V3 Power to Filter NET 'USB_PHY_3V3' L1051-2 # Filtered USB 3V3 Power NET 'USB_PHY_3V3' C1051-2 C1052-2 # 3V3 Bypass Caps NET 'GROUND' C1051-1 C1052-1 # Ground Side of Filter Caps NET 'USB_PHY_3V3' U1051-32 # 3V3 Power to the USB Phy Chip NET 'GROUND' U1051-33 U1051-34 U1051-35 # Grounds to the USB Phy Chip NET 'GROUND' U1051-36 U1051-37 U1051-38 # Grounds to the USB Phy Chip NET 'GROUND' U1051-39 U1051-40 U1051-41 # Grounds to the USB Phy Chip # # 5.0 Volt Power to USB Phy Chip: # ----------------------------------- # NET 'BULK_5V0' C1053-1 C1054-1 # 5V0 Bypass Caps NET 'GROUND' C1053-2 C1054-2 # Ground Side of Filter Caps NET 'BULK_5V0' U1051-21 # 5V0 Power to the USB Phy Chip # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # This is a 3V3 signal: Reference Clock to the USB Phy chip # ------------------------------------------------------------- # # # NET 'FPGA_Ref_Clk_to_USB_Phy' # FPGA USB Phy Ref Clk to Series Term # # # # BB Audio ADC # ---------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 27-Nov-2022 # Current Rev. 5-Dec-2023 # # # This net list holds the BB Audio ADC and # its connections to the DK FPGA. # # # The components for the BB Audio ADC # are in the range 1101 to 1149. # # # BB Audio ADC Analog Input Signals & their AC Coupling Capacitors: # -------------------------------------------------------------------- # NET 'Interposer_1_Audio_DIR' C1111-2 # Interposer #1 Audio Signal DIR NET 'BB_Audio_ADC_Input_1_DIR' U1101-6 C1111-1 # BB Audio ADC Analog Input #1 DIR NET 'Interposer_1_Audio_CMP' C1112-2 # Interposer #1 Audio Signal CMP NET 'BB_Audio_ADC_Input_1_CMP' U1101-7 C1112-1 # BB Audio ADC Analog Input #1 CMP NET 'Interposer_2_Audio_DIR' C1113-2 # Interposer #2 Audio Signal DIR NET 'BB_Audio_ADC_Input_2_DIR' U1101-8 C1113-1 # BB Audio ADC Analog Input #2 DIR NET 'Interposer_2_Audio_CMP' C1114-2 # Interposer #2 Audio Signal CMP NET 'BB_Audio_ADC_Input_2_CMP' U1101-9 C1114-1 # BB Audio ADC Analog Input #2 CMP NET 'NO_CONN_Audio_ADC_Input_3_DIR' U1101-10 # No Connection Input 3 DIR pin 10 NET 'NO_CONN_Audio_ADC_Input_3_CMP' U1101-11 # No Connection Input 3 CMP pin 11 NET 'NO_CONN_Audio_ADC_Input_4_DIR' U1101-12 # No Connection Input 4 DIR pin 12 NET 'NO_CONN_Audio_ADC_Input_4_CMP' U1101-13 # No Connection Input 4 CMP pin 13 # # BB Audio ADC to/from DK FPGA Connections: # --------------------------------------------- # NET 'FPGA_BB_ADC_CLK_Out' R1101-1 # FPGA BB Audio ADC CLK to Term Resistor NET 'BB_Audio_ADC_CLK_GPIO1' U1101-20 R1101-2 # Term Resistor to BB ADC CLK GPIO1 Input NET 'BB_Audio_ADC_SDOUT' U1101-21 R1102-2 # BB ADC Serial Data to Term Resistor NET 'FPGA_BB_ADC_SDATA_IN' R1102-1 # Term Resistor to FPGA BB ADC SData Input NET 'BB_Audio_ADC_BCLK_Out' U1101-22 R1103-2 # BB ADC BCLK Output to Term Resistor NET 'FPGA_BB_ADC_BCLK_IN' R1103-1 # Term Resistor to FPGA BB ADC BCLK Input NET 'BB_Audio_ADC_FSYNC_Out' U1101-23 R1104-2 # BB ADC FSYNC Output to Term Resistor NET 'FPGA_BB_ADC_FSYNC_IN' R1104-1 # Term Resistor to FPGA BB ADC FSYNC Input # # BB Audio ADC RESET Signal: # ------------------------------ # NET 'BB_Audio_ADC_RESET_B' U1101-14 # BB Audio ADC RESET_B signal # # Internal PS and Bias Connections for the BB Audio ADC Chip: # -------------------------------------------------------------- # NET 'BB_AUDIO_ADC_AREG' U1101-2 C1105-1 C1106-2 # Bypass Analog Regulator NET 'GROUND' C1105-2 C1106-1 # Ground Side of Bypass Caps NET 'BB_AUDIO_ADC_VREF' U1101-3 C1107-1 # Bypass VREF pin NET 'GROUND' C1107-2 # Ground Side of Bypass Cap NET 'BB_AUDIO_ADC_MIC_BIAS' U1101-5 C1108-2 # Bypass MIC_BIAS pin NET 'GROUND' C1108-1 # Ground Side of Bypass Cap NET 'BB_AUDIO_ADC_DREG' U1101-24 C1109-1 C1110-2 # Bypass Digital Regulator NET 'GROUND' C1109-2 C1110-1 # Ground Side of Bypass Caps # # BB Audio ADC I2C BUS Connection: # ------------------------------------ # NET 'I2C_SCLK_SENSOR_BB_ADC' U1101-17 # I2C Bus SCLK Connection NET 'I2C_DATA_SENSOR_BB_ADC' U1101-18 # I2C Bus DATA Connection # # BB Audio ADC ADDRESS Pins: # ------------------------------ # NET 'GROUND' U1101-15 U1101-16 # Grounds to the ADDRESS pins # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are 1V8 signals: Clock to and Data from the Audio ADC # --------------------------------------------------------------------- # # # NET 'FPGA_BB_ADC_CLK_Out' # FPGA BB Audio ADC CLK to Term Resistor # # NET 'FPGA_BB_ADC_SDATA_IN' # Term Resistor to FPGA BB ADC SData Input # # NET 'FPGA_BB_ADC_BCLK_IN' # Term Resistor to FPGA BB ADC BCLK Input # # NET 'FPGA_BB_ADC_FSYNC_IN' # Term Resistor to FPGA BB ADC FSYNC Input # # # The Sensor I2C Bus connections to the FPGA (this I2C bus is also # used to setup this Audio ADC) are referenced in the Environmental # Sensors Nets File. # # # # 3.3 Volt Power and Grounds to BB Audio ADC Chip: # ---------------------------------------------------- # NET 'BULK_3V3' L1101-2 # Bulk_3V3 Power to Filter NET 'BB_AUDIO_ADC_3V3' L1101-1 # Filtered BB Audio ADC 3V3 Power NET 'BB_AUDIO_ADC_3V3' C1101-1 C1102-2 # 3V3 Bypass Caps NET 'GROUND' C1101-2 C1102-1 # Ground Side of Filter Caps NET 'BB_AUDIO_ADC_3V3' U1101-1 # 3V3 Power to the BB Audio ADC NET 'GROUND' U1101-4 # Ground to the AVSS ADC Pin NET 'GROUND' U1101-25 U1101-26 U1101-27 # Grounds to the Thermal Via Pins NET 'GROUND' U1101-28 U1101-29 U1101-30 # Grounds to the Thermal Via Pins NET 'GROUND' U1101-31 U1101-32 U1101-33 # Grounds to the Thermal Via Pins # # 1.8 Volt Power to BB Audio ADC Chip: # ---------------------------------------- # NET 'BULK_1V8' L1102-1 # Bulk_1V8 Power to Filter NET 'BB_AUDIO_ADC_1V8' L1102-2 # Filtered BB Audio ADC 1V8 Power NET 'BB_AUDIO_ADC_1V8' C1103-2 C1104-1 # 1V8 Bypass Caps NET 'GROUND' C1103-1 C1104-2 # Ground Side of Filter Caps NET 'BB_AUDIO_ADC_1V8' U1101-19 # 1V8 Power to the BB Audio ADC # # JTAG for the DK's FPGA/CPU Nets # -------------------------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 30-Nov-2023 # Current Rev. 20-Dec-2023 # # # # This net list holds the JTAG for the DK's FPGA/CPU # ------------------------------ # # The components for the # JTAG for the DK's FPGA/CPU # are in the range 1401 to 1449. # # # NOTE: the hex inverter U1402 officially belongs to # this net list file that covers the DK FPGA/CPU # JTAG circuits but that one section in the U1402 # hex inverter is used to handle inverting the # DK_CPU_Is_Awake_B signal in the Startup and Resets # net list file. # # # The JTAG connection to the FPGA/CPU on the DK board is made # via the first 10 pin on the DK J12 Access Connector. # # Access Connector J12 Pinout (first 10 pins) # ------------------------------------------------- # # 1. JTAG_TCLK 2. GROUND # 3. JTAG_TDO 4. NO_CONN # 5. JTAG_TMS 6. JTAG_3V3 # 7. NO_CONN 8. JTAG_TRSTB # 9. JTAG_TDI 10. GROUND # # # This JTAG pinout matches the MicroChip "standard" for their # PolarFire SoC parts as shown on page 15 of their, "Board # Design Guidelines" document. # # NOTE - This document is NOT consistent: # # For the TRSTB signal this document shows a 1k Ohm pull-down # resistor and the text says, "Must be connected to VDDI3 through # a 1k Ohm resistor" and it also says "TRSTB must be held Low # during device operation". What operation - normal operation # or JTAG operation ??? # # For the TCLK signal this document shows a 1k Ohm pull-down # resistor and the text says, "Must be connected to VSS through # a 10k Ohm resistor". # # See also sheets 12 and 24 of the schematics for the # PolarFire SoC SEV Kit demo board. # # From reading various other JTAG documents and checking their # demo-board schematics I will do the following on the DK board: # # TCLK Pull-Down # TMS Pull-Up # TDI Pull-Up # TDO Series Terminator # TRSTB Pull-Down # # # TCLK Input Signal to the DK Board: # --------------------------------------- # NET 'JTAG_TCLK_INPUT' J12-1 R1401-1 U1401-1 # TCLK Input to Pull-Down and 1st Buffer NET 'JTAG_TCLK_1st_2nd' U1401-2 U1401-3 # TCLK 1st Buf Output to 2nd Buf Input NET 'JTAG_TCLK_2nd_TERM' U1401-4 R1405-2 # TCLK 2nd Buf Output to Series Term NET 'JTAG_TCLK_TERM_FPGA' R1405-1 U1-H12 # TCLK Series Term to FPGA Input NET 'GROUND' R1401-2 # Pull-Down Anchor # # TMS Input Signal to the DK Board: # -------------------------------------- # NET 'JTAG_TMS_INPUT' J12-5 R1402-1 U1401-13 # TMS Input to Pull-Up and 1st Buffer NET 'JTAG_TMS_1st_2nd' U1401-12 U1401-11 # TMS 1st Buf Output to 2nd Buf Input NET 'JTAG_TMS_2nd_TERM' U1401-10 R1406-2 # TMS 2nd Buf Output to Series Term NET 'JTAG_TMS_TERM_FPGA' R1406-1 U1-J12 # TMS Series Term to FPGA Input NET 'BULK_3V3' R1402-2 # Pull-Up 3V3 Source # # TDI Input Signal to the DK Board: # -------------------------------------- # NET 'JTAG_TDI_INPUT' J12-9 R1403-1 U1401-9 # TDI Input to Pull-Up and 1st Buffer NET 'JTAG_TDI_1st_2nd' U1401-8 U1401-5 # TDI 1st Buf Output to 2nd Buf Input NET 'JTAG_TDI_2nd_TERM' U1401-6 R1407-2 # TDI 2nd Buf Output to Series Term NET 'JTAG_TDI_TERM_FPGA' R1407-1 U1-H11 # TDI Series Term to FPGA Input NET 'BULK_3V3' R1403-2 # Pull-Up 3V3 Source # # TDO Output Signal from the DK Board: # ----------------------------------------- # NET 'JTAG_TDO_FPGA_1st_TERM' U1-J11 R1409-1 # TDO FPGA Output to 1st Series Term NET 'JTAG_TDO_1st_TERM_1st_Buf' R1409-2 U1402-3 # TDO 1st Term to 1st Buf Input NET 'JTAG_TDO_1st_2nd' U1402-4 U1402-5 # TDO 1st Buf Output to 2nd Buf Input NET 'JTAG_TDO_2nd_Buf_2nd_TERM' U1402-6 R1408-2 # TDO 2nd Buf Output to 2nd Term NET 'JTAG_TDO_OUTPUT' R1408-1 J12-3 # 2nd Series Term to TDO Output Pin # # TRST_B Input Signal to the DK Board: # -------------------------------------- # NET 'JTAG_TRST_B_INPUT' J12-8 R1404-1 U1402-11 # TRST_B Input to Pull-Down and 1st Buffer NET 'JTAG_TRST_B_1st_2nd' U1402-10 U1402-9 # TRST_B 1st Buf Output to 2nd Buf Input NET 'JTAG_TRST_B_2nd_FPGA' U1402-8 U1-J10 # TRST_B 2nd Buf Output to FPGA Input NET 'GROUND' R1404-2 # Pull-Down Anchor # # 3.3 Volt Power and Grounds to the JTAG part of the J12 Access Connector: # ----------------------------------------------------------------------------- # NET 'BULK_3V3' F1401-2 # Bulk_3V3 power to the JTAG Fuse NET 'JTAG_3V3' F1401-1 J12-6 # 3V3 Power to the JTAG Connector NET 'GROUND' J12-2 J12-10 # Ground pins in the JTAG part of J12 NET 'NO_CONN_J12_Pin_4' J12-4 # No Connect Pin #4 in J12 NET 'NO_CONN_J12_Pin_7' J12-7 # No Connect Pin #7 in J12 # # 3.3 Volt Power and Grounds to the JTAG Buffer Chips: # -------------------------------------------------------- # NET 'BULK_3V3' C1401-1 C1402-1 C1403-1 # 3V3 Bypass Caps NET 'GROUND' C1401-2 C1402-2 C1403-2 # Ground Side of Bypass Caps NET 'BULK_3V3' U1401-14 U1402-14 # 3V3 Power to the Buffer Chips NET 'GROUND' U1401-7 U1402-7 # Ground pins on the Buffer Chips NET 'GROUND' U1402-13 # Ground unused input to Buffer U1402 # # CPU Boot Memory CPU QSPI Port # -=====---------------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 27-Nov-2022 # Current Rev. 30-Nov-2023 # # # This net list holds the CPU Boot Memory # its connections to the DK CPU QSPI Port. # # # The components for the CPU Boot Memory # are in the range 1201 to 1249. # # # CPU Boot Memory to/from DK CPU QSPI Port: # -===----------------------------------------- # NET 'CPU_Boot_Mem_SELECT_B' U1201-7 R1203-2 R1204-2 # Select_B to Pull-Up and Term NET 'CPU_QSPI_SS0' U1-N9 R1204-1 # Term Resistor to CPU QSPI Port NET 'CPU_Boot_Mem_DQ3_Hold_B' U1201-1 R1202-2 R1205-2 # DQ3/HOLD_B to Pull-Up and Term NET 'CPU_QSPI_DATA_3' U1-N11 R1205-1 # Term Resistor to CPU QSPI Port NET 'CPU_Boot_Mem_DQ2_W_B' U1201-9 R1201-2 R1206-2 # DQ2/W_B to Pull-Up and Term NET 'CPU_QSPI_DATA_2' U1-M11 R1206-1 # Term Resistor to CPU QSPI Port NET 'CPU_Boot_Mem_DQ1' U1201-8 R1207-2 # DQ1 to Terminator Resistor NET 'CPU_QSPI_DATA_1' U1-M9 R1207-1 # Term Resistor to CPU QSPI Port NET 'CPU_Boot_Mem_DQ0' U1201-15 R1208-2 # DQ0 to Terminator Resistor NET 'CPU_QSPI_DATA_0' U1-L10 R1208-1 # Term Resistor to CPU QSPI Port NET 'CPU_Boot_Mem_CLOCK' U1201-16 R1209-2 # CLOCK to Terminator Resistor NET 'CPU_QSPI_CLK' U1-M10 R1209-1 # Term Resistor to CPU QSPI Port NET 'BULK_3V3' R1201-1 R1202-1 R1203-1 # Pull-Up 3V3 Source # # CPU Boot Memory RESET Signal: # -===-------------------------- # NET 'CPU_Boot_Mem_RESET_B' U1201-3 R1210-2 # CPU Boot Memory RESET_B pin NET 'BULK_3V3' R1210-1 # Pull-Up 3V3 Source # # 3.3 Volt Power and Grounds to the CPU Boot Memory: # ------------------------------------===-------------- # NET 'BULK_3V3' C1201-2 C1202-2 C1203-1 # 3V3 Bypass Caps NET 'GROUND' C1201-1 C1202-1 C1203-2 # Ground Side of Bypass Caps NET 'BULK_3V3' U1201-2 # 3V3 Power to the CPU Boot Memory NET 'GROUND' U1201-10 # Ground to the CPU Boot Memory # # CPU Boot Memory No_Connect Pins: # -===------------------------------- # NET 'NO_CONN_CPU_Boot_Mem_Pin_4' U1201-4 # No Conn U1201 Pin 4 NET 'NO_CONN_CPU_Boot_Mem_Pin_5' U1201-5 # No Conn U1201 Pin 5 NET 'NO_CONN_CPU_Boot_Mem_Pin_6' U1201-6 # No Conn U1201 Pin 6 NET 'NO_CONN_CPU_Boot_Mem_Pin_11' U1201-11 # No Conn U1201 Pin 11 NET 'NO_CONN_CPU_Boot_Mem_Pin_12' U1201-12 # No Conn U1201 Pin 12 NET 'NO_CONN_CPU_Boot_Mem_Pin_13' U1201-13 # No Conn U1201 Pin 13 NET 'NO_CONN_CPU_Boot_Mem_Pin_14' U1201-14 # No Conn U1201 Pin 14 # # FPGA Boot Memory FPGA Bank #3 # -=====---------------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 27-Nov-2022 # Current Rev. 30-Nov-2023 # # # This net list holds the: # # FPGA Boot Memory and its connections to the DK FPGA Bank #3 # ------------------------------------------------------------- # # # NOTE: This file also holds the nets for some: # # Bank #3 Pull-Up Resistors for Default Operation # --------------------------------------------------- # # # The components for the FPGA Boot Memory # are in the range 1251 to 1299. # # The components for the Bank #3 Default Operation Pull-Up Resistors # are from a separate Comps file: R1351, R1352, R1353. # # # FPGA Boot Memory to/from Multiplexer: # -===--------------------------------------- # NET 'FPGA_Boot_Mem_SELECT_B' U1251-7 U1252-3 U1252-18 # Select_B from Mux. NET 'FPGA_Boot_Mem_DQ1' U1251-8 U1252-15 U1252-4 # MISO / DQ1 to Mux. NET 'FPGA_Boot_Mem_DQ0' U1251-15 U1252-7 U1252-14 # MOSI / DQ0 from Mux. NET 'FPGA_Boot_Mem_CLOCK' U1251-16 U1252-9 U1252-12 # CLOCK / SCK from Mux. # # Multiplexer to/from DK FPGA Bank #3: # ------------------------------------------ # NET 'FPGA_Bank_3_SPI_SS' U1-J9 U1252-2 # FPGA SPI SEL_B to FPGA Boot Mem Mux. NET 'FPGA_Boot_Mux_FPGA_MISO' U1252-16 R1254-2 # SPI MISO from Mux to Term Res NET 'FPGA_Bank_3_SPI_MISO' U1-K10 R1254-1 # Term Res to FPGA SPI MISO NET 'FPGA_Bank_3_SPI_MOSI' U1-H8 R1255-1 # FPGA SPI MOSI to Term Res NET 'FPGA_Boot_Mux_FPGA_MOSI' U1252-6 R1255-2 # Term Res to FPGA Boot Mem Mux. NET 'FPGA_Bank_3_SPI_SCK' U1-J8 R1256-1 # FPGA SPI SCK to Term Res NET 'FPGA_Boot_Mux_FPGA_SCK' U1252-8 R1256-2 # Term Res to FPGA Boot Mem Mux. # # Multiplexer to/from ER uProcessor: # --------------------------------------- # NET 'RESCUE_PIO_0_21_SPI_SSEL0' U1252-17 # ER uProc SPI SEL_B to FPGA Boot Mem Mux. NET 'FPGA_Boot_Mux_ER_MISO' U1252-5 R1251-2 # SPI MISO from Mux to Term Res NET 'RESCUE_PIO_0_22_SPI_MISO' R1251-1 # Term Res to ER uProc SPI MISO NET 'RESCUE_PIO_0_23_SPI_MOSI' R1252-1 # ER uProc SPI MOSI to Term Res NET 'FPGA_Boot_Mux_ER_MOSI' U1252-13 R1252-2 # Term Res to FPGA Boot Mem Mux. NET 'RESCUE_PIO_0_14_SPI_SCK' R1253-1 # ER uProc SPI SCK to Term Res NET 'FPGA_Boot_Mux_ER_SCK' U1252-11 R1253-2 # Term Res to FPGA Boot Mem Mux. NET 'ER_Controls_Boot_SPI' U1252-1 U1252-19 # Control Signal from ER uProcessor # HW Logic HI ---> ER Takes Control # of the FPGA Boot Memory SPI Bus # # Pull-Up & Pull-Down Resistors for FPGA Boot Memory Clock Signal: # -------------------------------------------------------------------- # NET 'FPGA_Boot_Mem_CLOCK' R1261-2 R1262-2 # FPGA Boot Mem CLOCK / SCLK NET 'BULK_3V3' R1261-1 # Pull-Up 3V3 Source NET 'GROUND' R1262-1 # Pull-Down Anchor # # Pull-Up Resistors on the FPGA Boot Memory: # ----------------------------====-------------- # NET 'FPGA_Boot_Mem_DQ3_HOLD_B' U1251-1 R1257-2 # FPGA Boot Memory DQ3/HOLD_B pin NET 'FPGA_Boot_Mem_RESET_B' U1251-3 R1258-2 # FPGA Boot Memory RESET_B pin NET 'FPGA_Boot_Mem_DQ2_W_B' U1251-9 R1259-1 # FPGA Boot Memory DQ2/W_B pin NET 'BULK_3V3' R1257-1 R1258-1 R1259-2 # Pull-Up 3V3 Source NET 'FPGA_Boot_Mem_SELECT_B' R1260-2 # FPGA Boot Memory SELECT_B pin NET 'BULK_3V3' R1260-1 # Pull-Up 3V3 Source # # 3.3 Volt Power and Grounds to the FPGA Boot Memory & Multiplexer Chip: # ------------------------------------===------------------------------------ # NET 'BULK_3V3' C1251-1 C1252-2 C1253-1 C1254-2 # 3V3 Bypass Caps NET 'GROUND' C1251-2 C1252-1 C1253-2 C1254-1 # Ground Side of Bypass Caps NET 'BULK_3V3' U1251-2 U1252-20 # 3V3 Power to the FPGA Boot & Mux NET 'GROUND' U1251-10 U1252-10 # Ground to the FPGA Boot & Mux # # FPGA Boot Memory No_Connect Pins: # -====------------------------------- # NET 'NO_CONN_FPGA_Boot_Mem_Pin_4' U1251-4 # No Conn U1201 Pin 4 NET 'NO_CONN_FPGA_Boot_Mem_Pin_5' U1251-5 # No Conn U1201 Pin 5 NET 'NO_CONN_FPGA_Boot_Mem_Pin_6' U1251-6 # No Conn U1201 Pin 6 NET 'NO_CONN_FPGA_Boot_Mem_Pin_11' U1251-11 # No Conn U1201 Pin 11 NET 'NO_CONN_FPGA_Boot_Mem_Pin_12' U1251-12 # No Conn U1201 Pin 12 NET 'NO_CONN_FPGA_Boot_Mem_Pin_13' U1251-13 # No Conn U1201 Pin 13 NET 'NO_CONN_FPGA_Boot_Mem_Pin_14' U1251-14 # No Conn U1201 Pin 14 # # Bank #3 Default Operation Pull-Up Resistors # ------------------------------------------------- # NET 'Bank_3_FF_EXIT_N' U1-J13 R1351-2 # Pull-Up FF_EXIT_N NET 'Bank_3_IO_CFG_INTF' U1-H13 R1352-2 # Pull-Up IO_CFG_INTF NET 'Bank_3_SPI_EN' U1-K12 R1353-2 # Pull-Up SPI_EN NET 'BULK_3V3' R1351-1 R1352-1 R1353-1 # Pull-Up 3V3 Source # # Interposer All SPI Nets # ------------------------------ # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 30-Nov-2023 # Current Rev. 21-Dec-2023 # # # # This net list holds the Interposer All SPI Nets # ---------------------------- # # The components for the # DK's Interposer All SPI Nets # are in the range 1451 to 1499. # # # NOTE: that 2 sections of the U1459 hex inverter, which # officially belongs to the Interposer_All_Other net # list file where is is used to handle the Muon SMUT signals, # is used in this net list file to handle inverting the # Interposer SPI Mux Control signals. # # # SPI Signals Mux to Interposer #1 Connector J4: # --------------------------------------------------- # NET 'Poser_1_Conn_SCLK' R1453-2 # SCLK Series Term to Poser #1 Conn NET 'Poser_1_Drv_SCLK' U1451-18 R1453-1 R1461-1 # SCLK Driver to Ser Term & Pull_Dwn NET 'Poser_1_Conn_MOSI' R1454-2 # MOSI Series Term to Poser #1 Conn NET 'Poser_1_Drv_MOSI' U1451-16 R1454-1 R1462-1 # MOSI Driver to Ser Term & Pull_Dwn NET 'Poser_1_Conn_MISO' U1451-6 R1463-2 # MISO Poser #1 Conn to Pull-Down & Receiver NET 'Poser_1_Conn_CS_B' U1451-12 R1481-2 # CS_B Driver & Pull-Up to Poser #1 Conn NET 'Poser_1_Conn_CS_A0' U1451-9 R1464-2 # CS_A0 Driver & Pull-Up to Poser #1 Conn NET 'Poser_1_Conn_CS_A1' U1451-7 R1465-2 # CS_A1 Driver & Pull-Up to Poser #1 Conn NET 'Poser_1_Conn_CS_A2' U1451-5 R1466-2 # CS_A2 Driver & Pull-Up to Poser #1 Conn NET 'BULK_3V3' R1481-1 # Pull-Up Source NET 'GROUND' R1461-2 R1462-2 R1463-1 # Pull-Down Anchor NET 'GROUND' R1464-1 R1465-1 R1466-1 # Pull-Down Anchor # # SPI Signals Mux to Interposer #2 Connector J5: # --------------------------------------------------- # NET 'Poser_2_Conn_SCLK' R1455-2 # SCLK Series Term to Poser #2 Conn NET 'Poser_2_Drv_SCLK' U1452-18 R1455-1 R1467-1 # SCLK Driver to Ser Term & Pull_Dwn NET 'Poser_2_Conn_MOSI' R1456-2 # MOSI Series Term to Poser #2 Conn NET 'Poser_2_Drv_MOSI' U1452-16 R1456-1 R1468-1 # MOSI Driver to Ser Term & Pull_Dwn NET 'Poser_2_Conn_MISO' U1452-6 R1469-2 # MISO Poser #2 Conn to Pull-Down & Receiver NET 'Poser_2_Conn_CS_B' U1452-12 R1482-2 # CS_B Driver & Pull-Up to Poser #2 Conn NET 'Poser_2_Conn_CS_A0' U1452-9 R1470-2 # CS_A0 Driver & Pull-Up to Poser #2 Conn NET 'Poser_2_Conn_CS_A1' U1452-7 R1471-2 # CS_A1 Driver & Pull-Up to Poser #2 Conn NET 'Poser_2_Conn_CS_A2' U1452-5 R1472-2 # CS_A2 Driver & Pull-Up to Poser #2 Conn NET 'BULK_3V3' R1482-1 # Pull-Up Source NET 'GROUND' R1467-2 R1468-2 R1469-1 # Pull-Down Anchor NET 'GROUND' R1470-1 R1471-1 R1472-1 # Pull-Down Anchor # # SPI Signals FPGA to/from Multiplexer: # -------------------------------------------- # NET 'Poser_SCLK_FPGA_to_Term' R1451-1 # SCLK FPGA to Series Term NET 'Poser_SCLK_Term_to_Mux' R1451-2 U1451-2 U1452-2 # SCLK Series Term to Mux NET 'Poser_MOSI_FPGA_to_Term' R1452-1 # MOSI FPGA to Series Term NET 'Poser_MOSI_Term_to_Mux' R1452-2 U1451-4 U1452-4 # MOSI Series Term to Mux NET 'Poser_MISO_Mux_to_Term' U1451-14 U1452-14 R1457-1 # MISO Mux to Term NET 'Poser_MISO_Mux_to_Term' R1473-1 # MISO Mux to Pull-Dwn NET 'Poser_MISO_Term_to_FPGA' R1457-2 # MISO Mux Term to FPGA NET 'GROUND' R1473-2 # Pull-Down Anchor # # Mux Control Signals FPGA to Multiplexer (via an inverter where necessary): # --------------------------------------------------------------------------------- # # NOTE: the use of hex inverter U1459 to handle the inversion # of the SPI Mux Control signals. Hex inverter U1459 # officially belongs to the Interposer All Other net list # file where it handles Muon SMUT signals. # NET 'Poser_CS_1_B' U1451-1 U1459-1 # FPGA to Enable one half Interposer #1 Mux _B NET 'Poser_CS_1' U1459-2 U1451-19 # Inverter to Enable other half Interposer #1 Mux NET 'Poser_CS_2_B' U1452-1 U1459-13 # FPGA to Enable one half Interposer #2 Mux _B NET 'Poser_CS_2' U1459-12 U1452-19 # Inverter to Enable other half Interposer #2 Mux # # CS Address Signals FPGA to Multiplexer: # --------------------------------------------- # NET 'Poser_CS_Adrs_0' U1451-11 U1452-11 # CS Address 0 FPGA to Mux NET 'Poser_CS_Adrs_1' U1451-13 U1452-13 # CS Address 1 FPGA to Mux NET 'Poser_CS_Adrs_2' U1451-15 U1452-15 # CS Address 2 FPGA to Mux # # Tie-Down All Unused CMOS Inputs: # -------------------------------------- # NET 'GROUND' U1451-17 U1452-17 # Tie-Down the Input to the # Unused Section of the Mux # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are 3V3 signals: SPI Bus and GPIO # ------------------------------------------------- # # NET 'Poser_SCLK_FPGA_to_Term' # SCLK FPGA to Series Term # NET 'Poser_MOSI_FPGA_to_Term' # MOSI FPGA to Series Term # NET 'Poser_MISO_Term_to_FPGA' # MISO Mux Term to FPGA # # NET 'Poser_CS_1_B' # FPGA Signal to Enable Interposer #1 Mux _B # NET 'Poser_CS_2_B' # FPGA Signal to Enable Interposer #2 Mux _B # # NET 'Poser_CS_Adrs_0' # CS Address 0 FPGA to Mux # NET 'Poser_CS_Adrs_1' # CS Address 1 FPGA to Mux # NET 'Poser_CS_Adrs_2' # CS Address 2 FPGA to Mux # # # 3.3 Volt Power and Grounds to the Interposer SPI Buffe Chips: # ------------------------------------------------------------------ # NET 'BULK_3V3' U1451-20 U1452-20 # 3V3 Power to the Buffer Chips NET 'GROUND' U1451-10 U1452-10 # Ground pins on the Buffer Chips NET 'BULK_3V3' C1451-2 C1452-2 # 3V3 Bypass Caps NET 'GROUND' C1451-1 C1452-1 # Ground Side of Bypass Caps # # Interposer All Other Nets # -------------===========------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 4-Dec-2023 # Current Rev. 27-Dec-2023 # # # # This net list holds the Interposer All Other Nets # ------------===========----- # # The components for the # DK's Interposer All Other Nets # are in the range 1451 to 1499. # # # NOTE: that 2 sections of the U1459 hex inverter, which # is shown lower in this file, are used in a different # net list file to handle the Interposer SPI Mux Control # signals. # # # PIEZO Hydrophone Connection to the BB Audio ADC Inputs # ----------------------------------------------------------- # # This connection is made in the: # # interposer_connectors_all_nets.txt # and the bb_audio_adc_nets.txt files. # # # Nets for the Interposer 1V8 UART Buffers: # ------------------------------------------------- # # Interposer #1 Serviced by CPU MMUART #3 # --------------------------------------------- NET 'CPU_UART_3_Tx__to__Poser_1' R1483-1 # DK CPU UART 3 Tx Data to Terminator NET 'Tx_to_Poser_1_Term_Buf' R1483-2 U1454-3 # DK CPU UART Tx Data to Data Buffer NET 'CPU_UART_Tx_to_Poser_1_B' U1454-4 U1454-5 # Inverted NET 'Data_to_Poser_1_Buf_Term' U1454-6 R1484-1 # Tx Data to the DK Tx Terminator NET 'DK_Tx_Data_to_Poser_1' R1484-2 J4-31 # Tx Data to the Poser_1 Connector NET 'DK_Rx_Data_from_Poser_1' J4-32 U1454-11 # Rx Data from the Poser_1 Connector NET 'DK_Rx_Data_from_Poser_1_B' U1454-10 U1454-9 # Inverted NET 'DK_Rx_Data_Psr_1_to_Term' U1454-8 R1485-1 # Rx Data from the Poser_1 to Term NET 'CPU_UART_3_Rx_from_Poser_1' R1485-2 # Rx Data from the Poser_1 via Buf # and Term to the DK's CPU UART #3 NET 'GROUND' U1454-1 U1454-13 # Tie down unused buffer inputs NET 'BULK_1V8' U1454-14 C1454-1 # 1V8 Power for UART Buffer NET 'GROUND' U1454-7 C1454-2 # Ground for the UART Buffer # Interposer #2 Serviced by CPU MMUART #4 # --------------------------------------------- NET 'CPU_UART_4_Tx__to__Poser_2' R1486-1 # DK CPU UART 4 Tx Data to Terminator NET 'Tx_to_Poser_2_Term_Buf' R1486-2 U1455-3 # DK CPU UART Tx Data to Data Buffer NET 'CPU_UART_Tx_to_Poser_2_B' U1455-4 U1455-5 # Inverted NET 'Data_to_Poser_2_Buf_Term' U1455-6 R1487-1 # Tx Data to the DK Tx Terminator NET 'DK_Tx_Data_to_Poser_2' R1487-2 J5-31 # Tx Data to the Poser_2 Connector NET 'DK_Rx_Data_from_Poser_2' J5-32 U1455-11 # Rx Data from the Poser_2 Connector NET 'DK_Rx_Data_from_Poser_2_B' U1455-10 U1455-9 # Inverted NET 'DK_Rx_Data_Psr_2_to_Term' U1455-8 R1488-1 # Rx Data from the Poser_2 to Term NET 'CPU_UART_4_Rx_from_Poser_2' R1488-2 # Rx Data from the Poser_2 via Buf # and Term to the DK's CPU UART #4 NET 'GROUND' U1455-1 U1455-13 # Tie down unused buffer inputs NET 'BULK_1V8' U1455-14 C1455-1 # 1V8 Power for UART Buffer NET 'GROUND' U1455-7 C1455-2 # Ground for the UART Buffer # # FLASH-NOW Signal from FPGA/CPU to Both Interposers and to the AD9546 TG: # ---------------------------------------------------------------------------------- # NET 'Flash_Now' R1490-2 R1491-2 # Flash_Now signal from the FPGA/CPU # This is a 3V3 CMOS single ended signal # from a "floating" pin on the FPGA/CPU # to a pair of series terminators. NET 'TG_Aux_In_M1' R1490-1 # Flash_Now from the FPGA/CPU to the "M1" Auxiliary Input # of the AD9546 Timing Generator for timing measurement. NET 'Flash_Now_to_Interposers' R1491-1 # Flash_Now from series terminator NET 'Flash_Now_to_Interposers' U1456-5 U1457-5 # to the LVDS Flash Now Drivers inputs NET 'Poser_1_Flash_Now_Dir' U1456-4 J4-7 # Flash Now DIR to This Hemisphere NET 'Poser_1_Flash_Now_Cmp' U1456-3 J4-8 # Flash Now CMP to This Hemisphere NET 'Poser_2_Flash_Now_Dir' U1457-4 J5-7 # Flash Now DIR to Other Hemisphere NET 'Poser_2_Flash_Now_Cmp' U1457-3 J5-8 # Flash Now CMP to Other Hemisphere NET 'BULK_3V3' U1456-1 U1457-1 # Bulk_3V3 to the LVDS Driver chips NET 'GROUND' U1456-2 U1457-2 # Ground to the LVDS Driver chips NET 'BULK_3V3' C1481-1 C1482-2 C1483-2 # Bulk_3V3 to the Bypass Caps NET 'GROUND' C1481-2 C1482-1 C1483-1 # Ground to the Bypass Caps # # FLASH-TDC signals from Both Interposers to the AD9546 for Timing Measurement: # ---------------------------------------------------------------------------------------- # NET 'Poser_1_Flash_TDC_In' J4-15 U1458-3 # Flash TDC Input from This Hemisphere NET 'Poser_1_Flash_TDC_Link' U1458-4 U1458-5 # Flash TDC Buf Link This Hemisphere NET 'Poser_1_Flash_TDC_Term' U1458-6 R1493-1 # Flash TDC Buf Term This Hemisphere NET 'TG_Aux_In_M2' R1493-2 # Flash TDC from This Hemisphere to the # "M2" input of the AD9546 Timing Generator # for time measurement a 3V3 CMOS signal NET 'Poser_2_Flash_TDC_In' J5-15 U1458-11 # Flash TDC Input from Other Hemisphere NET 'Poser_2_Flash_TDC_Link' U1458-10 U1458-9 # Flash TDC Bus Link Other Hemisphere NET 'Poser_2_Flash_TDC_Term' U1458-8 R1492-1 # Flash TDC Buf Term Other Hemisphere NET 'TG_Aux_In_M3' R1492-2 # Flash TDC from Other Hemisphere to the # "M3" input of the AD9546 Timing Generator # for time measurement a 3V3 CMOS signal NET 'BULK_3V3' U1458-14 C1484-2 # Bulk_3V3 to the Buffer and Bypass caps NET 'GROUND' U1458-7 C1484-1 # Ground to the buffer and Bypass caps # # Interposer Controller Reset from FPGA/CPU to Both Interposers: # ---------------------------------------------------------------------------- # NET 'Interposer_Ctrl_Reset' R1494-2 # Interposer Ctrl Reset from FPGA/CPU NET 'POSER_Reset_Term_to_Buf' R1494-1 U1458-1 U1458-13 # Series Term to Buffer Inputs NET 'POSER_1_Ctrl_Reset' U1458-2 J4-19 # Control Reset to Interposer This Hemisphere NET 'POSER_2_Ctrl_Reset' U1458-12 J5-19 # Control Reset to Interposer Other Hemisphere # # Muon SMUT S1 S2 S3 S4 signals from Other Hemishpere to the FPGA/CPU "TDCs": # --------------------------------------------------------------------------------------- # # # NOTE: that most of the U1459 hex inverter is used by the # following Muon SMUT signals but 2 sections of the # U1459 hex inverter are used in a different net list # file to handle the Interposer SPI Mux Control Lines. # NET 'SMUT_S1_Other_Hemi' J5-33 U1459-3 # Muon SMUT signal S1 from Other Hemisphere NET 'SMUT_S2_Other_Hemi' J5-35 U1459-5 # Muon SMUT signal S2 from Other Hemisphere NET 'SMUT_S3_Other_Hemi' J5-36 U1459-9 # Muon SMUT signal S3 from Other Hemisphere NET 'SMUT_S4_Other_Hemi' J5-37 U1459-11 # Muon SMUT signal S4 from Other Hemisphere NET 'Muon_S1_Other_Term' U1459-4 R1498-1 # SMUT Muon S1 Other Hemi to Term --> FPGA/CPU "TDC" NET 'Muon_S2_Other_Term' U1459-6 R1497-1 # SMUT Muon S2 Other Hemi to Term --> FPGA/CPU "TDC" NET 'Muon_S3_Other_Term' U1459-8 R1496-1 # SMUT Muon S3 Other Hemi to Term --> FPGA/CPU "TDC" NET 'Muon_S4_Other_Term' U1459-10 R1495-1 # SMUT Muon S4 Other Hemi to Term --> FPGA/CPU "TDC" NET 'Muon_S1_Other_Hemi' R1498-2 # SMUT Muon S1 Other Hemi to FPGA/CPU "TDC" NET 'Muon_S2_Other_Hemi' R1497-2 # SMUT Muon S2 Other Hemi to FPGA/CPU "TDC" NET 'Muon_S3_Other_Hemi' R1496-2 # SMUT Muon S3 Other Hemi to FPGA/CPU "TDC" NET 'Muon_S4_Other_Hemi' R1495-2 # SMUT Muon S4 Other Hemi to FPGA/CPU "TDC" NET 'NO_CONN_This_Hemi_SMUT_S1_J4_pin_33' J4-33 # No SMUT S1 in This Hemisphere NET 'NO_CONN_This_Hemi_SMUT_S2_J4_pin_35' J4-35 # No SMUT S2 in This Hemisphere NET 'NO_CONN_This_Hemi_SMUT_S3_J4_pin_36' J4-36 # No SMUT S3 in This Hemisphere NET 'NO_CONN_This_Hemi_SMUT_S4_J4_pin_37' J4-37 # No SMUT S4 in This Hemisphere NET 'BULK_3V3' U1459-14 C1485-2 # Bulk_3V3 to the Buffer and Bypass caps NET 'GROUND' U1459-7 C1485-1 # Ground to the buffer and Bypass caps # # Power Feeds to the Interposers - Isolation Filters and Bypass Capacitors # ---------------------------------------------------------------------------- # # Poser #1 1V8 Power # --------------------- NET 'BULK_1V8' C1461-2 L1461-1 # BULK_1V8 Feed to the Filter NET 'POSER_1_1V8' C1462-2 L1461-2 J4-1 J4-2 # POSER #1 1V8 Power NET 'GROUND' C1461-1 C1462-1 # Ground Anchor for the Caps # Poser #1 3V3 Power # --------------------- NET 'BULK_3V3' C1463-2 L1462-1 # BULK_3V3 Feed to the Filter NET 'POSER_1_3V3' C1464-2 L1462-2 J4-3 J4-4 # POSER #1 3V3 Power NET 'GROUND' C1463-1 C1464-1 # Ground Anchor for the Caps # Poser #1 5V0 Power # --------------------- NET 'BULK_5V0' C1465-2 L1463-1 # BULK_5V0 Feed to the Filter NET 'POSER_1_5V0' C1466-1 L1463-2 J4-39 J4-40 # POSER #1 5V0 Power NET 'GROUND' C1465-1 C1466-2 # Ground Anchor for the Caps # Poser #2 1V8 Power # --------------------- NET 'BULK_1V8' C1471-2 L1471-1 # BULK_1V8 Feed to the Filter NET 'POSER_2_1V8' C1472-1 L1471-2 J5-1 J5-2 # POSER #2 1V8 Power NET 'GROUND' C1471-1 C1472-2 # Ground Anchor for the Caps # Poser #2 3V3 Power # --------------------- NET 'BULK_3V3' C1473-2 L1472-1 # BULK_3V3 Feed to the Filter NET 'POSER_2_3V3' C1474-1 L1472-2 J5-3 J5-4 # POSER #2 3V3 Power NET 'GROUND' C1473-1 C1474-2 # Ground Anchor for the Caps # Poser #2 5V0 Power # --------------------- NET 'BULK_5V0' C1475-2 L1473-1 # BULK_5V0 Feed to the Filter NET 'POSER_2_5V0' C1476-2 L1473-2 J5-39 J5-40 # POSER #2 5V0 Power NET 'GROUND' C1475-1 C1476-1 # Ground Anchor for the Caps # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are 1V8 signals: CPU UART Data to/from both Interposers # ---------------------------------------------------------------------------- # # NET 'CPU_UART_Tx__to__Poser_1' # Tx UART Data to Interposer_1 via Buffer # NET 'CPU_UART_Rx_from_Poser_1' # Rx UART Data from Interposer_1 via Buffer # # NET 'CPU_UART_Tx__to__Poser_2' # Tx UART Data to Interposer_2 via Buffer # NET 'CPU_UART_Rx_from_Poser_2' # Rx UART Data from Interposer_2 via Buffer # # # # All of these are 3V3 signals: Flash-Now to both Interposers and to AD9546 # Control-Reset to both Interposers # SMUT S1...S4 from only Other Interposer to FPGA # ------------------------------------------------------------------------------------- # # NET 'Flash_Now' # Flash_Now from the FPGA/CPU to both # # Interposers and to the AD9546 for # # time measurement a 3V3 CMOS signal # # NET 'Interposer_Ctrl_Reset' # Control Reset to Both Interposers from FPGA/CPU # # NET 'Muon_S1_Other_Hemi' # Muon SMUT signal S1 from Other Hemisphere to FPGA/CPU # NET 'Muon_S2_Other_Hemi' # Muon SMUT signal S2 from Other Hemisphere to FPGA/CPU # NET 'Muon_S3_Other_Hemi' # Muon SMUT signal S3 from Other Hemisphere to FPGA/CPU # NET 'Muon_S4_Other_Hemi' # Muon SMUT signal S4 from Other Hemisphere to FPGA/CPU # # # Interposer Connectors J4 & J5 All Nets # ------------------------------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 30-Nov-2023 # Current Rev. 14-Dec-2023 # # # # This net list holds the Interposer Connectors J4 & J5 All Nets # ------------------------------------------- # # # # # From Adam's drawing from 20-Oct-2023: 87833-4020 # # # 1 1V8 2 1V8 # 3 3V3 4 3V3 # 5 Gnd 6 Gnd # 7 FLASH_Pulse_p 8 FLASH_Pulse_n # 9 Gnd 10 Gnd # # 11 PIEZO_p 12 PIEZO_n # 13 Gnd 14 Gnd # 15 FLASH_TDC 16 Gnd # 17 Gnd 18 SPI_CLK # 19 CTRL_RST 20 SPI_MISO # # 21 Gnd 22 SPI_MOSI # 23 A0 24 SPI_CS # 25 Gnd 26 Gnd # 27 A2 28 A1 # 29 Gnd 30 Gnd # # 31 UART_Tx 32 UART-Rx # 33 SMUT_S1 34 Gnd # 35 SMUT_S2 36 SMUT_S3 # 37 SMUT_S4 38 Gnd # 39 5V0 40 5V0 # # # SPI Signals to Interposer #1 J4 THIS Hemisphere: # ---------------------------------------------------------------- # NET 'Poser_1_Conn_SCLK' J4-18 # SPI CLK to Interposer #1 Pin 18 NET 'Poser_1_Conn_MOSI' J4-22 # SPI MOSI to Interposer #1 Pin 22 NET 'Poser_1_Conn_MISO' J4-20 # SPI MISO from Interposer #1 Pin 20 NET 'Poser_1_Conn_CS_B' J4-24 # SPI CS_B to Interposer #1 Pin 24 # # Address Signals to Interposer #1 J4 THIS Hemisphere: # ------------------------------------------------------------ # NET 'Poser_1_Conn_CS_A0' J4-23 # CS_A0 to Poser #1 Conn Pin 23 NET 'Poser_1_Conn_CS_A1' J4-28 # CS_A1 to Poser #1 Conn Pin 28 NET 'Poser_1_Conn_CS_A2' J4-27 # CS_A2 to Poser #1 Conn Pin 27 # # SPI Signals to Interposer #2 J5 OTHER Hemisphere: # ----------------------------------------------------------------- # NET 'Poser_2_Conn_SCLK' J5-18 # SPI CLK to Interposer #2 Pin 18 NET 'Poser_2_Conn_MOSI' J5-22 # SPI MOSI to Interposer #2 Pin 22 NET 'Poser_2_Conn_MISO' J5-20 # SPI MISO from Interposer #2 Pin 20 NET 'Poser_2_Conn_CS_B' J5-24 # SPI CS_B to Interposer #2 Pin 24 # # Address Signals to Interposer #2 J5 OTHER Hemisphere: # ------------------------------------------------------------- # NET 'Poser_2_Conn_CS_A0' J5-23 # CS_A0 to Poser #2 Conn Pin 23 NET 'Poser_2_Conn_CS_A1' J5-28 # CS_A1 to Poser #2 Conn Pin 28 NET 'Poser_2_Conn_CS_A2' J5-27 # CS_A2 to Poser #2 Conn Pin 27 # # Piezo Input Signals to BB Audio ADC for Interposer #1 & #2: # ----------------------------------------------------------------- # NET 'Interposer_1_Audio_DIR' J4-11 # Interposer #1 Audio Signal DIR aka PIEZO_p NET 'Interposer_1_Audio_CMP' J4-12 # Interposer #1 Audio Signal CMP aka PIEZO_n NET 'Interposer_2_Audio_DIR' J5-11 # Interposer #2 Audio Signal DIR aka PIEZO_p NET 'Interposer_2_Audio_CMP' J5-12 # Interposer #2 Audio Signal CMP aka PIEZO_n # # GROUND Pins on the Interposer Connectors: # ------------------------------------------- # NET 'GROUND' J4-5 J4-6 J4-9 J4-10 # Grounds on J4 NET 'GROUND' J4-13 J4-14 J4-16 J4-17 # Grounds on J4 NET 'GROUND' J4-21 J4-25 J4-26 J4-29 # Grounds on J4 NET 'GROUND' J4-30 J4-34 J4-38 # Grounds on J4 NET 'GROUND' J5-5 J5-6 J5-9 J5-10 # Grounds on J5 NET 'GROUND' J5-13 J5-14 J5-16 J5-17 # Grounds on J5 NET 'GROUND' J5-21 J5-25 J5-26 J5-29 # Grounds on J5 NET 'GROUND' J5-30 J5-34 J5-38 # Grounds on J5 # # Crystal Oscillators # ----------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 6-Dec-2022 # Current Rev. 12-Dec-2023 # # # This net list holds the Crystal Oscillators # and their connections to the DK FPGA/CPU. # # # The components for the Crystal Oscillators # are in the range 1501 to 1549. # # # Currently (12-Dec-2023) it is assumed that: # # - XTAL #1 will be installed and will be 125 MHz # # - XTAL #1 will provide its signal to both: # - the prefered MSS_REF_CLK_IN P11, R11 in Bank #5 and # - XCVR_0A_REF_CLK_IN pins R23, R24 in the XCVR_0 section # # NOTE: for this double load to work we must be # able to turn OFF the terminator in one of # the two loads. The 100 Ohm terminator in the # XCVR Ref Clock 0A input can be set to open circuit. # # # - XTAL #2 is a spare and will not be installed # # - XTAL #2 is wired to a prefered CCC clock input # in Bank #7 CCC_SW_CLK_IN_W_0 aka # GPIO_167P_B7 / CLKIN_W_0 G5,G4 # # # For Reference: Currently (7-Dec-2023) the other clocks that are # provided to the FPGA/CPU come from the AD9546 # Timing Generator and are: # # Time Gen Output 1A to XCVR_1A_REF_CLK_IN L23, L24 JESD Clock # # Time Gen Output 1B to CCC_SE_CLK_IN_S_9 J14, H14 a Spare Clk # GPIO11PB1/CLKIN_S_9 Bank #1 # # # Crystal Oscillators LVDS Outputs to the FPGA/CPU: # ------------------------------------------------------- # NET 'XTAL_1_Output_Dir' Y1501-4 U1-P11 # XTAL #1 Output Dir to # MSS_REF_CLK_IN_P NET 'XTAL_1_Output_Cmp' Y1501-5 U1-R11 # XTAL #1 Output Cmp to # MSS_REF_CLK_IN_N # XTAL #1 also feeds (but only one can be Terminated): NET 'XTAL_1_Output_Dir' U1-R23 # XTAL #1 Output Dir to # XCVR_0A_REF_CLK_IN_P NET 'XTAL_1_Output_Cmp' U1-R24 # XTAL #1 Output Cmp to # XCVR_0A_REF_CLK_IN_N NET 'XTAL_2_Output_Dir' Y1502-4 U1-G5 # XTAL #2 Output Dir to # GPIO_167P_B7 / CLKIN_W_0 / CCC_SW_CLKIN_W_O NET 'XTAL_2_Output_Cmp' Y1502-5 U1-G4 # XTAL #2 Output Cmp to # GPIO_167N_B7 # # Crystal Oscillator Enable Pins: # ------------------------------------ # NET 'XTAL_1_Enable' Y1501-1 R1501-1 # HI Enable the Xtal #1 Output NET 'XTAL_2_Enable' Y1502-1 R1502-1 # HI Enable the Xtal #2 Output NET 'XTAL_1_3V3' R1501-2 # Pull-Up Source NET 'XTAL_2_3V3' R1502-2 # Pull-Up Source # # 3.3 Volt Power and Grounds to the Crystal Oscillators: # ----------------------------------------------------------- # NET 'BULK_3V3' L1501-1 # Bulk_3V3 Power to Filter NET 'XTAL_1_3V3' L1501-2 # Filtered XTAL #1 3V3 Power NET 'XTAL_1_3V3' C1501-2 C1503-2 # Filtered 3V3 Bypass Caps NET 'GROUND' C1501-1 C1503-1 # Ground Side of Filter Caps NET 'XTAL_1_3V3' Y1501-6 # Filtered 3V3 Power to XTAL #1 NET 'GROUND' Y1501-3 # Ground to XTAL #1 NET 'BULK_3V3' L1502-1 # Bulk_3V3 Power to Filter NET 'XTAL_2_3V3' L1502-2 # Filtered XTAL #2 3V3 Power NET 'XTAL_2_3V3' C1502-2 C1504-2 # Filtered 3V3 Bypass Caps NET 'GROUND' C1502-1 C1504-1 # Ground Side of Filter Caps NET 'XTAL_2_3V3' Y1502-6 # Filtered 3V3 Power to XTAL #2 NET 'GROUND' Y1502-3 # Ground to XTAL #2 # # BARNACLE Interface # ---------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 6-Dec-2022 # Current Rev. 27-Dec-2023 # # # This net list holds the Barnacle Interface # # # The components for the Barnacle Interface # are in the range 1551 to 1599. # # # NOTE: In another net list file the Emergency Rescue # functions use 1 section of the U1551 hex inverter # that is officially part of the Barnacle Interface circuit. # # # Barnacle Interface UART Data Buffers and their FPGA/CPU Connection: # -------------------------------------------------------------------------- # NET 'CPU_UART_2_Tx__to__Barnacle' R1551-1 # DK CPU UART Tx Data to Terminator NET 'Tx_to_Barnacle_Term_Buf' R1551-2 U1551-3 # DK CPU UART Tx Data to Data Buffer NET 'CPU_UART_Tx_to_Barnacle_B' U1551-4 U1551-5 # Inverted NET 'Data_to_Barnacle_Buf_Term' U1551-6 R1552-1 # Tx Data to the DK Tx Terminator NET 'DK_Tx_Data_to_Barnacle' R1552-2 J7-5 # Tx Data to the Barnacle Connector NET 'DK_Rx_Data_from_Barnacle' J7-7 U1551-11 # Rx Data from the Barnacle Connector NET 'DK_Rx_Data_from_Barnacle_B' U1551-10 U1551-9 # Inverted NET 'DK_Rx_Data_to_Terminator' U1551-8 R1553-1 # Rx Data from the Barnacle to Term NET 'CPU_UART_2_Rx_from_Barnacle' R1553-2 # Rx Data from the Barnacle via Buf # and Term to the DK's CPU UART # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are 3V3 signals: Barnacle UART Data # --------------------------------------------------------------------------- # # NET 'CPU_UART_2_Tx__to__Barnacle' # DK CPU UART 2 Tx Data to Barnacle # NET 'CPU_UART_2_Rx_from_Barnacle' # DK CPU UART 2 Rx Data from Barnacle # # # # # Barnacle Interface Master_Reset_B & CONTROL Signals to the Barnacle: # ----------------------------------------------------------------------------- # NET 'Barnacle_Master_Reset_B' J7-3 # Master_Reset_B to the Barnacle NET 'DK_Control_1_to_Barnacle' J7-9 # Control Signal #1 from DK to the Barnacle NET 'DK_Control_2_to_Barnacle' J7-11 # Control Signal #2 from DK to the Barnacle # These 3 Barnacle Control Signals come from the Hardwired # Reset Circuits where they are all forced LOW during Power Up. # # Barnacle Interface Power Feed and Ground Pins: # ----------------------------------------------------- # NET 'BULK_5V0' L1551-2 C1551-2 # Bulk_5V0 Power to Filter NET 'GROUND' C1551-1 # Ground Filter Input Capacitor NET 'BARNACLE_5V0' L1551-1 C1552-2 # Filtered Barnacle 5V0 Power NET 'GROUND' C1552-1 # Ground the Bypass Capacitor NET 'BARNACLE_5V0' J7-1 J7-13 # Filtered 5V0 to the Barnacle Connector NET 'GROUND' J7-2 J7-4 J7-6 # Grounds to the Barnacle Connector NET 'GROUND' J7-8 J7-10 J7-12 NET 'GROUND' J7-14 # # 3.3 Volt Power and Grounds to the UART Data Buffers: # --------------------------------------------------------- # NET 'BULK_3V3' C1553-1 C1554-1 # UART Data Buffer 3V3 Bypass Caps NET 'GROUND' C1553-2 C1554-2 # Ground Side of Bypass Caps NET 'BULK_3V3' U1551-14 # 3V3 Power to UART Data Buffer chip NET 'GROUND' U1551-7 # Ground to UART Data Buffer chip NET 'GROUND' U1551-13 # Tie Down the unused input of the # U1551 hex inverter # # Access Connector J12 # ------------------------- # # and Miscellaneous UART Connections # ------------------------------------ # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 14-Dec-2022 # Current Rev. 18-Dec-2023 # # # This net list holds the connections to the J12 # Access Connector Pins 11:40 and miscellaneous # UART connections. # # # Additional connections to the Access Connector are # made in the net list file: jtag_for_fpga_cpu_nets.txt # # # Additional UART connections are made in the following # net list files: # # barnacle_interface_nets.txt CPU MMUART #2 3V3 # # interposer_all_other_nets.txt CPU MMUART #3 1V8 Interposer #1 # CPU MMUART #4 1V8 Interposer #2 # # rescue_rs485_nets.txt Rescue UART #0 to the RS-485 Cable # Rescue UART #1 to the Access Header # Rescue UART #2 to the FPGA/CPU MMUART #1 # Rescue UART #3 to the TOMCat via LVDS # Rescue UART #4 to the Not Used # # # All of the actual UART connections to the FPGA/CPU are # made in the net list file: # # fpga_cpu_floating_connection_nets.txt # # # The components for the Access Connector # are in the range 1401 to 1449. # # # # Access Connector J12 Pinout # ------------------------------- # # # 1. JTAG_TCLK 2. GROUND # 3. JTAG_TDO 4. NO_Connection # 5. JTAG_TMS 6. JTAG_3V3 # 7. NO_Connection 8. JTAG_TRST # 9. JTAG_TDI 10. GROUND # # 11. GROUND 12. GROUND # 13. CPU MMUART #0 Tx 3V3 14. CPU MMUART #0 Rx 3V3 # 15. GROUND 16. GROUND # 17. Rescue UART #1 Tx 3V3 18. Rescue UART #1 Rx 3V3 # 19. GROUND 20. GROUND # # 21. Access_Signal_1 22. GROUND # 23. Access_Signal_2 24. GROUND # 25. Access_Signal_3 26. GROUND # 27. Access_Signal_4 28. GROUND # 29. Access_Signal_5 30. GROUND # # 31. GROUND 32. GROUND # 33. Diff_Signal_1_Dir 34. Diff_Signal_1_Cmp # 35. GROUND 36. GROUND # 37. Diff_Signal_2_Dir 38. Diff_Signal_2_Cmp # 39. GROUND 40. GROUND # # # # Connect the FPGA/CPU MMUART #1 with the Rescue UART #2 # ----------------------------------------------------------- # # Connect these Tx to Rx via 499 Ohm resistors to help # limit the current flow when one device is powered up # and the other is not yet driving it output banks. # NET 'RESCUE_PIO_0_20_UART_2_Tx' R1411-1 # ER UART 2 Tx Data to NET 'CPU_UART_1_Rx_from_ER_uProc' R1411-2 # FPGA/CPU MMUART 1 Rx NET 'RESCUE_PIO_0_19_UART_2_Rx' R1412-1 # ER UART 2 Rx Data from NET 'CPU_UART_1_Tx__to__ER_uProc' R1412-2 # FPGA/CPU MMUART 1 Tx # # Connect pins 11 through 40 of the J12 Access Connector # -------------------------------------------------------------- # # NET 'GROUND' J12-11 J12-12 NET 'CPU_UART_0_Tx__to__Access' J12-13 # CPU UART 0 Tx Data to Access Connector NET 'CPU_UART_0_Rx_from_Access' J12-14 # CPU UART 0 Rx Data from Access Connector NET 'GROUND' J12-15 J12-16 NET 'RESCUE_PIO_0_7_UART_1_Tx' J12-17 # ER UART 1 Tx Data to Header Pin NET 'RESCUE_PIO_0_6_UART_1_Rx' J12-18 # ER UART 1 Rx Data from Header Pin NET 'GROUND' J12-19 J12-20 NET 'Access_Signal_1' J12-21 # Access Connector FPGA Signal #1 NET 'GROUND' J12-22 NET 'Access_Signal_2' J12-23 # Access Connector FPGA Signal #2 NET 'GROUND' J12-24 NET 'Access_Signal_3' J12-25 # Access Connector FPGA Signal #3 NET 'GROUND' J12-26 NET 'Access_Signal_4' J12-27 # Access Connector FPGA Signal #4 NET 'GROUND' J12-28 NET 'Access_Signal_5' J12-29 # Access Connector FPGA Signal #5 NET 'GROUND' J12-30 NET 'GROUND' J12-31 J12-32 NET 'Access_Diff_Pair_1_Dir' J12-33 # Access Connector FPGA Differential Pair #1 DIR NET 'Access_Diff_Pair_1_Cmp' J12-34 # Access Connector FPGA Differential Pair #1 CMP NET 'GROUND' J12-35 J12-36 NET 'Access_Diff_Pair_2_Dir' J12-37 # Access Connector FPGA Differential Pair #2 DIR NET 'Access_Diff_Pair_2_Cmp' J12-38 # Access Connector FPGA Differential Pair #2 CMP NET 'GROUND' J12-39 J12-40 # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # These are 3V3 signals: CPU MMUART #0 Data to/from Access Connector # ------------------------------------------------------------------------ # # NET 'CPU_UART_0_Tx__to__Access' # CPU UART 0 Tx Data to Access Connector # NET 'CPU_UART_0_Rx_from_Access' # CPU UART 0 Rx Data from Access Connector # # # These are 3V3 signals: CPU MMUART #1 Data to/from Emergency Rescue uProcessor # ----------------------------------------------------------------------------------- # # NET 'CPU_UART_1_Tx__to__ER_uProc' # CPU UART 1 Tx Data to Emergency Rescue uProc # NET 'CPU_UART_1_Rx_from_ER_uProc' # CPU UART 1 Rx Data from Emergency Rescue uProc # # # # These are 3V3 signals: FPGA/CPU <--> Access Connector Single Ended Signals # --------------------------------------------------------------------------------- # # NET 'Access_Signal_1' # Access Connector FPGA Signal #1 # NET 'Access_Signal_2' # Access Connector FPGA Signal #2 # NET 'Access_Signal_3' # Access Connector FPGA Signal #3 # NET 'Access_Signal_4' # Access Connector FPGA Signal #4 # NET 'Access_Signal_5' # Access Connector FPGA Signal #5 # # # # Both of these are Differential signals, e.g. LVDS: # # FPGA/CPU <--> Access Connector Differential Pairs # ---------------------------------------------------------------------------------------- # # NET 'Access_Diff_Pair_1_Dir' # Access Connector FPGA Differential Pair #1 DIR # NET 'Access_Diff_Pair_1_Cmp' # Access Connector FPGA Differential Pair #1 CMP # # NET 'Access_Diff_Pair_2_Dir' # Access Connector FPGA Differential Pair #2 DIR # NET 'Access_Diff_Pair_2_Cmp' # Access Connector FPGA Differential Pair #2 CMP # # # Startup and Reset Nets # --------------------------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 15-Dec-2022 # Current Rev. 4-Jan-2024 # # # This net list holds the Startup and Reset # nets. # # The components in the Startup and Reset # section of the design have reference # designators in the range 1151 :1199 # # NOTE: below the use of one section in the U1402 hex inverter # to handle inverting the DK_CPU_Is_Awake_B signal. # U1402 officially belongs to the DK FPGA/CPU JTAG # circuits and appears in that net list file. # # NOTES: The Startup and Resets ICs U1151 through U1155 are # powered by the "always ON" CNST_3V3 supply where as # the associated Pull-Up resistors R1171 & R1172 are # powered by BULK_3V3 because there is no need or # desire for the signals pulled up by these resistors # to be in the HI state before the BULK_3V3 has # finished its ramp up. # # U1156 and the Pull-Up Resistor R1177 are powered by # the BULK_5V0 supply because this circuit must supply # a glitch free Master_Reset_B to the Barnacle Interface # as the BULK_5V0 supply ramps up. # # Two section of the U1602 Quad NAND (which is officially # part of the SFP control circuits) are used by the # Startup and Reset circuits that are described below. # U1602 4,5,6 is used to make the DK_CPU_Is_Sane_B # signal that is used by the Emergency Rescue circuits # and U1602 8,9,10 is used to make a Spare Run signal. # # # Startup Delay TPS3808s U1151 - Senses the Bulk_5V0 and # --------------- Makes the DCDC Converter "Track Bus": # ----------------------------------------------------------------------------- # NET 'BULK_5V0' R1161-1 # Bulk 5V0 to the Sense Resistor Divider NET 'Start_Delay_Sense' R1161-2 R1162-1 # Sense Input to the Startup Delay NET 'Start_Delay_Sense' U1151-5 C1161-1 # Sense Input to the Startup Delay NET 'GROUND' R1162-2 C1161-2 # Ground Volt Divider and Filter Cap NET 'Start_Delay_Cap_T' U1151-4 C1162-1 # Start Delay Timing Cap NET 'GROUND' C1162-2 # Ground Timing Cap NET 'NO_CONN_U1151_Pin_3' U1151-3 # Un-Used Start Delay MR_B pin NET 'DCDC_Conv_Track' U1151-1 # Start Delay Reset_B pin # "Track Bus" to the 7 DCDC converters # # All Power Good TPS3808s U1152 - Senses the Bulk_3V3 and # ---------------- Makes the Delayed_All_Power_Good signal: # ----------------------------------------------------------------------------------- # NET 'BULK_3V3' R1163-1 # Bulk 3V3 to the Sense Resistor Divider NET 'All_Good_Delay_Sense' R1163-2 R1164-1 # Sense Input to the All_Power_Good Delay NET 'All_Good_Delay_Sense' U1152-5 C1163-1 # Sense Input to the All_Power_Good Delay NET 'GROUND' R1164-2 C1163-2 # Ground Volt Divider and Filter Cap NET 'All_Good_Delay_Cap_T' U1152-4 C1164-1 # All_Power_Good Delay Timing Cap NET 'GROUND' C1164-2 # Ground Timing Cap NET 'NO_CONN_U1152_Pin_3' U1152-3 # Un-Used All Power Good MR_B pin NET 'Delayed_All_Power_Good' U1152-1 # All Power Good Delay Reset_B pin # Delayed_All_Power_Good to the Reset Circuits # # Make the "CPU IS SANE" and "FPGA/CPU_Reset_B" signals: # -------------------------------------------------------------- # # NOTE: the use of one section in the U1402 hex inverter # to handle inverting the DK_CPU_Is_Awake_B signal. # U1402 officially belongs to the DK FPGA/CPU JTAG # circuits and appears in that net list file. # # The DK_CPU_Is_Sane signal is made below by U1153 # and DK_CPU_Is_Sane_B is made in the SFP net list file # by U1602. # NET 'Delayed_All_Power_Good' R1171-1 U1153-5 U1155-1 # Pull-Up on Delayed All Power Good NET 'BULK_3V3' R1171-2 # 3V3 Pull-Up Source NET 'FPGA_CPU_RESET_B' R1172-1 U1-H9 U1155-2 # Reset to the FPGA/CPU NET 'BULK_3V3' R1172-2 # 3V3 Pull-Up Source NET 'DK_CPU_Is_Awake' R1173-1 U1153-2 # CPU is Awake & its Pull-Down NET 'GROUND' R1173-2 # Pull-Down Anchor NET 'DK_CPU_Is_Awake_B' R1174-1 U1402-1 # CPU is Awake_B to Inverter & Pull-Up NET 'CNST_3V3' R1174-2 # 3V3 Pull-Up Source NET 'DK_CPU_Is_Awake_B_INV' U1402-2 U1153-1 # Inverted Awake_B to AND NET 'DK_CPU_Awake_AND_B' U1153-3 U1153-4 # Awake & _B to AND with Delayed All Good NET 'DK_CPU_Is_Sane' R1178-1 U1153-6 # DK_CPU_Is_Sane for Distribution NET 'GROUND' R1178-2 # Pull-Down on DK_CPU_Is_Sane with 4.7k # so that it is defined even before the # CNST_3V3 supply is fully ramped up. # In this way the Barnacle_Master_Reset_B # is defined Low while the BULK_5V0 ramps. # # Make the PMT_ADC_Reset_B this is a 1V8 Low Active signal: # ------------------------------------------------------------------ NET 'Run_PMT_ADC' U1153-9 # Run_PMT_ADC signal from CPU NET 'DK_CPU_Is_Sane' U1153-10 # AND with DK_CPU_Is_Sane NET 'DK_Sane__Run_PMT' U1153-8 U1155-3 # AND of Sane and Run_PMT NET 'PMT_ADC_Reset_B' U1155-4 R1175-1 # PMT_ADC_Reset_B signal NET 'BULK_1V8' R1175-2 # Pull-Up 1V8 Source # # Make the BB_Audio_ADC_Reset_B this is a 1V8 Low Active signal: # ----------------------------------------------------------------------- NET 'Run_BB_Audio_ADC' U1153-13 # Run_BB_Audio_ADC signal from CPU NET 'DK_CPU_Is_Sane' U1153-12 # AND with DK_CPU_Is_Sane NET 'DK_Sane__Run_BB_ADC' U1153-11 U1155-5 # AND of Sane and Run_BB_Audio_ADC NET 'BB_Audio_ADC_Reset_B' U1155-6 R1176-1 # BB_Audio_ADC_Reset_B signal NET 'BULK_1V8' R1176-2 # Pull-Up 1V8 Source # # Make the Clock_Generator_Reset_B this is a 3V3 Low Active signal: # -------------------------------------------------------------------------- NET 'Run_Clock_Generator' U1154-5 # Run_BB_Audio_ADC signal from CPU NET 'DK_CPU_Is_Sane' U1154-4 # AND with DK_CPU_Is_Sane NET 'Clock_Gen_Reset_B' U1154-6 # Clock_Gen_Reset_B signal # # Make the USB_Reset_B this is a 3V3 Low Active signal: # -------------------------------------------------------------- NET 'Run_USB_Interface' U1154-1 # Run_USB_Interface signal from CPU NET 'DK_CPU_Is_Sane' U1154-2 # AND with DK_CPU_Is_Sane NET 'USB_Reset_B' U1154-3 # USB_Reset_B signal # # Make a SPARE_Reset signal this is a 3V3 Hi Active signal: # # This Run Spare circuit uses U1602 which is officially # part of the SFP control circuits. In the SFP control # circuit net list file the DK_CPU_Is_Sane signal is # connected to pin U1602-10. # ------------------------------------------------------------------ NET 'Run_SPARE' U1602-9 # Run_Spare signal from CPU NET 'SPARE_Reset' U1602-8 # SPARE_Reset signal 3V3 Hi Active # Currently this Reset signal is not used. # # Make the Barnacle_Control_ 1 and 2 signals # # They are Open-Drain Outputs with Pull-Up Resistors on the Barnacle: # ----------------------------------------------------------------------- NET 'Barnacle_Control_1' U1154-13 # Barnacle_Control_1 signal from CPU NET 'DK_CPU_Is_Sane' U1154-12 # AND with DK_CPU_Is_Sane NET 'DK_Sane__Barn_Ctrl_1' U1154-11 U1155-13 # AND of Sane and Barn_Ctrl_1 NET 'DK_Control_1_to_Barnacle' U1155-12 # Control_1 signal to the Barnacle NET 'Barnacle_Control_2' U1154-9 # Barnacle_Control_2 signal from CPU NET 'DK_CPU_Is_Sane' U1154-10 # AND with DK_CPU_Is_Sane NET 'DK_Sane__Barn_Ctrl_2' U1154-8 U1155-11 # AND of Sane and Barn_Ctrl_2 NET 'DK_Control_2_to_Barnacle' U1155-10 # Control_2 signal to the Barnacle # # Make the Barnacle_Master_Reset_B signal # # This is an Open-Drain Output with its Pull-Up Resistor on the Barnacle: # Limit the Pull-Up current on the Barnacle to 500 uAmps # --------------------------------------------------------------------------- # NET 'DK_CPU_Is_Sane' R1165-1 # DK_CPU_Is_Sane CMOS Logic signal # input to voltage divider that NET 'Barn_Sense_Pin' R1165-2 R1166-1 # feeds the Sense pin on the NET 'Barn_Sense_Pin' C1165-1 U1156-5 # Barnacle_Master_Reset_B TPS3808 NET 'GROUND' C1165-2 R1166-2 # Ground low side divider and fltr cap NET 'Run_Barnacle' U1155-9 # Run_Barnacle 3V3 signal from the FPGA/CPU # input to the O.D. Buffer for conversion NET 'Run_Barn_5V' U1155-8 R1177-1 # to a 5V logic signal to feed the MR_B NET 'Run_Barn_5V' U1156-3 # input on the Barn_Master_Reset_B TPS3808 NET 'Bulk_5V0' R1177-2 # Pull-Up Source to Bulk_5V0 NET 'NO_CONN_Barnacle_U1156_pin_4' U1156-4 # Open TPS3808 Timing Pin ---> 20 msec. NET 'Barnacle_Master_Reset_B' U1156-1 # Master_Reset_B to the Barnacle # # Power and Ground to the ICs and their Bypass Caps: # ------------------------------------------------------- # NET 'CNST_3V3' U1151-6 U1152-6 # CNST_3V3 to the two Startup TPS3808s NET 'GROUND' U1151-2 U1152-2 # and their Ground NET 'CNST_3V3' U1153-14 U1154-14 U1155-14 # CNST_3V3 to the three Reset ICs NET 'GROUND' U1153-7 U1154-7 U1155-7 # and their Ground NET 'CNST_3V3' C1151-1 C1152-1 C1153-1 # CNST_3V3 to Bypass Caps NET 'GROUND' C1151-2 C1152-2 C1153-2 # and the Bypass Grounds NET 'CNST_3V3' C1154-1 C1155-1 # CNST_3V3 to Bypass Caps NET 'GROUND' C1154-2 C1155-2 # and the Bypass Grounds NET 'BULK_5V0' U1156-6 # 5V0 to the Barnacle Reset TPS3808 NET 'GROUND' U1156-2 # and its Ground NET 'BULK_5V0' C1156-1 # 5V0 to a Bypass Cap NET 'GROUND' C1156-2 # and that Bypass Ground # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # These are 3V3 signals: DK_CPU_Is_Awake (_B) and the RUN signals # ----------------------------------------------------------------------- # # NET 'DK_CPU_Is_Awake' # CPU is Awake signal # NET 'DK_CPU_Is_Awake_B' # CPU is Awake_B signal # # NET 'Run_PMT_ADC' # LOW ---> Reset the AD9083 PMT ADC # NET 'Run_Clock_Generator' # LOW ---> Reset the AD9546 Clock Generator # NET 'Run_USB_Interface' # LOW ---> Reset the USB3340 USB Transceiver # NET 'Run_BB_Audio_ADC' # LOW ---> Reset the TLV320ADC6140 BB Audio ADC # NET 'Run_SPARE' # Currently 26-Dec-2023 this signal is not used # # NET 'Run_Barnacle' # LOW ---> Barnacle Power Down and Master_Reset_B # NET 'Barnacle_Control_1' # Barnacle Control Signal 1 default is Low # NET 'Barnacle_Control_2' # Barnacle Control Signal 2 default is Low # # # Disco-Kraken Key In Net List # ------------------------------- # # # Floating Pin Connections to FPGA/CPU # -==============------------------------- # # # # Initial Rev. 4-Dec-2023 # Current Rev. 27-Dec-2023 # # # # This netlist holds just the FPGA/CPU end of nets that connect # to "floating" pins on this component, i.e. to pins that are # fixed to a given pin number only by the design put into the # FPGA/CPU. # # Function specific pins, e.g. Bank #3, DDR4 Memory, High-Speed # Serial Links, are all assigned in the Net List file that # describes that particular function on the DK board. # # This Net List file is only for the FPGA/CPU end of these # "floating" connections. All of these floating connections # are either to: Bank #9 for 1V8 I/O or to Banks #1 & #7 # for 3V3 I/O. Most of these floating conections go to CPU # peripherals or to normal FPGA I/O signals. # # For reference the pins in Banks 1, 7, and 9 are listed at # the end of this file. # # The intent of this Net List file is to collect in one place all # of the floating pin connections to the FPGA/CPU so that it is # easier to coordinate these pin numbers with the firmware/software # work on this part. # # The Net List files that describe the functions that are assigned # to floating pins on the FPGA/CPU all included a note to remind # folks that the final step in these floating FPGA/CPU conections # is in this file. # # This file is devided into a number of sections - one section for # each DK board function that connects to the FPGA/CPU via Floating # Pin Assignments. # # #--------------------------------------------------------------------- # # 26-Dec-2023 Currently there are 72 Floating pin nets # Start by randomly assigning them to random pins. # Assign into the correct voltage bank and # for now into the first 3 rings. # # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # Access Connector and UART to ER uProc Connections with the FPGA/CPU 13 Pins # --------------------------------------------------------------------------------------- # # # These are 3V3 signals: CPU MMUART #0 Data to/from Access Connector # ------------------------------------------------------------------------ NET 'CPU_UART_0_Tx__to__Access' U1-B4 # CPU UART 0 Tx Data to Access Conn. GPIO177PB1/CCC_SW_PLL0_OUT0 NET 'CPU_UART_0_Rx_from_Access' U1-A4 # CPU UART 0 Rx Data from Access Conn. GPIO177NB1 # # These are 3V3 signals: CPU MMUART #1 Data to/from Emergency Rescue uProcessor # ----------------------------------------------------------------------------------- NET 'CPU_UART_1_Tx__to__ER_uProc' U1-D4 # CPU UART 1 Tx Data to ER uProc GPIO176PB1/DQS/CCC_SW_PLL0_OUT0 NET 'CPU_UART_1_Rx_from_ER_uProc' U1-C4 # CPU UART 1 Rx Data from ER uProc GPIO176NB1/DQS # # # These are 3V3 signals: FPGA/CPU <--> Access Connector Single Ended Signals # ---------------------------------------------------------------------------------------- NET 'Access_Signal_1' U1-C1 # Access Conn. FPGA Signal #1 GPIO172PB1/CCC_SW_PLL1_OUT1 NET 'Access_Signal_2' U1-B1 # Access Conn. FPGA Signal #2 GPIO172NB1 NET 'Access_Signal_3' U1-C2 # Access Conn. FPGA Signal #3 GPIO168PB1/CCC_SW_CLKIN_S_0 NET 'Access_Signal_4' U1-B2 # Access Conn. FPGA Signal #4 GPIO168NB1 NET 'Access_Signal_5' U1-A2 # Access Conn. FPGA Signal #5 GPIO173PB1/CLKIN_S_3/ # CCC_SW_CLKIN_S_3 # # Both of these are Differential signals, e.g. LVDS: # # FPGA/CPU <--> Access Connector Differential Pairs # ---------------------------------------------------------------------------------------- NET 'Access_Diff_Pair_1_Dir' U1-E1 # Access Conn. Diff Pair #1 DIR GPIO170PB1/DQS/CCC_SW_PLL1_OUT0 NET 'Access_Diff_Pair_1_Cmp' U1-D1 # Access Conn. Diff Pair #1 CMP GPIO170NB1/DQS NET 'Access_Diff_Pair_2_Dir' U1-D3 # Access Conn. Diff Pair #2 DIR GPIO171PB1/ # CLKIN_S_2/CCC_SW_CLKIN_S_2/ # CCC_SW_PLL1_OUT0 NET 'Access_Diff_Pair_2_Cmp' U1-C3 # Access Conn. Diff Pair #2 CMP GPIO171NB1 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # BARNACLE to/from CPU MMUART #2 Data Connections 2 Pins # ------------------------------------------------------------------- # # # These are 3V3 signals: Barnacle UART Data # CPU MMUART #2 # ---------------------------------------------- NET 'CPU_UART_2_Tx__to__Barnacle' U1-E3 # DK CPU UART 2 Tx Data to Barnacle GPIO169PB1/ # CCC_SW_CLKIN_S_1 NET 'CPU_UART_2_Rx_from_Barnacle' U1-E2 # DK CPU UART 2 Rx Data from Barnacle GPIO169NB1 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # BB Audio ADC Clock and Readout Data Connections with the FPGA/CPU 4 Pins # --------------------------------------------------------------------------------- # # # These are 1V8 signals: BB Audio ADC Readout Signals # ------------------------------------------------------- NET 'FPGA_BB_ADC_CLK_Out' U1-A27 # FPGA Output BB Audio ADC CLK GPIO57PB9/ # CLKIN_S_12/ # CCC_SE_CLKIN_S_12/ # CCC_SE_PLL0_OUT0 NET 'FPGA_BB_ADC_SDATA_IN' U1-A22 # FPGA Input BB ADC SData Input GPIO50PB9/DQS NET 'FPGA_BB_ADC_BCLK_IN' U1-A23 # FPGA Input BB ADC BCLK Input GPIO50NB9/DQS NET 'FPGA_BB_ADC_FSYNC_IN' U1-A24 # FPGA Input BB ADC FSYNC Input GPIO53PB9 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # Environmental Sensor I2C Bus Connections with the FPGA/CPU 2 Pins # -------------------------------------------------------------------------- # # # These are 1V8 signals: Env Sesnsor and BB Audio I2C Bus # CPU I2C Controller #1 # ----------------------------------------------------------- NET 'I2C_DATA_SENSOR_BB_ADC' U1-B20 # Sensor & BB ADC I2C Bus Data GPIO47PB9 NET 'I2C_SCLK_SENSOR_BB_ADC' U1-A20 # Sensor & BB ADC I2C Bus Clock GPIO47NB9 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # Interposer 1 and 2 Connections to the FPGA/CPU via Floating Pins 18 Pins # --------------------------------------------------------------------------------- # # # These are 3V3 signals: SPI Bus and GPIO Used with the Interposer SPI Bus # from CPU SPI Controller #1 and 5 GPIO signals # ------------------------------------------------------------------------------ NET 'Poser_SCLK_FPGA_to_Term' U1-B6 # SCLK FPGA to Interposers GPIO175NB1 NET 'Poser_MOSI_FPGA_to_Term' U1-B5 # MOSI FPGA to Interposers GPIO179PB1 NET 'Poser_MISO_Term_to_FPGA' U1-A5 # MISO Mux Term to FPGA GPIO179NB1 NET 'Poser_CS_1_B' U1-B7 # FPGA Signal to Enable Interposer #1 Mux _B GPIO1PB1/CLKIN_S_5 NET 'Poser_CS_2_B' U1-A7 # FPGA Signal to Enable Interposer #2 Mux _B GPIO1NB1 NET 'Poser_CS_Adrs_0' U1-C8 # CS Address 0 FPGA to Mux GPIO2PB1/DQS NET 'Poser_CS_Adrs_1' U1-C7 # CS Address 1 FPGA to Mux GPIO2NB1/DQS NET 'Poser_CS_Adrs_2' U1-A8 # CS Address 2 FPGA to Mux GPIO3PB1/CLKIN_S_6 # # These are 1V8 signals: CPU UART Data to/from both Interposers --> PMT Bases # CPU MMUART #3 <--> Interposer #1 "This Hemisphere" # CPU MMUART #4 <--> Interposer #2 "Other Hemisphere" # --------------------------------------------------------------------------------- NET 'CPU_UART_3_Tx__to__Poser_1' U1-A17 # Tx UART 3 Data to Interposer_1 via Buffer GPIO43PB9 NET 'CPU_UART_3_Rx_from_Poser_1' U1-A18 # Rx UART 3 Data from Interposer_1 via Buffer GPIO43NB9 NET 'CPU_UART_4_Tx__to__Poser_2' U1-B19 # Tx UART 4 Data to Interposer_2 via Buffer GPIO45PB9 NET 'CPU_UART_4_Rx_from_Poser_2' U1-A19 # Rx UART 4 Data from Interposer_2 via Buffer GPIO45NB9 # # All of these are 3V3 signals: Flash-Now to both Interposers and to AD9546 # Control-Reset to both Interposers # SMUT S1...S4 from Other Interposer to FPGA # ------------------------------------------------------------------------------------- NET 'Flash_Now' U1-A9 # Flash_Now from the FPGA/CPU to both GPIO3NB1 # Interposers and to the AD9546 for # time measurement a 3V3 CMOS signal NET 'Interposer_Ctrl_Reset' U1-C9 # Control Reset to Both Interposers from FPGA GPIO4PB1/LPRB_A NET 'Muon_S1_Other_Hemi' U1-B9 # Muon SMUT signal S1 from Other Hemisphere to FPGA GPIO4NB1/LPRB_B NET 'Muon_S2_Other_Hemi' U1-B10 # Muon SMUT signal S2 from Other Hemisphere to FPGA GPIO5PB1/CLKIN_S_7 NET 'Muon_S3_Other_Hemi' U1-A10 # Muon SMUT signal S3 from Other Hemisphere to FPGA GPIO5NB1 NET 'Muon_S4_Other_Hemi' U1-B11 # Muon SMUT signal S4 from Other Hemisphere to FPGA GPIO13NB1 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # PMT ADC Connections with the FPGA/CPU 7 Pins # ------------------------------------------------------- # # # These are 1V8 SPI signals: PMT ADC SPI Bus (private) # CPU SPI Bus Controller #0 # and 4W to 3W Converter # ------------------------------------------------------------ NET 'PMT_ADC_CHIP_SELECT_B' U1-B21 # ADC SPI Chip Select Active LOW GPIO49PB9 NET 'PMT_ADC_SPI_CLOCK' U1-C21 # ADC SPI Clock GPIO49NB9 NET 'PMT_ADC_SPI_DATA_IO' U1-B22 # ADC SPI Data I/O GPIO52PB9 # # These are LVDS signals: PMT ADC Clock Type Signals # I think this should be 1V8 LVDS # ------------------------------------------------------------ NET 'PMT_ADC_SYNC_ENB_B_DIR' U1-B24 # ADC JESD204B Sync Enb B DIR GPIO54PB9 NET 'PMT_ADC_SYNC_ENB_B_CMP' U1-C24 # ADC JESD204B Sync Enb B CMP GPIO54NB9 NET 'PMT_ADC_Trigger_DIR' U1-B25 # ADC Trigger Dir Input GPIO55PB9 NET 'PMT_ADC_Trigger_CMP' U1-B26 # ADC Trigger Cmp Input GPIO55NB9 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # SFP Module and I2C Controller #0 Connections with the FPGA/CPU 15 Pins # -------------------------------------------------------------------------------- # # # These are 3V3 signals: SFP Module Control and Monitor Signals # ----------------------------------------------------------------- NET 'SFP_Time_TX_Fault' U1-C14 # Time SFP Tx Fault to FPGA/CPU GPIO Input GPIO15PB1/ # CCC_SE_CLKIN_S_10 NET 'SFP_Time_MOD_ABS' U1-B12 # Time SFP Module Absent to FPGA/CPU GPIO Input GPIO13PB1 NET 'SFP_Time_RX_LOS' U1-C13 # Time SFP Rx Signal Loss to FPGA/CPU GPIO Input GPIO14PB1/DQS NET 'SFP_Time_Trans_Enable' U1-C12 # Time SFP Tx Enable from FPGA/CPU GPIO Output GPIO14NB1/DQS NET 'SFP_Time_RS_0' U1-D11 # Time SFP Rate Select 0 <--> FPGA/CPU GPIO I/O GPIO16PB1 NET 'SFP_Time_RS_1' U1-C11 # Time SFP Rate Select 1 <--> FPGA/CPU GPIO I/O GPIO16NB1 NET 'SFP_ENet_TX_Fault' U1-D9 # ENet SFP Tx Fault to FPGA/CPU GPIO Input GPIO0PB1/CLKIN_S_4 NET 'SFP_ENet_MOD_ABS' U1-D10 # ENet SFP Module Absent to FPGA/CPU GPIO Input GPIO0NB1 NET 'SFP_ENet_RX_LOS' U1-E12 # ENet SFP Rx Signal Loss to FPGA/CPU GPIO Input GPIO6NB1 NET 'SFP_ENet_Trans_Enable' U1-E13 # ENET SFP Tx Enable from FPGA/CPU GPIO Output GPIO7NB1 NET 'SFP_ENet_RS_0' U1-D14 # Time SFP Rate Select 0 <--> FPGA/CPU GPIO I/O GPIO8PB1/DQS NET 'SFP_ENet_RS_1' U1-D13 # Time SFP Rate Select 1 <--> FPGA/CPU GPIO I/O GPIO8NB1/DQS # # These are 3V3 signals: I2C Bus for both SFP Modules and for Timing Generator # CPU I2C Controller #0 Serial Clk & Data # -------------------------------------------------------------------------------- NET 'CPU_I2C_Ctrl_0_SCL' U1-A12 # FPGA/CPU Controller 0 I2C SCLK to Fan-Out GPIO17PB1/ # CCC_SE_CLKIN_S_11 NET 'CPU_I2C_Ctrl_0_SDA' U1-A13 # FPGA/CPU Controller 0 I2C SDATA to Fan-Out GPIO17NB1 NET 'CPU_I2C_Ctrl_0_Fan_Out_RESET_B' U1-B14 # I2C Fanout Reset_B from FPGA/CPU GPIO GPIO15NB1 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # Startup and Resets Controller Connections with the FPGA/CPU 10 Pins # ----------------------------------------------------------------------------- # # # These are 3V3 signals: DK_CPU_Is_Awake (_B) and the RUN signals # ----------------------------------------------------------------------- NET 'DK_CPU_Is_Awake' U1-A3 # CPU is Awake signal GPIO173NB1 NET 'DK_CPU_Is_Awake_B' U1-C6 # CPU is Awake_B signal GPIO175PB1 NET 'Run_PMT_ADC' U1-D5 # LOW ---> Reset the AD9083 PMT ADC GPIO178NB1 NET 'Run_Clock_Generator' U1-E5 # LOW ---> Reset the AD9546 Clock Generator GPIO174PB1 NET 'Run_USB_Interface' U1-E6 # LOW ---> Reset the USB3340 USB Transceiver GPIO182NB1/DQS NET 'Run_BB_Audio_ADC' U1-E7 # LOW ---> Reset the TLV320ADC6140 BB Audio ADC GPIO182PB1/DQS NET 'Run_SPARE' U1-D8 # Currently 26-Dec-2023 this signal is not used GPIO185NB1 NET 'Run_Barnacle' U1-E8 # LOW ---> Barnacle Power Down & Master_Reset_B GPIO185PB1 NET 'Barnacle_Control_1' U1-E10 # Barnacle Control Signal 1 default is Low GPIO12NB1 NET 'Barnacle_Control_2' U1-E11 # Barnacle Control Signal 2 default is Low GPIO12PB1 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # USB Phy Reference Clock Connections with the FPGA/CPU 1 Pin # ------------------------------------------------------------------- # # # These are 3V3 signals: USB Phy Ref Clk 26 MHz # from a FPGA/CPU CCC Clock Output # ------------------------------------------------------------ NET 'FPGA_Ref_Clk_to_USB_Phy' U1-D6 # FPGA Clk Output to USB Phy Ref Clk Input GPIO178PB1/ # CCC_SW_PLL0_OUT1 # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- #--------------------------------------------------------------------- #--------------------------------------------------------------------- # # # Reference Data MPFS250T-1FCVG784I Banks: 1, 7, 9 # --------------------------------------------------------- # # # FPGA Bank 1 # ------------------- # # There are 72 pins in Bank 1 This is a 3V3 Bank on the DK. # # Bank 1 pins are located in two groups on the FCVG784 package. # # # D9 GPIO0PB1/CLKIN_S_4 DDR_S_3 I/O GPIO # D10 GPIO0NB1 DDR_S_3 I/O GPIO # # B7 GPIO1PB1/CLKIN_S_5 DDR_S_3 I/O GPIO # A7 GPIO1NB1 DDR_S_3 I/O GPIO # # C8 GPIO2PB1/DQS DDR_S_3 I/O GPIO # C7 GPIO2NB1/DQS DDR_S_3 I/O GPIO # # A8 GPIO3PB1/CLKIN_S_6 DDR_S_3 I/O GPIO # A9 GPIO3NB1 DDR_S_3 I/O GPIO # # C9 GPIO4PB1/LPRB_A DDR_S_3 I/O GPIO # B9 GPIO4NB1/LPRB_B DDR_S_3 I/O GPIO # # B10 GPIO5PB1/CLKIN_S_7 DDR_S_3 I/O GPIO # A10 GPIO5NB1 DDR_S_3 I/O GPIO # # F12 GPIO6PB1 DDR_S_4 I/O GPIO # E12 GPIO6NB1 DDR_S_4 I/O GPIO # # F13 GPIO7PB1 DDR_S_4 I/O GPIO # E13 GPIO7NB1 DDR_S_4 I/O GPIO # # D14 GPIO8PB1/DQS DDR_S_4 I/O GPIO # D13 GPIO8NB1/DQS DDR_S_4 I/O GPIO # # G12 GPIO9PB1/CLKIN_S_8/ # CCC_SE_CLKIN_S_8 DDR_S_4 I/O GPIO # G11 GPIO9NB1 DDR_S_4 I/O GPIO # # F14 GPIO10PB1 DDR_S_4 I/O GPIO # G14 GPIO10NB1 DDR_S_4 I/O GPIO # # J14 GPIO11PB1/CLKIN_S_9/ # CCC_SE_CLKIN_S_9 DDR_S_4 I/O GPIO # H14 GPIO11NB1 DDR_S_4 I/O GPIO # # E11 GPIO12PB1 DDR_S_5 I/O GPIO # E10 GPIO12NB1 DDR_S_5 I/O GPIO # # B12 GPIO13PB1 DDR_S_5 I/O GPIO # B11 GPIO13NB1 DDR_S_5 I/O GPIO # # C13 GPIO14PB1/DQS DDR_S_5 I/O GPIO # C12 GPIO14NB1/DQS DDR_S_5 I/O GPIO # # C14 GPIO15PB1/ # CCC_SE_CLKIN_S_10 DDR_S_5 I/O GPIO # B14 GPIO15NB1 DDR_S_5 I/O GPIO # # D11 GPIO16PB1 DDR_S_5 I/O GPIO # C11 GPIO16NB1 DDR_S_5 I/O GPIO # # A12 GPIO17PB1/ # CCC_SE_CLKIN_S_11 DDR_S_5 I/O GPIO # A13 GPIO17NB1 DDR_S_5 I/O GPIO # # # # # C2 GPIO168PB1/CCC_SW_CLKIN_S_0 DDR_S_0 1 I/O GPIO # B2 GPIO168NB1 DDR_S_0 1 I/O GPIO # # E3 GPIO169PB1/CCC_SW_CLKIN_S_1 DDR_S_0 1 I/O GPIO # E2 GPIO169NB1 DDR_S_0 1 I/O GPIO # # E1 GPIO170PB1/DQS/CCC_SW_PLL1_OUT0 DDR_S_0 1 I/O GPIO # D1 GPIO170NB1/DQS DDR_S_0 1 I/O GPIO # # D3 GPIO171PB1/ DDR_S_0 1 I/O GPIO # CLKIN_S_2/CCC_SW_CLKIN_S_2/ # CCC_SW_PLL1_OUT0 # C3 GPIO171NB1 DDR_S_0 1 I/O GPIO # # C1 GPIO172PB1/CCC_SW_PLL1_OUT1 DDR_S_0 1 I/O GPIO # B1 GPIO172NB1 DDR_S_0 1 I/O GPIO # # A2 GPIO173PB1/CLKIN_S_3/ DDR_S_0 1 I/O GPIO # CCC_SW_CLKIN_S_3 # A3 GPIO173NB1 DDR_S_0 1 I/O GPIO # # E5 GPIO174PB1 DDR_S_1 1 I/O GPIO # F5 GPIO174NB1 DDR_S_1 1 I/O GPIO # # C6 GPIO175PB1 DDR_S_1 1 I/O GPIO # B6 GPIO175NB1 DDR_S_1 1 I/O GPIO # # D4 GPIO176PB1/DQS/CCC_SW_PLL0_OUT0 DDR_S_1 1 I/O GPIO # C4 GPIO176NB1/DQS DDR_S_1 1 I/O GPIO # # B4 GPIO177PB1/CCC_SW_PLL0_OUT0 DDR_S_1 1 I/O GPIO # A4 GPIO177NB1 DDR_S_1 1 I/O GPIO # # D6 GPIO178PB1/CCC_SW_PLL0_OUT1 DDR_S_1 1 I/O GPIO # D5 GPIO178NB1 DDR_S_1 1 I/O GPIO # # B5 GPIO179PB1 DDR_S_1 1 I/O GPIO # A5 GPIO179NB1 DDR_S_1 1 I/O GPIO # # G9 GPIO180PB1 DDR_S_2 1 I/O GPIO # F9 GPIO180NB1 DDR_S_2 1 I/O GPIO # # G7 GPIO181PB1 DDR_S_2 1 I/O GPIO # G6 GPIO181NB1 DDR_S_2 1 I/O GPIO # # E7 GPIO182PB1/DQS DDR_S_2 1 I/O GPIO # E6 GPIO182NB1/DQS DDR_S_2 1 I/O GPIO # # G10 GPIO183PB1 DDR_S_2 1 I/O GPIO # F10 GPIO183NB1 DDR_S_2 1 I/O GPIO # # F8 GPIO184PB1 DDR_S_2 1 I/O GPIO # F7 GPIO184NB1 DDR_S_2 1 I/O GPIO # # E8 GPIO185PB1 DDR_S_2 1 I/O GPIO # D8 GPIO185NB1 DDR_S_2 1 I/O GPIO # # # # # # FPGA Bank 7 # ------------------- # # There are 24 pins in Bank 7 This is a 3V3 Bank on the DK. # # # K5 GPIO138NB7 DDR_W_4 I/O GPIO # K6 GPIO138PB7 DDR_W_4 I/O GPIO # # K3 GPIO139NB7 DDR_W_4 I/O GPIO # J3 GPIO139PB7/CLKIN_W_7 DDR_W_4 I/O GPIO # # J4 GPIO140NB7 DDR_W_4 I/O GPIO # J5 GPIO140PB7/CLKIN_W_6 DDR_W_4 I/O GPIO # # H4 GPIO141NB7/DQS DDR_W_4 I/O GPIO # H3 GPIO141PB7/DQS DDR_W_4 I/O GPIO # # J6 GPIO142NB7 DDR_W_4 I/O GPIO # K7 GPIO142PB7/CLKIN_W_5 DDR_W_4 I/O GPIO # # H6 GPIO143NB7 DDR_W_4 I/O GPIO # H7 GPIO143PB7/CLKIN_W_4 DDR_W_4 I/O GPIO # # K2 GPIO162NB7 DDR_W_0 I/O GPIO # K1 GPIO162PB7/CLKIN_W_3/ DDR_W_0 I/O GPIO # CCC_SW_CLKIN_W_3 # # J1 GPIO163NB7 DDR_W_0 I/O GPIO # H1 GPIO163PB7/CLKIN_W_2/ DDR_W_0 I/O GPIO # CCC_SW_CLKIN_W_2/ # CCC_SW_PLL0_OUT0 # # F3 GPIO164NB7 DDR_W_0 I/O GPIO # F4 GPIO164PB7/CLKIN_W_1/ DDR_W_0 I/O GPIO # CCC_SW_CLKIN_W_1 # # H2 GPIO165NB7/DQS DDR_W_0 I/O GPIO # G2 GPIO165PB7/DQS/ DDR_W_0 I/O GPIO # CCC_SW_PLL0_OUT0 # # G1 GPIO166NB7 DDR_W_0 I/O GPIO # F2 GPIO166PB7 DDR_W_0 I/O GPIO # # G4 GPIO167NB7 DDR_W_0 I/O GPIO # G5 GPIO167PB7/CLKIN_W_0/ DDR_W_0 I/O GPIO # CCC_SW_CLKIN_W_0 # # # # # # FPGA Bank 9 # ------------------- # # There are 84 pins in Bank 9 This is a 1V8 Bank on the DK. # # # E15 GPIO18PB9 DDR_S_6 I/O GPIO # D15 GPIO18NB9 DDR_S_6 I/O GPIO # # A14 GPIO19PB9 DDR_S_6 I/O GPIO # A15 GPIO19NB9 DDR_S_6 I/O GPIO # # B15 GPIO20PB9/DQS DDR_S_6 I/O GPIO # B16 GPIO20NB9/DQS DDR_S_6 I/O GPIO # # E17 GPIO21PB9 DDR_S_6 I/O GPIO # E16 GPIO21NB9 DDR_S_6 I/O GPIO # # D16 GPIO22PB9 DDR_S_6 I/O GPIO # C16 GPIO22NB9 DDR_S_6 I/O GPIO # # C17 GPIO23PB9 DDR_S_6 I/O GPIO # B17 GPIO23NB9 DDR_S_6 I/O GPIO # # K15 GPIO24PB9 DDR_S_7 I/O GPIO # J15 GPIO24NB9 DDR_S_7 I/O GPIO # # G17 GPIO25PB9 DDR_S_7 I/O GPIO # F17 GPIO25NB9 DDR_S_7 I/O GPIO # # G16 GPIO26PB9/DQS DDR_S_7 I/O GPIO # H16 GPIO26NB9/DQS DDR_S_7 I/O GPIO # # H17 GPIO27PB9 DDR_S_7 I/O GPIO # J16 GPIO27NB9 DDR_S_7 I/O GPIO # # G15 GPIO28PB9 DDR_S_7 I/O GPIO # F15 GPIO28NB9 DDR_S_7 I/O GPIO # # K17 GPIO29PB9 DDR_S_7 I/O GPIO # K16 GPIO29NB9 DDR_S_7 I/O GPIO # # F18 GPIO30PB9 DDR_S_8 I/O GPIO # F19 GPIO30NB9 DDR_S_8 I/O GPIO # # G19 GPIO31PB9 DDR_S_8 I/O GPIO # H18 GPIO31NB9 DDR_S_8 I/O GPIO # # J18 GPIO32PB9/DQS DDR_S_8 I/O GPIO # K18 GPIO32NB9/DQS DDR_S_8 I/O GPIO # # K20 GPIO33PB9 DDR_S_8 I/O GPIO # J20 GPIO33NB9 DDR_S_8 I/O GPIO # # F20 GPIO34PB9 DDR_S_8 I/O GPIO # G20 GPIO34NB9 DDR_S_8 I/O GPIO # # H19 GPIO35PB9 DDR_S_8 I/O GPIO # J19 GPIO35NB9 DDR_S_8 I/O GPIO # # D19 GPIO42PB9 DDR_S_10 I/O GPIO # E20 GPIO42NB9 DDR_S_10 I/O GPIO # # A17 GPIO43PB9 DDR_S_10 I/O GPIO # A18 GPIO43NB9 DDR_S_10 I/O GPIO # # C18 GPIO44PB9/DQS DDR_S_10 I/O GPIO # C19 GPIO44NB9/DQS DDR_S_10 I/O GPIO # # B19 GPIO45PB9 DDR_S_10 I/O GPIO # A19 GPIO45NB9 DDR_S_10 I/O GPIO # # E18 GPIO46PB9 DDR_S_10 I/O GPIO # D18 GPIO46NB9 DDR_S_10 I/O GPIO # # B20 GPIO47PB9 DDR_S_10 I/O GPIO # A20 GPIO47NB9 DDR_S_10 I/O GPIO # # D21 GPIO48PB9 DDR_S_11 I/O GPIO # D20 GPIO48NB9 DDR_S_11 I/O GPIO # # B21 GPIO49PB9 DDR_S_11 I/O GPIO # C21 GPIO49NB9 DDR_S_11 I/O GPIO # # A22 GPIO50PB9/DQS DDR_S_11 I/O GPIO # A23 GPIO50NB9/DQS DDR_S_11 I/O GPIO # # C23 GPIO51PB9 DDR_S_11 I/O GPIO # D23 GPIO51NB9 DDR_S_11 I/O GPIO # # B22 GPIO52PB9 DDR_S_11 I/O GPIO # C22 GPIO52NB9 DDR_S_11 I/O GPIO # # A24 GPIO53PB9 DDR_S_11 I/O GPIO # A25 GPIO53NB9 DDR_S_11 I/O GPIO # # B24 GPIO54PB9 DDR_S_12 I/O GPIO # C24 GPIO54NB9 DDR_S_12 I/O GPIO # # B25 GPIO55PB9 DDR_S_12 I/O GPIO # B26 GPIO55NB9 DDR_S_12 I/O GPIO # # C27 GPIO56PB9/DQS/ DDR_S_12 I/O GPIO # CCC_SE_PLL0_OUT0 # C26 GPIO56NB9/DQS DDR_S_12 I/O GPIO # # A27 GPIO57PB9/ DDR_S_12 I/O GPIO # CLKIN_S_12/ # CCC_SE_CLKIN_S_12/ # CCC_SE_PLL0_OUT0 # B27 GPIO57NB9 DDR_S_12 I/O GPIO # # D25 GPIO58PB9/ DDR_S_12 I/O GPIO # CCC_SE_PLL0_OUT1 # D24 GPIO58NB9 DDR_S_12 I/O GPIO # # B28 GPIO59PB9/ DDR_S_12 I/O GPIO # CLKIN_S_13/ # CCC_SE_CLKIN_S_13 # C28 GPIO59NB9 DDR_S_12 I/O GPIO # # H21 GPIO60PB9 DDR_S_13 I/O GPIO # G21 GPIO60NB9 DDR_S_13 I/O GPIO # # K21 GPIO61PB9 DDR_S_13 I/O GPIO # J21 GPIO61NB9 DDR_S_13 I/O GPIO # # F22 GPIO62PB9/DQS/ DDR_S_13 I/O GPIO # CCC_SE_PLL1_OUT0 # G22 GPIO62NB9/DQS DDR_S_13 I/O GPIO # # E21 GPIO63PB9/ DDR_S_13 I/O GPIO # CCC_SE_CLKIN_S_14/ # CCC_SE_PLL1_OUT0 # E22 GPIO63NB9 DDR_S_13 I/O GPIO # # H22 GPIO64PB9/ DDR_S_13 I/O GPIO # CCC_SE_PLL1_OUT1 # G23 GPIO64NB9 DDR_S_13 I/O GPIO # # F23 GPIO65PB9/ DDR_S_13 I/O GPIO # CCC_SE_CLKIN_S_15 # E23 GPIO65NB9 DDR_S_13 I/O GPIO # #