#
#           Disco-Kraken  Net List  File
#
#       FPGA  Bypass Caps  and  Power Filters
#      ---------------------------------------
#
#
#                                        Initial Rev.  16-Nov-2022
#                                        Current Rev.  30-Nov-2023
#
#
#   This net list holds the nets for:
#
#     - FPGA LC Power Filters
#
#     - FPGA ByPass Capacitors
#


#
#    CORE Power to the FPGA/CPU   1V05:
#   ------------------------------------
#

NET  'BULK_1V05'    L101-1                      # Bulk_1V05 Power Into Filter
NET  'CORE_1V05'    L101-2                      # Filtered CORE Power

NET  'CORE_1V05'    C101-2   C102-2                     # CORE  Tantalum  Bypass
NET  'GROUND'       C101-1   C102-1                     # Tant Bypass Cap Grounds

NET  'CORE_1V05'    C103-1   C104-1   C105-1   C106-1   # CORE  22 uFd  Bypass
NET  'GROUND'       C103-2   C104-2   C105-2   C106-2   # Bypass Cap Grounds





#
#    FPGA_1V8  Supply for:  Programming, HSIO Aux, and  Bank #9  I/O
#
#    The  FPGA_1V8  Supply comes from the  BULK_1V8  Supply via  L103
#   ------------------------------------------------------------------
#

NET  'BULK_1V8'     L103-2         # Bulk_1V8 Power into the Filter
NET  'FPGA_1V8'     L103-1         # Filtered Power to FPGA:  Prog, HSIO_Aux, Bank #9





#
#    Transceiver  1V05  Analog Power:
#   ----------------------------------
#

NET  'BULK_1V05'    L102-1         # Bulk_1V05 Power Into Filter
NET  'XCVR_1V05'    L102-2         # Filtered Transceiver 1V05 Analog Power





#
#    2V5 Power to the FPGA/CPU and to the DDR4 Memory:
#   ---------------------------------------------------
#

#   Analog_2V5 for:   FPGA_PLL_2V5,  XCVR_PLL_2V5, &  XCVR_CLK   Supplies

NET  'BULK_2V5'      L104-2        # Bulk_2V5 Power Into Filter
NET  'Analog_2V5'    L104-1        # Filtered  Analog_2V5  Power


#   Digital_2V5 for:   DDR4 Memory PreCharge  &  Bank #9 Aux   Supplies

NET  'BULK_2V5'      L105-2        # Bulk_2V5 Power Into Filter
NET  'Digital_2V5'   L105-1        # Filtered  Analog_2V5  Power





#
#    BANK 0   FPGA DDR4 Memory   BULK_1V2:
#   ---------------------------------------
#

NET  'BULK_1V2'     C201-1   C202-1                     # Bank 0  22 uFd  Bypass
NET  'GROUND'       C201-2   C202-2                     # Bypass Cap Grounds

NET  'BULK_1V2'     C203-1   C204-1                     # Bank 0  2.2 uFd  Bypass
NET  'GROUND'       C203-2   C204-2                     # Bypass Cap Grounds





#
#    BANK 6   CPU DDR4 Memory   BULK_1V2:
#   --------------------------------------
#

NET  'BULK_1V2'     C221-1   C222-1                     # Bank 0  22 uFd  Bypass
NET  'GROUND'       C221-2   C222-2                     # Bypass Cap Grounds

NET  'BULK_1V2'     C223-1   C224-1                     # Bank 0  2.2 uFd  Bypass
NET  'GROUND'       C223-2   C224-2                     # Bypass Cap Grounds