# # Disco-Kraken Key In Net List # ------------------------------- # # # Floating Pin Connections to FPGA/CPU # -==============------------------------- # # # # Initial Rev. 4-Dec-2023 # Current Rev. 26-Dec-2023 # # # # This netlist holds just the FPGA/CPU end of nets that connect # to "floating" pins on this component, i.e. to pins that are # fixed to a given pin number only by the design put into the # FPGA/CPU. # # Function specific pins, e.g. Bank #3, DDR4 Memory, High-Speed # Serial Links, are all assigned in the Net List file that # describes that particular function on the DK board. # # This Net List file is only for the FPGA/CPU end of these # "floating" connections. All of these floating connections # are either to: Bank #9 for 1V8 I/O or to Banks #1 & #7 # for 3V3 I/O. Most of these floating conections go to CPU # peripherals or to normal FPGA I/O signals. # # For reference the pins in Banks 1, 7, and 9 are listed at # the end of this file. # # The intent of this Net List file is to collect in one place all # of the floating pin connections to the FPGA/CPU so that it is # easier to coordinate these pin numbers with the firmware/software # work on this part. # # The Net List files that describe the functions that are assigned # to floating pins on the FPGA/CPU all included a note to remind # folks that the final step in these floating FPGA/CPU conections # is in this file. # # This file is devided into a number of sections - one section for # each DK board function that connects to the FPGA/CPU via Floating # Pin Assignments. # # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # Access Connector and UART to ER uProc Connections with the FPGA/CPU # --------------------------------------------------------------------------- # # # These are 3V3 signals: CPU MMUART #0 Data to/from Access Connector # ------------------------------------------------------------------------ # # NET 'CPU_UART_0_Tx__to__Access' # CPU UART 0 Tx Data to Access Connector # NET 'CPU_UART_0_Rx_from_Access' # CPU UART 0 Rx Data from Access Connector # # # These are 3V3 signals: CPU MMUART #1 Data to/from Emergency Rescue uProcessor # ----------------------------------------------------------------------------------- # # NET 'CPU_UART_1_Tx__to__ER_uProc' # CPU UART 1 Tx Data to Emergency Rescue uProc # NET 'CPU_UART_1_Rx_from_ER_uProc' # CPU UART 1 Rx Data from Emergency Rescue uProc # # # # These are 3V3 signals: FPGA/CPU <--> Access Connector Single Ended Signals # ---------------------------------------------------------------------------------------- # # NET 'Access_Signal_1' # Access Connector FPGA Signal #1 # NET 'Access_Signal_2' # Access Connector FPGA Signal #2 # NET 'Access_Signal_3' # Access Connector FPGA Signal #3 # NET 'Access_Signal_4' # Access Connector FPGA Signal #4 # NET 'Access_Signal_5' # Access Connector FPGA Signal #5 # # # # Both of these are Differential signals, e.g. LVDS: # # FPGA/CPU <--> Access Connector Differential Pairs # ---------------------------------------------------------------------------------------- # # NET 'Access_Diff_Pair_1_Dir' # Access Connector FPGA Differential Pair #1 DIR # NET 'Access_Diff_Pair_1_Cmp' # Access Connector FPGA Differential Pair #1 CMP # # NET 'Access_Diff_Pair_2_Dir' # Access Connector FPGA Differential Pair #2 DIR # NET 'Access_Diff_Pair_2_Cmp' # Access Connector FPGA Differential Pair #2 CMP # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # BARNACLE to/from CPU UART Data Connections with the FPGA/CPU # ---------------------------------------------------------------- # # # These are 3V3 signals: Barnacle UART Data # CPU MMUART #2 # ---------------------------------------------- # # NET 'CPU_UART_Tx__to__Barnacle' # DK CPU UART Tx Data to Barnacle # NET 'CPU_UART_Rx_from_Barnacle' # DK CPU UART Rx Data from Barnacle # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # BB Audio ADC Clock and Readout Data Connections with the FPGA/CPU # --------------------------------------------------------------------- # # # These are 1V8 signals: BB Audio ADC Readout Signals # ------------------------------------------------------- # # NET 'FPGA_BB_ADC_CLK_Out' # FPGA BB Audio ADC CLK to Term Resistor # # NET 'FPGA_BB_ADC_SDATA_IN' # Term Resistor to FPGA BB ADC SData Input # # NET 'FPGA_BB_ADC_BCLK_IN' # Term Resistor to FPGA BB ADC BCLK Input # # NET 'FPGA_BB_ADC_FSYNC_IN' # Term Resistor to FPGA BB ADC FSYNC Input # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # Environmental Sensor I2C Bus Connections with the FPGA/CPU # -------------------------------------------------------------- # # # These are 1V8 signals: Env Sesnsor and BB Audio I2C Bus # CPU I2C Controller #1 # ----------------------------------------------------------- # # NET 'I2C_DATA_SENSOR_BB_ADC' # Sensor & BB ADC I2C Bus Data # # NET 'I2C_SCLK_SENSOR_BB_ADC' # Sensor & BB ADC I2C Bus Clock # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # Interposer 1 and 2 Connections to the FPGA/CPU via Floating Pins # --------------------------------------------------------------------- # # # These are 3V3 signals: SPI Bus and GPIO Used with the Interposer SPI Bus # from CPU SPI Bus Controller #1 # ---------------------------------------------------------------------------- # NET 'Poser_SCLK_FPGA_to_Term' U1-A10 # SCLK FPGA to Series Term NET 'Poser_MOSI_FPGA_to_Term' U1-A12 # MOSI FPGA to Series Term NET 'Poser_MISO_Term_to_FPGA' U1-A13 # MISO Mux Term to FPGA # # NET 'Poser_CS_1_B' # FPGA Signal to Enable Interposer #1 Mux _B # NET 'Poser_CS_2_B' # FPGA Signal to Enable Interposer #2 Mux _B # # NET 'Poser_CS_Adrs_0' # CS Address 0 FPGA to Mux # NET 'Poser_CS_Adrs_1' # CS Address 1 FPGA to Mux # NET 'Poser_CS_Adrs_2' # CS Address 2 FPGA to Mux # # # # These are 1V8 signals: CPU UART Data to/from both Interposers --> PMT Bases # CPU MMUART #3 <--> Interposer #1 "This Hemisphere" # CPU MMUART #4 <--> Interposer #2 "Other Hemisphere" # --------------------------------------------------------------------------------- # # NET 'CPU_UART_3_Tx__to__Poser_1' # Tx UART 3 Data to Interposer_1 via Buffer # NET 'CPU_UART_3_Rx_from_Poser_1' # Rx UART 3 Data from Interposer_1 via Buffer # # NET 'CPU_UART_4_Tx__to__Poser_2' # Tx UART 4 Data to Interposer_2 via Buffer # NET 'CPU_UART_4_Rx_from_Poser_2' # Rx UART 4 Data from Interposer_2 via Buffer # # # # All of these are 3V3 signals: Flash-Now to both Interposers and to AD9546 # Control-Reset to both Interposers # SMUT S1...S4 from only Other Interposer to FPGA # ------------------------------------------------------------------------------------- # # NET 'Flash_Now' # Flash_Now from the FPGA/CPU to both # # Interposers and to the AD9546 for # # time measurement a 3V3 CMOS signal # # NET 'Interposer_Ctrl_Reset' # Control Reset to Both Interposers from FPGA/CPU # # NET 'SMUT_S1_Other_Hemi' # Muon SMUT signal S1 from Other Hemisphere to FPGA/CPU # NET 'SMUT_S2_Other_Hemi' # Muon SMUT signal S2 from Other Hemisphere to FPGA/CPU # NET 'SMUT_S3_Other_Hemi' # Muon SMUT signal S3 from Other Hemisphere to FPGA/CPU # NET 'SMUT_S4_Other_Hemi' # Muon SMUT signal S4 from Other Hemisphere to FPGA/CPU # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # PMT ADC Connections with the FPGA/CPU # ------------------------------------------- # # # These are 1V8 SPI signals: PMT ADC SPI Bus (private) # CPU SPI Bus Controller #0 # and 4W to 3W Converter # ------------------------------------------------------------ # # NET 'PMT_ADC_CHIP_SELECT_B' # ADC SPI Chip Select Active LOW # NET 'PMT_ADC_SPI_CLOCK' # ADC SPI Clock # NET 'PMT_ADC_SPI_DATA_IO' # ADC SPI Data I/O # # # These are LVDS signals: PMT ADC Clock Type Signals # ------------------------------------------------------- # # NET 'PMT_ADC_SYNC_ENB_B_DIR' # ADC JESD204B Sync Enb B DIR # NET 'PMT_ADC_SYNC_ENB_B_CMP' # ADC JESD204B Sync Enb B CMP # # NET 'PMT_ADC_Trigger_DIR' # ADC Trigger Dir Input # NET 'PMT_ADC_Trigger_CMP' # ADC Trigger Cmp Input # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # SFP Module and I2C Controller #0 Connections with the FPGA/CPU # -------------------------------------------------------------------- # # # These are 3V3 signals: SFP Module Control and Monitor Signals # ----------------------------------------------------------------- # # NET 'SFP_Time_TX_Fault' # Time SFP Tx Fault to FPGA/CPU GPIO Input # NET 'SFP_Time_MOD_ABS' # Time SFP Module Absent to FPGA/CPU GPIO Input # NET 'SFP_Time_RX_LOS' # Time SFP Rx Signal Loss to FPGA/CPU GPIO Input # # NET 'SFP_Time_Trans_Enable' # Time SFP Tx Enable from FPGA/CPU GPIO Output # # NET 'SFP_Time_RS_0' # Time SFP Rate Select 0 <--> FPGA/CPU GPIO I/O # NET 'SFP_Time_RS_1' # Time SFP Rate Select 1 <--> FPGA/CPU GPIO I/O # # # NET 'SFP_ENet_TX_Fault' # ENet SFP Tx Fault to FPGA/CPU GPIO Input # NET 'SFP_ENet_MOD_ABS' # ENet SFP Module Absent to FPGA/CPU GPIO Input # NET 'SFP_ENet_RX_LOS' # ENet SFP Rx Signal Loss to FPGA/CPU GPIO Input # # NET 'SFP_ENet_Trans_Enable' # ENET SFP Tx Enable from FPGA/CPU GPIO Output # # NET 'SFP_ENet_RS_0' # Time SFP Rate Select 0 <--> FPGA/CPU GPIO I/O # NET 'SFP_ENet_RS_1' # Time SFP Rate Select 1 <--> FPGA/CPU GPIO I/O # # # These are 3V3 signals: I2C Bus for both SFP Modules and for Timing Generator # CPU I2C Controller #0 Serial Clk & Data # -------------------------------------------------------------------------------- # # NET 'CPU_I2C_Ctrl_0_SCL' # FPGA/CPU Controller 0 I2C SCLK to Fan-Out # NET 'CPU_I2C_Ctrl_0_SDA' # FPGA/CPU Controller 0 I2C SDATA to Fan-Out # # NET 'CPU_I2C_Ctrl_0_Fan_Out_RESET_B' # I2C Fanout Reset_B from FPGA/CPU GPIO # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # Startup and Resets Controller Connections with the FPGA/CPU # -------------------------------------------------------------------- # # # These are 3V3 signals: DK_CPU_Is_Awake (_B) and the RUN signals # ----------------------------------------------------------------------- # # NET 'DK_CPU_Is_Awake' # CPU is Awake signal # NET 'DK_CPU_Is_Awake_B' # CPU is Awake_B signal # # NET 'Run_PMT_ADC' # LOW ---> Reset the AD9083 PMT ADC # NET 'Run_Clock_Generator' # LOW ---> Reset the AD9546 Clock Generator # NET 'Run_USB_Interface' # LOW ---> Reset the USB3340 USB Transceiver # NET 'Run_BB_Audio_ADC' # LOW ---> Reset the TLV320ADC6140 BB Audio ADC # NET 'Run_SPARE' # Currently 26-Dec-2023 this signal is not used # # NET 'Run_Barnacle' # LOW ---> Barnacle Power Down and Master_Reset_B # NET 'Barnacle_Control_1' # Barnacle Control Signal 1 default is Low # NET 'Barnacle_Control_2' # Barnacle Control Signal 2 default is Low # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- # # # USB Phy Reference Clock Connections with the FPGA/CPU # ------------------------------------------------------ # # # These are 3V3 signals: USB Phy Ref Clk 26 MHz # from a FPGA/CPU CCC Clock Output # ------------------------------------------------------------ # # NET 'FPGA_Ref_Clk_to_USB_Phy' # FPGA Clk Output to USB Phy Ref Clk Input # #--------------------------------------------------------------------- # # #--------------------------------------------------------------------- #--------------------------------------------------------------------- #--------------------------------------------------------------------- # # # Reference Data MPFS250T-1FCVG784I Banks: 1, 7, 9 # --------------------------------------------------------- # # # FPGA Bank 1 # ------------------- # # There are 72 pins in Bank 1 This is a 3V3 Bank on the DK. # # Bank 1 pins are located in two groups on the FCVG784 package. # # # D9 GPIO0PB1/CLKIN_S_4 DDR_S_3 I/O GPIO # D10 GPIO0NB1 DDR_S_3 I/O GPIO # # B7 GPIO1PB1/CLKIN_S_5 DDR_S_3 I/O GPIO # A7 GPIO1NB1 DDR_S_3 I/O GPIO # # C8 GPIO2PB1/DQS DDR_S_3 I/O GPIO # C7 GPIO2NB1/DQS DDR_S_3 I/O GPIO # # A8 GPIO3PB1/CLKIN_S_6 DDR_S_3 I/O GPIO # A9 GPIO3NB1 DDR_S_3 I/O GPIO # # C9 GPIO4PB1/LPRB_A DDR_S_3 I/O GPIO # B9 GPIO4NB1/LPRB_B DDR_S_3 I/O GPIO # # B10 GPIO5PB1/CLKIN_S_7 DDR_S_3 I/O GPIO # A10 GPIO5NB1 DDR_S_3 I/O GPIO # # F12 GPIO6PB1 DDR_S_4 I/O GPIO # E12 GPIO6NB1 DDR_S_4 I/O GPIO # # F13 GPIO7PB1 DDR_S_4 I/O GPIO # E13 GPIO7NB1 DDR_S_4 I/O GPIO # # D14 GPIO8PB1/DQS DDR_S_4 I/O GPIO # D13 GPIO8NB1/DQS DDR_S_4 I/O GPIO # # G12 GPIO9PB1/CLKIN_S_8/ # CCC_SE_CLKIN_S_8 DDR_S_4 I/O GPIO # G11 GPIO9NB1 DDR_S_4 I/O GPIO # # F14 GPIO10PB1 DDR_S_4 I/O GPIO # G14 GPIO10NB1 DDR_S_4 I/O GPIO # # J14 GPIO11PB1/CLKIN_S_9/ # CCC_SE_CLKIN_S_9 DDR_S_4 I/O GPIO # H14 GPIO11NB1 DDR_S_4 I/O GPIO # # E11 GPIO12PB1 DDR_S_5 I/O GPIO # E10 GPIO12NB1 DDR_S_5 I/O GPIO # # B12 GPIO13PB1 DDR_S_5 I/O GPIO # B11 GPIO13NB1 DDR_S_5 I/O GPIO # # C13 GPIO14PB1/DQS DDR_S_5 I/O GPIO # C12 GPIO14NB1/DQS DDR_S_5 I/O GPIO # # C14 GPIO15PB1/ # CCC_SE_CLKIN_S_10 DDR_S_5 I/O GPIO # B14 GPIO15NB1 DDR_S_5 I/O GPIO # # D11 GPIO16PB1 DDR_S_5 I/O GPIO # C11 GPIO16NB1 DDR_S_5 I/O GPIO # # A12 GPIO17PB1/ # CCC_SE_CLKIN_S_11 DDR_S_5 I/O GPIO # A13 GPIO17NB1 DDR_S_5 I/O GPIO # # # # # C2 GPIO168PB1/CCC_SW_CLKIN_S_0 DDR_S_0 1 I/O GPIO # B2 GPIO168NB1 DDR_S_0 1 I/O GPIO # # E3 GPIO169PB1/CCC_SW_CLKIN_S_1 DDR_S_0 1 I/O GPIO # E2 GPIO169NB1 DDR_S_0 1 I/O GPIO # # E1 GPIO170PB1/DQS/CCC_SW_PLL1_OUT0 DDR_S_0 1 I/O GPIO # D1 GPIO170NB1/DQS DDR_S_0 1 I/O GPIO # # D3 GPIO171PB1/ DDR_S_0 1 I/O GPIO # CLKIN_S_2/CCC_SW_CLKIN_S_2/ # CCC_SW_PLL1_OUT0 # C3 GPIO171NB1 DDR_S_0 1 I/O GPIO # # C1 GPIO172PB1/CCC_SW_PLL1_OUT1 DDR_S_0 1 I/O GPIO # B1 GPIO172NB1 DDR_S_0 1 I/O GPIO # # A2 GPIO173PB1/CLKIN_S_3/ DDR_S_0 1 I/O GPIO # CCC_SW_CLKIN_S_3 # A3 GPIO173NB1 DDR_S_0 1 I/O GPIO # # E5 GPIO174PB1 DDR_S_1 1 I/O GPIO # F5 GPIO174NB1 DDR_S_1 1 I/O GPIO # # C6 GPIO175PB1 DDR_S_1 1 I/O GPIO # B6 GPIO175NB1 DDR_S_1 1 I/O GPIO # # D4 GPIO176PB1/DQS/CCC_SW_PLL0_OUT0 DDR_S_1 1 I/O GPIO # C4 GPIO176NB1/DQS DDR_S_1 1 I/O GPIO # # B4 GPIO177PB1/CCC_SW_PLL0_OUT0 DDR_S_1 1 I/O GPIO # A4 GPIO177NB1 DDR_S_1 1 I/O GPIO # # D6 GPIO178PB1/CCC_SW_PLL0_OUT1 DDR_S_1 1 I/O GPIO # D5 GPIO178NB1 DDR_S_1 1 I/O GPIO # # B5 GPIO179PB1 DDR_S_1 1 I/O GPIO # A5 GPIO179NB1 DDR_S_1 1 I/O GPIO # # G9 GPIO180PB1 DDR_S_2 1 I/O GPIO # F9 GPIO180NB1 DDR_S_2 1 I/O GPIO # # G7 GPIO181PB1 DDR_S_2 1 I/O GPIO # G6 GPIO181NB1 DDR_S_2 1 I/O GPIO # # E7 GPIO182PB1/DQS DDR_S_2 1 I/O GPIO # E6 GPIO182NB1/DQS DDR_S_2 1 I/O GPIO # # G10 GPIO183PB1 DDR_S_2 1 I/O GPIO # F10 GPIO183NB1 DDR_S_2 1 I/O GPIO # # F8 GPIO184PB1 DDR_S_2 1 I/O GPIO # F7 GPIO184NB1 DDR_S_2 1 I/O GPIO # # E8 GPIO185PB1 DDR_S_2 1 I/O GPIO # D8 GPIO185NB1 DDR_S_2 1 I/O GPIO # # # # # # FPGA Bank 7 # ------------------- # # There are 24 pins in Bank 7 This is a 3V3 Bank on the DK. # # # K5 GPIO138NB7 DDR_W_4 I/O GPIO # K6 GPIO138PB7 DDR_W_4 I/O GPIO # # K3 GPIO139NB7 DDR_W_4 I/O GPIO # J3 GPIO139PB7/CLKIN_W_7 DDR_W_4 I/O GPIO # # J4 GPIO140NB7 DDR_W_4 I/O GPIO # J5 GPIO140PB7/CLKIN_W_6 DDR_W_4 I/O GPIO # # H4 GPIO141NB7/DQS DDR_W_4 I/O GPIO # H3 GPIO141PB7/DQS DDR_W_4 I/O GPIO # # J6 GPIO142NB7 DDR_W_4 I/O GPIO # K7 GPIO142PB7/CLKIN_W_5 DDR_W_4 I/O GPIO # # H6 GPIO143NB7 DDR_W_4 I/O GPIO # H7 GPIO143PB7/CLKIN_W_4 DDR_W_4 I/O GPIO # # K2 GPIO162NB7 DDR_W_0 I/O GPIO # K1 GPIO162PB7/CLKIN_W_3/ DDR_W_0 I/O GPIO # CCC_SW_CLKIN_W_3 # # J1 GPIO163NB7 DDR_W_0 I/O GPIO # H1 GPIO163PB7/CLKIN_W_2/ DDR_W_0 I/O GPIO # CCC_SW_CLKIN_W_2/ # CCC_SW_PLL0_OUT0 # # F3 GPIO164NB7 DDR_W_0 I/O GPIO # F4 GPIO164PB7/CLKIN_W_1/ DDR_W_0 I/O GPIO # CCC_SW_CLKIN_W_1 # # H2 GPIO165NB7/DQS DDR_W_0 I/O GPIO # G2 GPIO165PB7/DQS/ DDR_W_0 I/O GPIO # CCC_SW_PLL0_OUT0 # # G1 GPIO166NB7 DDR_W_0 I/O GPIO # F2 GPIO166PB7 DDR_W_0 I/O GPIO # # G4 GPIO167NB7 DDR_W_0 I/O GPIO # G5 GPIO167PB7/CLKIN_W_0/ DDR_W_0 I/O GPIO # CCC_SW_CLKIN_W_0 # # # # # # FPGA Bank 9 # ------------------- # # There are 84 pins in Bank 9 This is a 1V8 Bank on the DK. # # # E15 GPIO18PB9 DDR_S_6 I/O GPIO # D15 GPIO18NB9 DDR_S_6 I/O GPIO # # A14 GPIO19PB9 DDR_S_6 I/O GPIO # A15 GPIO19NB9 DDR_S_6 I/O GPIO # # B15 GPIO20PB9/DQS DDR_S_6 I/O GPIO # B16 GPIO20NB9/DQS DDR_S_6 I/O GPIO # # E17 GPIO21PB9 DDR_S_6 I/O GPIO # E16 GPIO21NB9 DDR_S_6 I/O GPIO # # D16 GPIO22PB9 DDR_S_6 I/O GPIO # C16 GPIO22NB9 DDR_S_6 I/O GPIO # # C17 GPIO23PB9 DDR_S_6 I/O GPIO # B17 GPIO23NB9 DDR_S_6 I/O GPIO # # K15 GPIO24PB9 DDR_S_7 I/O GPIO # J15 GPIO24NB9 DDR_S_7 I/O GPIO # # G17 GPIO25PB9 DDR_S_7 I/O GPIO # F17 GPIO25NB9 DDR_S_7 I/O GPIO # # G16 GPIO26PB9/DQS DDR_S_7 I/O GPIO # H16 GPIO26NB9/DQS DDR_S_7 I/O GPIO # # H17 GPIO27PB9 DDR_S_7 I/O GPIO # J16 GPIO27NB9 DDR_S_7 I/O GPIO # # G15 GPIO28PB9 DDR_S_7 I/O GPIO # F15 GPIO28NB9 DDR_S_7 I/O GPIO # # K17 GPIO29PB9 DDR_S_7 I/O GPIO # K16 GPIO29NB9 DDR_S_7 I/O GPIO # # F18 GPIO30PB9 DDR_S_8 I/O GPIO # F19 GPIO30NB9 DDR_S_8 I/O GPIO # # G19 GPIO31PB9 DDR_S_8 I/O GPIO # H18 GPIO31NB9 DDR_S_8 I/O GPIO # # J18 GPIO32PB9/DQS DDR_S_8 I/O GPIO # K18 GPIO32NB9/DQS DDR_S_8 I/O GPIO # # K20 GPIO33PB9 DDR_S_8 I/O GPIO # J20 GPIO33NB9 DDR_S_8 I/O GPIO # # F20 GPIO34PB9 DDR_S_8 I/O GPIO # G20 GPIO34NB9 DDR_S_8 I/O GPIO # # H19 GPIO35PB9 DDR_S_8 I/O GPIO # J19 GPIO35NB9 DDR_S_8 I/O GPIO # # D19 GPIO42PB9 DDR_S_10 I/O GPIO # E20 GPIO42NB9 DDR_S_10 I/O GPIO # # A17 GPIO43PB9 DDR_S_10 I/O GPIO # A18 GPIO43NB9 DDR_S_10 I/O GPIO # # C18 GPIO44PB9/DQS DDR_S_10 I/O GPIO # C19 GPIO44NB9/DQS DDR_S_10 I/O GPIO # # B19 GPIO45PB9 DDR_S_10 I/O GPIO # A19 GPIO45NB9 DDR_S_10 I/O GPIO # # E18 GPIO46PB9 DDR_S_10 I/O GPIO # D18 GPIO46NB9 DDR_S_10 I/O GPIO # # B20 GPIO47PB9 DDR_S_10 I/O GPIO # A20 GPIO47NB9 DDR_S_10 I/O GPIO # # D21 GPIO48PB9 DDR_S_11 I/O GPIO # D20 GPIO48NB9 DDR_S_11 I/O GPIO # # B21 GPIO49PB9 DDR_S_11 I/O GPIO # C21 GPIO49NB9 DDR_S_11 I/O GPIO # # A22 GPIO50PB9/DQS DDR_S_11 I/O GPIO # A23 GPIO50NB9/DQS DDR_S_11 I/O GPIO # # C23 GPIO51PB9 DDR_S_11 I/O GPIO # D23 GPIO51NB9 DDR_S_11 I/O GPIO # # B22 GPIO52PB9 DDR_S_11 I/O GPIO # C22 GPIO52NB9 DDR_S_11 I/O GPIO # # A24 GPIO53PB9 DDR_S_11 I/O GPIO # A25 GPIO53NB9 DDR_S_11 I/O GPIO # # B24 GPIO54PB9 DDR_S_12 I/O GPIO # C24 GPIO54NB9 DDR_S_12 I/O GPIO # # B25 GPIO55PB9 DDR_S_12 I/O GPIO # B26 GPIO55NB9 DDR_S_12 I/O GPIO # # C27 GPIO56PB9/DQS/ DDR_S_12 I/O GPIO # CCC_SE_PLL0_OUT0 # C26 GPIO56NB9/DQS DDR_S_12 I/O GPIO # # A27 GPIO57PB9/ DDR_S_12 I/O GPIO # CLKIN_S_12/ # CCC_SE_CLKIN_S_12/ # CCC_SE_PLL0_OUT0 # B27 GPIO57NB9 DDR_S_12 I/O GPIO # # D25 GPIO58PB9/ DDR_S_12 I/O GPIO # CCC_SE_PLL0_OUT1 # D24 GPIO58NB9 DDR_S_12 I/O GPIO # # B28 GPIO59PB9/ DDR_S_12 I/O GPIO # CLKIN_S_13/ # CCC_SE_CLKIN_S_13 # C28 GPIO59NB9 DDR_S_12 I/O GPIO # # H21 GPIO60PB9 DDR_S_13 I/O GPIO # G21 GPIO60NB9 DDR_S_13 I/O GPIO # # K21 GPIO61PB9 DDR_S_13 I/O GPIO # J21 GPIO61NB9 DDR_S_13 I/O GPIO # # F22 GPIO62PB9/DQS/ DDR_S_13 I/O GPIO # CCC_SE_PLL1_OUT0 # G22 GPIO62NB9/DQS DDR_S_13 I/O GPIO # # E21 GPIO63PB9/ DDR_S_13 I/O GPIO # CCC_SE_CLKIN_S_14/ # CCC_SE_PLL1_OUT0 # E22 GPIO63NB9 DDR_S_13 I/O GPIO # # H22 GPIO64PB9/ DDR_S_13 I/O GPIO # CCC_SE_PLL1_OUT1 # G23 GPIO64NB9 DDR_S_13 I/O GPIO # # F23 GPIO65PB9/ DDR_S_13 I/O GPIO # CCC_SE_CLKIN_S_15 # E23 GPIO65NB9 DDR_S_13 I/O GPIO # #