# # Interposer All Other Nets # -------------===========------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 4-Dec-2023 # Current Rev. 24-July-2024 # # # # This net list holds the Interposer All Other Nets # ------------===========----- # # The components for the # DK's Interposer All Other Nets # are in the range 1451 to 1499. # # # # PIEZO Hydrophone Connection to the BB Audio ADC Inputs # ----------------------------------------------------------- # # This connection is made in the: # # interposer_connectors_all_nets.txt # and the bb_audio_adc_nets.txt files. # # # Nets for the Interposer 1V8 UART Buffers: # ------------------------------------------------- # # Interposer #1 Serviced by CPU MMUART #3 # --------------------------------------------- NET 'CPU_UART_3_Tx_to_INTERP_1' U1453-3 # DK CPU UART #3 Tx Data to Buffer NET 'CPU_UART_Tx_to_INTERP_1_B' U1453-4 U1453-5 # Inverted NET 'Data_to_INTERP_1_Buf_Term' U1453-6 R1484-2 # Buffered DK Tx Data to Series Terminator NET 'Interposer_1_UART_Rx' R1484-1 # DK Tx Data to the Interposer_1 Connector NET 'Interposer_1_UART_Tx' U1453-11 # DK Rx Data from the Interposer_1 Connector NET 'DK_Rx_Data_from_INTERP_1_B' U1453-10 U1453-9 # Inverted NET 'DK_Rx_Data_IPsr_1_to_Term' U1453-8 R1485-2 # Buffered DK Rx Data to Series Terminator NET 'CPU_UART_3_Rx_from_INTERP_1' R1485-1 # DK Rx Data to the DK's CPU UART #3 NET 'GROUND' U1453-1 U1453-13 # Tie down unused buffer inputs NET 'NO_CONN_U1453_Pin_2' U1453-2 # Unused Buffer Output NET 'NO_CONN_U1453_Pin_12' U1453-12 # Unused Buffer Output NET 'BULK_1V8' U1453-14 C1454-2 # 1V8 Power for UART Buffer NET 'GROUND' U1453-7 C1454-1 # Ground for the UART Buffer # Interposer #2 Serviced by CPU MMUART #4 # --------------------------------------------- NET 'CPU_UART_4_Tx_to_INTERP_2' U1454-3 # DK CPU UART #4 Tx Data to Buffer NET 'CPU_UART_Tx_to_INTERP_2_B' U1454-4 U1454-5 # Inverted NET 'Data_to_INTERP_2_Buf_Term' U1454-6 R1486-1 # Buffered DK Tx Data to Series Terminator NET 'Interposer_2_UART_Rx' R1486-2 # DK Tx Data to the Interposer_2 Connector NET 'Interposer_2_UART_Tx' U1454-11 # DK Rx Data from the Interposer_2 Connector NET 'DK_Rx_Data_from_INTERP_2_B' U1454-10 U1454-9 # Inverted NET 'DK_Rx_Data_IPsr_2_to_Term' U1454-8 R1487-2 # Buffered DK Rx Data to Series Terminator NET 'CPU_UART_4_Rx_from_INTERP_2' R1487-1 # DK Rx Data to the DK's CPU UART #4 NET 'GROUND' U1454-1 U1454-13 # Tie down unused buffer inputs NET 'NO_CONN_U1454_Pin_2' U1454-2 # Unused Buffer Output NET 'NO_CONN_U1454_Pin_12' U1454-12 # Unused Buffer Output NET 'BULK_1V8' U1454-14 C1455-1 # 1V8 Power for UART Buffer NET 'GROUND' U1454-7 C1455-2 # Ground for the UART Buffer # # FLASH NOW signal from FPGA/CPU to Both Interposers and to the AD9546: # ----------------------------------------------------------------------------- # # The Flash Now signal comes from Bank #9 of the FPGA as 1V8 CMOS. # The Flash Now signal goes to the Timing Gen. M3 input as 1V8 CMOS. # The Flash Now signal is converted to 3V3 and goes to both Inputposer connectors. # # # The 1V8 Flash_Now signal come out on Bank #9 of the FPGA/CPU # # via R1490 to the M3 Auxiliary Input of the Timing Generator as 1V8 # # via R1491 to both B Inputs of the U1455 Level Translator 74AVCH2T45 # # from both of the 3V3 U1455 Outputs via R1492 & R1453 to pin 7 # on both Interposer connectors J4 & J5 as the 3V3 CMOS "Flash_Pulse" signal # # The Direction pin of the Level Translator is LOW --> B is Input A is Output # VccA is 3V3 VccB is 1V8 # # --------------------------------------------------------------------------------------- # NET 'Flash_Now' R1490-2 R1491-1 # Flash_Now signal from the FPGA/CPU # This is a 1V8 CMOS single ended signal # from a "floating" pin on the FPGA/CPU # Bank #9 to a pair of series terminators. NET 'TG_Aux_In_M3' R1490-1 # Flash_Now from the FPGA/CPU to the 1V8 "M3" Aux Input # of the AD9546 Timing Generator for timing measurement. NET 'Flash_Now_to_Level_Trans' R1491-2 U1455-6 U1455-7 # Flash_Now to Level Translator # B Inputs as a 1V8 signal NET 'Flash_Now_1_to_Term' U1455-3 R1492-2 # 3V3 Flash Pulse to Terminator Resistor NET 'Interposer_1_Flash_Pulse' R1492-1 # Flash_Pluse signal to Interposer #1 NET 'Flash_Now_2_to_Term' U1455-2 R1493-1 # 3V3 Flash Pulse to Terminator Resistor NET 'Interposer_2_Flash_Pulse' R1493-2 # Flash_Pluse signal to Interposer #2 NET 'GROUND' U1455-4 U1455-5 # Ground the Level Translator Ground pin # and Ground its DIR pin ---> B is Input A is Output NET 'BULK_3V3' U1455-1 C1481-2 C1482-1 # Bulk_3V3 to the VccA pin on the translator NET 'GROUND' C1481-1 C1482-2 # Ground the bypass capacitors NET 'BULK_1V8' U1455-8 C1483-1 C1484-1 # Bulk_1V8 to the VccB pin on the translator NET 'GROUND' C1483-2 C1484-2 # Ground the bypass capacitors # # FLASH-TDC signals from Both Interposers to the AD9546 for Timing Measurement: # --------------------------------------------------------------------------------------- # # "A" Hemisphere Interposer #1 to AD9546 Auxiliary input M1 # "B" Hemisphere Interposer #2 to AD9546 Auxiliary input M2 # # # The FLASH-TDC signals arrive as 3V3 CMOS and are converted to 1V8 CMOS # by the Level Translator U1456 and then sent via Series Terminator resistors # R1494 and R1495 to the M1 and M2 inputs of the Timing Generator for TDC. # # The Direction pin of the Level Translator is LOW --> B is Input A is Output # VccA is 1V8 VccB is 3V3 # # ---------------------------------------------------------------------------------------- # NET 'Interposer_1_Flash_TDC' U1456-7 # 3V3 Flash-TDC signal from Interposer #1 NET 'INTERP_1_Flash_TDC_Term' U1456-2 R1494-2 # Flash TDC Trans Term for "A" Hemisphere NET 'TG_Aux_In_M1' R1494-1 # Flash TDC from "A" Hemisphere to the # "M1" input of the AD9546 Timing Generator # for time measurement a 1V8 CMOS signal NET 'Interposer_2_Flash_TDC' U1456-6 # 3V3 Flash-TDC signal from Interposer #2 NET 'INTERP_2_Flash_TDC_Term' U1456-3 R1495-2 # Flash TDC Trans Term for "B" Hemisphere NET 'TG_Aux_In_M2' R1495-1 # Flash TDC from "B" Hemisphere to the # "M2" input of the AD9546 Timing Generator # for time measurement a 1V8 CMOS signal NET 'GROUND' U1456-4 U1456-5 # Ground the Level Translator Ground pin # and Ground its DIR pin ---> B is Input A is Output NET 'BULK_1V8' U1456-1 C1485-2 # Bulk_1V8 to the VccA pin on the translator NET 'GROUND' C1485-1 # Ground the bypass capacitors NET 'BULK_3V3' U1456-8 C1486-2 # Bulk_3V3 to the VccB pin on the translator NET 'GROUND' C1486-1 # Ground the bypass capacitors # # Muon Scintillator S1 S2 S3 S4 signals # from "B" Hemishpere to the FPGA/CPU "TDCs": # ---------------------------------------------------------------------------------- # # The Muon Scintillator signals arrive on Interposer #2 connector J5 # as 3V3 CMOS signals. I need to use some type of Receiver so I'm # Translating them to 1V8 CMOS signals because I currently have more # Floating pins available in Bank #9 (1V8) than in Banks #1 or #7 (3V3). # # There are series terminator resistors at the outputs of the # Level Translators and from these series terminators the Muon signals # run to floating pins in Bank #9. # # The Direction pin of the Level Translator is LOW --> B is Input A is Output # VccA is 1V8 VccB is 3V3 # # ---------------------------------------------------------------------------------- # NET 'Interposer_2_Muon_S1' U1457-7 # 3V3 Muon-S1 signal from Interposer #2 NET 'INTERP_2_Muon_S1_Term' U1457-2 R1496-2 # Muon-S1 Trans Term for "B" Hemisphere NET 'Muon_S1_B_Hemi' R1496-1 # Muon S1 from "B" Hemisphere to the # FPGA/CPU Bank #9 as 1V8 CMOS for TDC. NET 'Interposer_2_Muon_S2' U1457-6 # 3V3 Muon S2 signal from Interposer #2 NET 'INTERP_2_Muon_S2_Term' U1457-3 R1497-2 # Muon S2 Trans Term for "B" Hemisphere NET 'Muon_S2_B_Hemi' R1497-1 # Muon S2 from "B" Hemisphere to the # FPGA/CPU Bank #9 as 1V8 CMOS for TDC. NET 'GROUND' U1457-4 U1457-5 # Ground the Level Translator Ground pin # and Ground its DIR pin ---> B is Input A is Output NET 'BULK_1V8' U1457-1 C1487-2 # Bulk_1V8 to the VccA pin on the translator NET 'GROUND' C1487-1 # Ground the bypass capacitors NET 'BULK_3V3' U1457-8 C1488-2 # Bulk_3V3 to the VccB pin on the translator NET 'GROUND' C1488-1 # Ground the bypass capacitors NET 'Interposer_2_Muon_S3' U1458-7 # 3V3 Muon-S3 signal from Interposer #2 NET 'INTERP_2_Muon_S3_Term' U1458-2 R1498-2 # Muon-S3 Trans Term for "B" Hemisphere NET 'Muon_S3_B_Hemi' R1498-1 # Muon S3 from "B" Hemisphere to the # FPGA/CPU Bank #9 as 1V8 CMOS for TDC. NET 'Interposer_2_Muon_S4' U1458-6 # 3V3 Muon S4 signal from Interposer #2 NET 'INTERP_2_Muon_S4_Term' U1458-3 R1499-2 # Muon S4 Trans Term for "B" Hemisphere NET 'Muon_S4_B_Hemi' R1499-1 # Muon S4 from "B" Hemisphere to the # FPGA/CPU Bank #9 as 1V8 CMOS for TDC. NET 'GROUND' U1458-4 U1458-5 # Ground the Level Translator Ground pin # and Ground its DIR pin ---> B is Input A is Output NET 'BULK_1V8' U1458-1 C1489-2 # Bulk_1V8 to the VccA pin on the translator NET 'GROUND' C1489-1 # Ground the bypass capacitors NET 'BULK_3V3' U1458-8 C1490-2 # Bulk_3V3 to the VccB pin on the translator NET 'GROUND' C1490-1 # Ground the bypass capacitors # # Power Feeds to the Interposers - Isolation Filters and Bypass Capacitors # ---------------------------------------------------------------------------- # # Interposer #1 1V8 Power # -------------------------- NET 'BULK_1V8' C1461-2 L1461-2 # BULK_1V8 Feed to the Filter NET 'INTERP_1_1V8' C1462-2 L1461-1 J4-1 J4-2 # Interposer #1 1V8 Power NET 'GROUND' C1461-1 C1462-1 # Ground Anchor for the Caps # Interposer #1 3V3 Power # -------------------------- NET 'BULK_3V3' C1463-1 L1462-1 # BULK_3V3 Feed to the Filter NET 'INTERP_1_3V3' C1464-1 L1462-2 J4-3 J4-4 # Interposer #1 3V3 Power NET 'GROUND' C1463-2 C1464-2 # Ground Anchor for the Caps # Interposer #1 5V0 Power # -------------------------- NET 'BULK_5V0' C1465-1 L1463-1 # BULK_5V0 Feed to the Filter NET 'INTERP_1_5V0' C1466-1 L1463-2 J4-39 J4-40 # Interposer #1 5V0 Power NET 'GROUND' C1465-2 C1466-2 # Ground Anchor for the Caps # Interposer #2 1V8 Power # -------------------------- NET 'BULK_1V8' C1471-1 L1471-1 # BULK_1V8 Feed to the Filter NET 'INTERP_2_1V8' C1472-1 L1471-2 J5-1 J5-2 # Interposer #2 1V8 Power NET 'GROUND' C1471-2 C1472-2 # Ground Anchor for the Caps # Interposer #2 3V3 Power # -------------------------- NET 'BULK_3V3' C1473-2 L1472-2 # BULK_3V3 Feed to the Filter NET 'INTERP_2_3V3' C1474-2 L1472-1 J5-3 J5-4 # Interposer #2 3V3 Power NET 'GROUND' C1473-1 C1474-1 # Ground Anchor for the Caps # Interposer #2 5V0 Power # -------------------------- NET 'BULK_5V0' C1475-2 L1473-2 # BULK_5V0 Feed to the Filter NET 'INTERP_2_5V0' C1476-2 L1473-1 J5-39 J5-40 # Interposer #2 5V0 Power NET 'GROUND' C1475-1 C1476-1 # Ground Anchor for the Caps # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # # fpga_cpu_floating_connection_nets.txt # # ---------------------------------------------------- # # # All of these are 1V8 signals: CPU UART Data to/from both Interposers # ---------------------------------------------------------------------------- # # NET 'CPU_UART_Tx_to_INTERP_1' # Tx UART Data to Interposer_1 via Buffer # NET 'CPU_UART_Rx_from_INTERP_1' # Rx UART Data from Interposer_1 via Buffer # # NET 'CPU_UART_Tx_to_INTERP_2' # Tx UART Data to Interposer_2 via Buffer # NET 'CPU_UART_Rx_from_INTERP_2' # Rx UART Data from Interposer_2 via Buffer # # # # All of these are 1V8 signals: Flash-Now to both Interposers and to AD9546 # SMUT S1...S4 from only "B" Interposer to FPGA # ------------------------------------------------------------------------------------- # # NET 'Flash_Now' # Flash_Now from the FPGA/CPU to both # # Interposers and to the AD9546 for TDC # # # Muon Scintillator 1V8 signals to the FPGA/CPU # # NET 'Muon_S1_B_Hemi' # Muon signal S1 from "B" Hemisphere to FPGA/CPU # NET 'Muon_S2_B_Hemi' # Muon signal S2 from "B" Hemisphere to FPGA/CPU # NET 'Muon_S3_B_Hemi' # Muon signal S3 from "B" Hemisphere to FPGA/CPU # NET 'Muon_S4_B_Hemi' # Muon signal S4 from "B" Hemisphere to FPGA/CPU #