# # Interposer All Other Nets # -------------===========------- # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 4-Dec-2023 # Current Rev. 27-Dec-2023 # # # # This net list holds the Interposer All Other Nets # ------------===========----- # # The components for the # DK's Interposer All Other Nets # are in the range 1451 to 1499. # # # NOTE: that 2 sections of the U1459 hex inverter, which # is shown lower in this file, are used in a different # net list file to handle the Interposer SPI Mux Control # signals. # # # PIEZO Hydrophone Connection to the BB Audio ADC Inputs # ----------------------------------------------------------- # # This connection is made in the: # # interposer_connectors_all_nets.txt # and the bb_audio_adc_nets.txt files. # # # Nets for the Interposer 1V8 UART Buffers: # ------------------------------------------------- # # Interposer #1 Serviced by CPU MMUART #3 # --------------------------------------------- NET 'CPU_UART_3_Tx__to__Poser_1' R1483-1 # DK CPU UART 3 Tx Data to Terminator NET 'Tx_to_Poser_1_Term_Buf' R1483-2 U1454-3 # DK CPU UART Tx Data to Data Buffer NET 'CPU_UART_Tx_to_Poser_1_B' U1454-4 U1454-5 # Inverted NET 'Data_to_Poser_1_Buf_Term' U1454-6 R1484-1 # Tx Data to the DK Tx Terminator NET 'DK_Tx_Data_to_Poser_1' R1484-2 J4-31 # Tx Data to the Poser_1 Connector NET 'DK_Rx_Data_from_Poser_1' J4-32 U1454-11 # Rx Data from the Poser_1 Connector NET 'DK_Rx_Data_from_Poser_1_B' U1454-10 U1454-9 # Inverted NET 'DK_Rx_Data_Psr_1_to_Term' U1454-8 R1485-1 # Rx Data from the Poser_1 to Term NET 'CPU_UART_3_Rx_from_Poser_1' R1485-2 # Rx Data from the Poser_1 via Buf # and Term to the DK's CPU UART #3 NET 'GROUND' U1454-1 U1454-13 # Tie down unused buffer inputs NET 'BULK_1V8' U1454-14 C1454-1 # 1V8 Power for UART Buffer NET 'GROUND' U1454-7 C1454-2 # Ground for the UART Buffer # Interposer #2 Serviced by CPU MMUART #4 # --------------------------------------------- NET 'CPU_UART_4_Tx__to__Poser_2' R1486-1 # DK CPU UART 4 Tx Data to Terminator NET 'Tx_to_Poser_2_Term_Buf' R1486-2 U1455-3 # DK CPU UART Tx Data to Data Buffer NET 'CPU_UART_Tx_to_Poser_2_B' U1455-4 U1455-5 # Inverted NET 'Data_to_Poser_2_Buf_Term' U1455-6 R1487-1 # Tx Data to the DK Tx Terminator NET 'DK_Tx_Data_to_Poser_2' R1487-2 J5-31 # Tx Data to the Poser_2 Connector NET 'DK_Rx_Data_from_Poser_2' J5-32 U1455-11 # Rx Data from the Poser_2 Connector NET 'DK_Rx_Data_from_Poser_2_B' U1455-10 U1455-9 # Inverted NET 'DK_Rx_Data_Psr_2_to_Term' U1455-8 R1488-1 # Rx Data from the Poser_2 to Term NET 'CPU_UART_4_Rx_from_Poser_2' R1488-2 # Rx Data from the Poser_2 via Buf # and Term to the DK's CPU UART #4 NET 'GROUND' U1455-1 U1455-13 # Tie down unused buffer inputs NET 'BULK_1V8' U1455-14 C1455-1 # 1V8 Power for UART Buffer NET 'GROUND' U1455-7 C1455-2 # Ground for the UART Buffer # # FLASH-NOW Signal from FPGA/CPU to Both Interposers and to the AD9546 TG: # ---------------------------------------------------------------------------------- # NET 'Flash_Now' R1490-2 R1491-2 # Flash_Now signal from the FPGA/CPU # This is a 3V3 CMOS single ended signal # from a "floating" pin on the FPGA/CPU # to a pair of series terminators. NET 'TG_Aux_In_M1' R1490-1 # Flash_Now from the FPGA/CPU to the "M1" Auxiliary Input # of the AD9546 Timing Generator for timing measurement. NET 'Flash_Now_to_Interposers' R1491-1 # Flash_Now from series terminator NET 'Flash_Now_to_Interposers' U1456-5 U1457-5 # to the LVDS Flash Now Drivers inputs NET 'Poser_1_Flash_Now_Dir' U1456-4 J4-7 # Flash Now DIR to This Hemisphere NET 'Poser_1_Flash_Now_Cmp' U1456-3 J4-8 # Flash Now CMP to This Hemisphere NET 'Poser_2_Flash_Now_Dir' U1457-4 J5-7 # Flash Now DIR to Other Hemisphere NET 'Poser_2_Flash_Now_Cmp' U1457-3 J5-8 # Flash Now CMP to Other Hemisphere NET 'BULK_3V3' U1456-1 U1457-1 # Bulk_3V3 to the LVDS Driver chips NET 'GROUND' U1456-2 U1457-2 # Ground to the LVDS Driver chips NET 'BULK_3V3' C1481-1 C1482-2 C1483-2 # Bulk_3V3 to the Bypass Caps NET 'GROUND' C1481-2 C1482-1 C1483-1 # Ground to the Bypass Caps # # FLASH-TDC signals from Both Interposers to the AD9546 for Timing Measurement: # ---------------------------------------------------------------------------------------- # NET 'Poser_1_Flash_TDC_In' J4-15 U1458-3 # Flash TDC Input from This Hemisphere NET 'Poser_1_Flash_TDC_Link' U1458-4 U1458-5 # Flash TDC Buf Link This Hemisphere NET 'Poser_1_Flash_TDC_Term' U1458-6 R1493-1 # Flash TDC Buf Term This Hemisphere NET 'TG_Aux_In_M2' R1493-2 # Flash TDC from This Hemisphere to the # "M2" input of the AD9546 Timing Generator # for time measurement a 3V3 CMOS signal NET 'Poser_2_Flash_TDC_In' J5-15 U1458-11 # Flash TDC Input from Other Hemisphere NET 'Poser_2_Flash_TDC_Link' U1458-10 U1458-9 # Flash TDC Bus Link Other Hemisphere NET 'Poser_2_Flash_TDC_Term' U1458-8 R1492-1 # Flash TDC Buf Term Other Hemisphere NET 'TG_Aux_In_M3' R1492-2 # Flash TDC from Other Hemisphere to the # "M3" input of the AD9546 Timing Generator # for time measurement a 3V3 CMOS signal NET 'BULK_3V3' U1458-14 C1484-2 # Bulk_3V3 to the Buffer and Bypass caps NET 'GROUND' U1458-7 C1484-1 # Ground to the buffer and Bypass caps # # Interposer Controller Reset from FPGA/CPU to Both Interposers: # ---------------------------------------------------------------------------- # NET 'Interposer_Ctrl_Reset' R1494-2 # Interposer Ctrl Reset from FPGA/CPU NET 'POSER_Reset_Term_to_Buf' R1494-1 U1458-1 U1458-13 # Series Term to Buffer Inputs NET 'POSER_1_Ctrl_Reset' U1458-2 J4-19 # Control Reset to Interposer This Hemisphere NET 'POSER_2_Ctrl_Reset' U1458-12 J5-19 # Control Reset to Interposer Other Hemisphere # # Muon SMUT S1 S2 S3 S4 signals from Other Hemishpere to the FPGA/CPU "TDCs": # --------------------------------------------------------------------------------------- # # # NOTE: that most of the U1459 hex inverter is used by the # following Muon SMUT signals but 2 sections of the # U1459 hex inverter are used in a different net list # file to handle the Interposer SPI Mux Control Lines. # NET 'SMUT_S1_Other_Hemi' J5-33 U1459-3 # Muon SMUT signal S1 from Other Hemisphere NET 'SMUT_S2_Other_Hemi' J5-35 U1459-5 # Muon SMUT signal S2 from Other Hemisphere NET 'SMUT_S3_Other_Hemi' J5-36 U1459-9 # Muon SMUT signal S3 from Other Hemisphere NET 'SMUT_S4_Other_Hemi' J5-37 U1459-11 # Muon SMUT signal S4 from Other Hemisphere NET 'Muon_S1_Other_Term' U1459-4 R1498-1 # SMUT Muon S1 Other Hemi to Term --> FPGA/CPU "TDC" NET 'Muon_S2_Other_Term' U1459-6 R1497-1 # SMUT Muon S2 Other Hemi to Term --> FPGA/CPU "TDC" NET 'Muon_S3_Other_Term' U1459-8 R1496-1 # SMUT Muon S3 Other Hemi to Term --> FPGA/CPU "TDC" NET 'Muon_S4_Other_Term' U1459-10 R1495-1 # SMUT Muon S4 Other Hemi to Term --> FPGA/CPU "TDC" NET 'Muon_S1_Other_Hemi' R1498-2 # SMUT Muon S1 Other Hemi to FPGA/CPU "TDC" NET 'Muon_S2_Other_Hemi' R1497-2 # SMUT Muon S2 Other Hemi to FPGA/CPU "TDC" NET 'Muon_S3_Other_Hemi' R1496-2 # SMUT Muon S3 Other Hemi to FPGA/CPU "TDC" NET 'Muon_S4_Other_Hemi' R1495-2 # SMUT Muon S4 Other Hemi to FPGA/CPU "TDC" NET 'NO_CONN_This_Hemi_SMUT_S1_J4_pin_33' J4-33 # No SMUT S1 in This Hemisphere NET 'NO_CONN_This_Hemi_SMUT_S2_J4_pin_35' J4-35 # No SMUT S2 in This Hemisphere NET 'NO_CONN_This_Hemi_SMUT_S3_J4_pin_36' J4-36 # No SMUT S3 in This Hemisphere NET 'NO_CONN_This_Hemi_SMUT_S4_J4_pin_37' J4-37 # No SMUT S4 in This Hemisphere NET 'BULK_3V3' U1459-14 C1485-2 # Bulk_3V3 to the Buffer and Bypass caps NET 'GROUND' U1459-7 C1485-1 # Ground to the buffer and Bypass caps # # Power Feeds to the Interposers - Isolation Filters and Bypass Capacitors # ---------------------------------------------------------------------------- # # Poser #1 1V8 Power # --------------------- NET 'BULK_1V8' C1461-2 L1461-1 # BULK_1V8 Feed to the Filter NET 'POSER_1_1V8' C1462-2 L1461-2 J4-1 J4-2 # POSER #1 1V8 Power NET 'GROUND' C1461-1 C1462-1 # Ground Anchor for the Caps # Poser #1 3V3 Power # --------------------- NET 'BULK_3V3' C1463-2 L1462-1 # BULK_3V3 Feed to the Filter NET 'POSER_1_3V3' C1464-2 L1462-2 J4-3 J4-4 # POSER #1 3V3 Power NET 'GROUND' C1463-1 C1464-1 # Ground Anchor for the Caps # Poser #1 5V0 Power # --------------------- NET 'BULK_5V0' C1465-2 L1463-1 # BULK_5V0 Feed to the Filter NET 'POSER_1_5V0' C1466-1 L1463-2 J4-39 J4-40 # POSER #1 5V0 Power NET 'GROUND' C1465-1 C1466-2 # Ground Anchor for the Caps # Poser #2 1V8 Power # --------------------- NET 'BULK_1V8' C1471-2 L1471-1 # BULK_1V8 Feed to the Filter NET 'POSER_2_1V8' C1472-1 L1471-2 J5-1 J5-2 # POSER #2 1V8 Power NET 'GROUND' C1471-1 C1472-2 # Ground Anchor for the Caps # Poser #2 3V3 Power # --------------------- NET 'BULK_3V3' C1473-2 L1472-1 # BULK_3V3 Feed to the Filter NET 'POSER_2_3V3' C1474-1 L1472-2 J5-3 J5-4 # POSER #2 3V3 Power NET 'GROUND' C1473-1 C1474-2 # Ground Anchor for the Caps # Poser #2 5V0 Power # --------------------- NET 'BULK_5V0' C1475-2 L1473-1 # BULK_5V0 Feed to the Filter NET 'POSER_2_5V0' C1476-2 L1473-2 J5-39 J5-40 # POSER #2 5V0 Power NET 'GROUND' C1475-1 C1476-1 # Ground Anchor for the Caps # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are 1V8 signals: CPU UART Data to/from both Interposers # ---------------------------------------------------------------------------- # # NET 'CPU_UART_Tx__to__Poser_1' # Tx UART Data to Interposer_1 via Buffer # NET 'CPU_UART_Rx_from_Poser_1' # Rx UART Data from Interposer_1 via Buffer # # NET 'CPU_UART_Tx__to__Poser_2' # Tx UART Data to Interposer_2 via Buffer # NET 'CPU_UART_Rx_from_Poser_2' # Rx UART Data from Interposer_2 via Buffer # # # # All of these are 3V3 signals: Flash-Now to both Interposers and to AD9546 # Control-Reset to both Interposers # SMUT S1...S4 from only Other Interposer to FPGA # ------------------------------------------------------------------------------------- # # NET 'Flash_Now' # Flash_Now from the FPGA/CPU to both # # Interposers and to the AD9546 for # # time measurement a 3V3 CMOS signal # # NET 'Interposer_Ctrl_Reset' # Control Reset to Both Interposers from FPGA/CPU # # NET 'Muon_S1_Other_Hemi' # Muon SMUT signal S1 from Other Hemisphere to FPGA/CPU # NET 'Muon_S2_Other_Hemi' # Muon SMUT signal S2 from Other Hemisphere to FPGA/CPU # NET 'Muon_S3_Other_Hemi' # Muon SMUT signal S3 from Other Hemisphere to FPGA/CPU # NET 'Muon_S4_Other_Hemi' # Muon SMUT signal S4 from Other Hemisphere to FPGA/CPU #