# # Interposer All SPI Nets # ------------------------------ # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 30-Nov-2023 # Current Rev. 21-Dec-2023 # # # # This net list holds the Interposer All SPI Nets # ---------------------------- # # The components for the # DK's Interposer All SPI Nets # are in the range 1451 to 1499. # # # NOTE: that 2 sections of the U1459 hex inverter, which # officially belongs to the Interposer_All_Other net # list file where is is used to handle the Muon SMUT signals, # is used in this net list file to handle inverting the # Interposer SPI Mux Control signals. # # # SPI Signals Mux to Interposer #1 Connector J4: # --------------------------------------------------- # NET 'Poser_1_Conn_SCLK' R1453-2 # SCLK Series Term to Poser #1 Conn NET 'Poser_1_Drv_SCLK' U1451-18 R1453-1 R1461-1 # SCLK Driver to Ser Term & Pull_Dwn NET 'Poser_1_Conn_MOSI' R1454-2 # MOSI Series Term to Poser #1 Conn NET 'Poser_1_Drv_MOSI' U1451-16 R1454-1 R1462-1 # MOSI Driver to Ser Term & Pull_Dwn NET 'Poser_1_Conn_MISO' U1451-6 R1463-2 # MISO Poser #1 Conn to Pull-Down & Receiver NET 'Poser_1_Conn_CS_B' U1451-12 R1481-2 # CS_B Driver & Pull-Up to Poser #1 Conn NET 'Poser_1_Conn_CS_A0' U1451-9 R1464-2 # CS_A0 Driver & Pull-Up to Poser #1 Conn NET 'Poser_1_Conn_CS_A1' U1451-7 R1465-2 # CS_A1 Driver & Pull-Up to Poser #1 Conn NET 'Poser_1_Conn_CS_A2' U1451-5 R1466-2 # CS_A2 Driver & Pull-Up to Poser #1 Conn NET 'BULK_3V3' R1481-1 # Pull-Up Source NET 'GROUND' R1461-2 R1462-2 R1463-1 # Pull-Down Anchor NET 'GROUND' R1464-1 R1465-1 R1466-1 # Pull-Down Anchor # # SPI Signals Mux to Interposer #2 Connector J5: # --------------------------------------------------- # NET 'Poser_2_Conn_SCLK' R1455-2 # SCLK Series Term to Poser #2 Conn NET 'Poser_2_Drv_SCLK' U1452-18 R1455-1 R1467-1 # SCLK Driver to Ser Term & Pull_Dwn NET 'Poser_2_Conn_MOSI' R1456-2 # MOSI Series Term to Poser #2 Conn NET 'Poser_2_Drv_MOSI' U1452-16 R1456-1 R1468-1 # MOSI Driver to Ser Term & Pull_Dwn NET 'Poser_2_Conn_MISO' U1452-6 R1469-2 # MISO Poser #2 Conn to Pull-Down & Receiver NET 'Poser_2_Conn_CS_B' U1452-12 R1482-2 # CS_B Driver & Pull-Up to Poser #2 Conn NET 'Poser_2_Conn_CS_A0' U1452-9 R1470-2 # CS_A0 Driver & Pull-Up to Poser #2 Conn NET 'Poser_2_Conn_CS_A1' U1452-7 R1471-2 # CS_A1 Driver & Pull-Up to Poser #2 Conn NET 'Poser_2_Conn_CS_A2' U1452-5 R1472-2 # CS_A2 Driver & Pull-Up to Poser #2 Conn NET 'BULK_3V3' R1482-1 # Pull-Up Source NET 'GROUND' R1467-2 R1468-2 R1469-1 # Pull-Down Anchor NET 'GROUND' R1470-1 R1471-1 R1472-1 # Pull-Down Anchor # # SPI Signals FPGA to/from Multiplexer: # -------------------------------------------- # NET 'Poser_SCLK_FPGA_to_Term' R1451-1 # SCLK FPGA to Series Term NET 'Poser_SCLK_Term_to_Mux' R1451-2 U1451-2 U1452-2 # SCLK Series Term to Mux NET 'Poser_MOSI_FPGA_to_Term' R1452-1 # MOSI FPGA to Series Term NET 'Poser_MOSI_Term_to_Mux' R1452-2 U1451-4 U1452-4 # MOSI Series Term to Mux NET 'Poser_MISO_Mux_to_Term' U1451-14 U1452-14 R1457-1 # MISO Mux to Term NET 'Poser_MISO_Mux_to_Term' R1473-1 # MISO Mux to Pull-Dwn NET 'Poser_MISO_Term_to_FPGA' R1457-2 # MISO Mux Term to FPGA NET 'GROUND' R1473-2 # Pull-Down Anchor # # Mux Control Signals FPGA to Multiplexer (via an inverter where necessary): # --------------------------------------------------------------------------------- # # NOTE: the use of hex inverter U1459 to handle the inversion # of the SPI Mux Control signals. Hex inverter U1459 # officially belongs to the Interposer All Other net list # file where it handles Muon SMUT signals. # NET 'Poser_CS_1_B' U1451-1 U1459-1 # FPGA to Enable one half Interposer #1 Mux _B NET 'Poser_CS_1' U1459-2 U1451-19 # Inverter to Enable other half Interposer #1 Mux NET 'Poser_CS_2_B' U1452-1 U1459-13 # FPGA to Enable one half Interposer #2 Mux _B NET 'Poser_CS_2' U1459-12 U1452-19 # Inverter to Enable other half Interposer #2 Mux # # CS Address Signals FPGA to Multiplexer: # --------------------------------------------- # NET 'Poser_CS_Adrs_0' U1451-11 U1452-11 # CS Address 0 FPGA to Mux NET 'Poser_CS_Adrs_1' U1451-13 U1452-13 # CS Address 1 FPGA to Mux NET 'Poser_CS_Adrs_2' U1451-15 U1452-15 # CS Address 2 FPGA to Mux # # Tie-Down All Unused CMOS Inputs: # -------------------------------------- # NET 'GROUND' U1451-17 U1452-17 # Tie-Down the Input to the # Unused Section of the Mux # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # fpga_cpu_floating_connection_nets.txt # ---------------------------------------------------- # # # All of these are 3V3 signals: SPI Bus and GPIO # ------------------------------------------------- # # NET 'Poser_SCLK_FPGA_to_Term' # SCLK FPGA to Series Term # NET 'Poser_MOSI_FPGA_to_Term' # MOSI FPGA to Series Term # NET 'Poser_MISO_Term_to_FPGA' # MISO Mux Term to FPGA # # NET 'Poser_CS_1_B' # FPGA Signal to Enable Interposer #1 Mux _B # NET 'Poser_CS_2_B' # FPGA Signal to Enable Interposer #2 Mux _B # # NET 'Poser_CS_Adrs_0' # CS Address 0 FPGA to Mux # NET 'Poser_CS_Adrs_1' # CS Address 1 FPGA to Mux # NET 'Poser_CS_Adrs_2' # CS Address 2 FPGA to Mux # # # 3.3 Volt Power and Grounds to the Interposer SPI Buffe Chips: # ------------------------------------------------------------------ # NET 'BULK_3V3' U1451-20 U1452-20 # 3V3 Power to the Buffer Chips NET 'GROUND' U1451-10 U1452-10 # Ground pins on the Buffer Chips NET 'BULK_3V3' C1451-2 C1452-2 # 3V3 Bypass Caps NET 'GROUND' C1451-1 C1452-1 # Ground Side of Bypass Caps