# # Interposer All SPI Nets # ------------------------------ # # # Disco-Kraken Key In Net List # ------------------------------- # # # Initial Rev. 30-Nov-2023 # Current Rev. 25-July-2024 # # # # This net list holds the Interposer All SPI Nets # ---------------------------- # # # The components for the SPI Bus and Address Bus Interface # to the Interposers are in the range 1451 to 1499. # # The SPI Bus & Address Bus pins on the Interposer Connectors J4 & J5 # are assigned Nets in the file: interposer_connectors_all_nets.txt # # This Nets File assigns 8 Floating Pins to the FPGA/CPU # See the end of this file. # # # The wiring of the Interposer "A" and Interposer "B" circuits are # functionally equivalent but do differ in physical layout and in # which section of their 74LVC244 is used to handle a given signal. # # Interposer #1 aka "A" J4 Connector: # ------------------------------------- # 74LVC244 Pin # ----------------- # J5 Pull Up/Down Series Term to Interposer # Pin Signal Resistor Resistor FPGA Connector # --- -------- ---------- ---------- ---- --------- # # 18 SCLK R1461 R1451 8 12 # 19 Ctrl_Reset_B R1468 --- 13 7 # 20 MISO R1463 9 * 11 # 22 MOSI R1462 R1452 6 14 # 23 A0 R1465 --- 15 5 # 24 CS_B R1464 --- 4 16 # 27 A2 R1467 --- 2 18 # 28 A1 R1466 --- 17 3 # # # * Note that all signal are from the FPGA to the Interposer # except for MISO which is the other direction. For the MISO # signal only, the Interposer connects to a 74LVC244 Input and # the output from that 74LVC244 section connects to the FPGA. # # # Interposer #2 aka "B" J5 Connector: # ------------------------------------- # 74LVC244 Pin # ----------------- # J5 Pull Up/Down Series Term to Interposer # Pin Signal Resistor Resistor FPGA Connector # --- -------- ---------- ---------- ---- --------- # 28 A1 R1474 --- 11 9 # 27 A2 R1475 --- 8 12 # 24 CS_B R1472 --- 6 14 # 23 A0 R1473 --- 13 7 # 22 MOSI R1470 R1454 4 16 # 20 MISO R1471 3 * 17 # 19 Ctrl_Reset_B R1476 --- 15 5 # 18 SCLK R1469 R1453 2 18 # # # * Note that all signal are from the FPGA to the Interposer # except for MISO which is the other direction. For the MISO # signal only, the Interposer connects to a 74LVC244 Input and # the output from that 74LVC244 section connects to the FPGA. # # # For reference the 74LVC244 Input and Output Pins are: # # Input Output # ----- ------ # 2 18 # 4 16 # 6 14 # 8 12 # # 11 9 # 13 7 # 15 5 # 17 3 # # # # SPI Signals from/to FPGA to/from Interposer #1 Connector J4: # --------------------------------------------------------------------- # NET 'INTERP_1_SCLK' U1451-8 # SCLK signal from FPGA to Driver NET 'INTERP_1_Drv_SCLK' U1451-12 R1461-2 R1451-1 # SCLK Driver to Series Term & Pull_Dwn NET 'INTERP_1_Conn_SCLK' R1451-2 # SCLK Series Term to Poser #1 Conn J4 NET 'INTERP_1_MOSI' U1451-6 # MOSI signal from FPGA to Driver NET 'INTERP_1_Drv_MOSI' U1451-14 R1462-2 R1452-1 # MOSI Driver to Series Term & Pull_Dwn NET 'INTERP_1_Conn_MOSI' R1452-2 # MOSI Series Term to Poser #1 Conn J4 NET 'INTERP_1_Conn_MISO' U1451-11 # MISO signal from Interposer #1 to Receiver NET 'INTERP_1_MISO' U1451-9 R1463-2 # MISO signal from Receiver to FPGA & Pull-Down NET 'INTERP_1_CS_B' U1451-4 # CS_B signal from FPGA to Driver NET 'INTERP_1_Conn_CS_B' U1451-16 R1464-2 # CS_B Driver & Pull-Up to Poser #1 Conn J4 NET 'BULK_3V3' R1464-1 # Pull-Up Source NET 'GROUND' R1461-1 R1462-1 R1463-1 # Pull-Down Anchor # # Address Signals from FPGA to Interposer #1 Connector J4: # --------------------------------------------------------------- # NET 'INTERP_1_CS_Adrs_0' U1451-15 # CS Address 0 signal from FPGA to Driver NET 'INTERP_1_Conn_CS_A0' U1451-5 R1465-2 # CS_A0 Driver & Pull-Down to Poser #1 Conn J4 NET 'INTERP_1_CS_Adrs_1' U1451-17 # CS Address 1 signal from FPGA to Driver NET 'INTERP_1_Conn_CS_A1' U1451-3 R1466-2 # CS_A1 Driver & Pull-Down to Poser #1 Conn J4 NET 'INTERP_1_CS_Adrs_2' U1451-2 # CS Address 2 signal from FPGA to Driver NET 'INTERP_1_Conn_CS_A2' U1451-18 R1467-2 # CS_A2 Driver & Pull-Down to Poser #1 Conn J4 NET 'INTERP_1_CTRL_Reset_B' U1451-13 # CTRL_Reset_B signal from FPGA to Driver NET 'INTERP_1_Conn_CTRL_Reset_B' U1451-7 R1468-2 # CTRL_Reset_B Driver & Pull_Down to Poser #1 Conn J4 NET 'GROUND' R1465-1 R1466-1 R1467-1 R1468-1 # Pull-Down Anchor # # SPI Signals from/to FPGA to/from Interposer #2 Connector J5: # --------------------------------------------------------------------- # NET 'INTERP_2_SCLK' U1452-2 # SCLK signal from FPGA to Driver NET 'INTERP_2_Drv_SCLK' U1452-18 R1469-2 R1453-1 # SCLK Driver to Series Term & Pull_Dwn NET 'INTERP_2_Conn_SCLK' R1453-2 # SCLK Series Term to Poser #2 Conn J5 NET 'INTERP_2_MOSI' U1452-4 # MOSI signal from FPGA to Driver NET 'INTERP_2_Drv_MOSI' U1452-16 R1470-2 R1454-1 # MOSI Driver to Series Term & Pull_Dwn NET 'INTERP_2_Conn_MOSI' R1454-2 # MOSI Series Term to Poser #2 Conn J5 NET 'INTERP_2_Conn_MISO' U1452-17 # MISO signal from Interposer #2 to Receiver NET 'INTERP_2_MISO' U1452-3 R1471-1 # MISO signal from Receiver to FPGA & Pull-Down NET 'INTERP_2_CS_B' U1452-6 # CS_B signal from FPGA to Driver NET 'INTERP_2_Conn_CS_B' U1452-14 R1472-2 # CS_B Driver & Pull-Up to Poser #2 Conn J5 NET 'BULK_3V3' R1472-1 # Pull-Up Source NET 'GROUND' R1469-1 R1470-1 R1471-2 # Pull-Down Anchor # # Address Signals from FPGA to Interposer #2 Connector J5: # --------------------------------------------------------------- # NET 'INTERP_2_CS_Adrs_0' U1452-13 # CS Address 0 signal from FPGA to Driver NET 'INTERP_2_Conn_CS_A0' U1452-7 R1473-2 # CS_A0 Driver & Pull-Down to Poser #2 Conn J5 NET 'INTERP_2_CS_Adrs_1' U1452-11 # CS Address 1 signal from FPGA to Driver NET 'INTERP_2_Conn_CS_A1' U1452-9 R1474-2 # CS_A1 Driver & Pull-Down to Poser #2 Conn J5 NET 'INTERP_2_CS_Adrs_2' U1452-8 # CS Address 2 signal from FPGA to Driver NET 'INTERP_2_Conn_CS_A2' U1452-12 R1475-2 # CS_A2 Driver & Pull-Down to Poser #2 Conn J5 NET 'INTERP_2_CTRL_Reset_B' U1452-15 # CTRL_Reset_B signal from FPGA to Driver NET 'INTERP_2_Conn_CTRL_Reset_B' U1452-5 R1476-2 # CTRL_Reset_B Driver & Pull_Down to Poser #2 Conn J5 NET 'GROUND' R1473-1 R1474-1 R1475-1 R1476-1 # Pull-Down Anchor # # Interposer SPI and Address Buffers Enable B: # ------------------------------------------------- # NET 'DK_CPU_IS_SANE' U1156-13 # From the Startup Reset/Enable Circuits Drw 51 NET 'INTERP_SPI_ADRS_BUF_ENB_B' U1156-12 # Once the DK CPU is Sane then NET 'INTERP_SPI_ADRS_BUF_ENB_B' U1451-1 U1451-19 # Enable the SPI Bus and Address Bus NET 'INTERP_SPI_ADRS_BUF_ENB_B' U1452-1 U1452-19 # Buffers for Interposers #1 and #2 # # 3.3 Volt Power and Grounds to the Interposer SPI Buffer Chips: # ------------------------------------------------------------------- # NET 'BULK_3V3' U1451-20 U1452-20 # 3V3 Power to the Buffer Chips NET 'GROUND' U1451-10 U1452-10 # Ground pins on the Buffer Chips NET 'BULK_3V3' C1451-2 C1452-2 # 3V3 Bypass Caps NET 'GROUND' C1451-1 C1452-1 # Ground Side of Bypass Caps # # List the NetNames of the Signals that must be # connected to FPGA Floating Pins. Here just list # the NetNames - the actual connections to these # FPGA Floating pins are made in the Nets File: # # fpga_cpu_floating_connection_nets.txt # # ---------------------------------------------------- # # # All of these are 3V3 signals: SPI Bus and GPIO for the Address lines # ----------------------------------------------------------------------- # # NET 'INTERP_1_SCLK' # Interposer #1 SCLK from FPGA # NET 'INTERP_1_MOSI' # Interposer #1 MOSI from FPGA # NET 'INTERP_1_MISO' # Interposer #1 MISO to FPGA # NET 'INTERP_1_CS_B' # Interposer #1 CS_B from FPGA # # NET 'INTERP_1_CS_Adrs_0' # Interposer #1 CS Address 0 from FPGA # NET 'INTERP_1_CS_Adrs_1' # Interposer #1 CS Address 1 from FPGA # NET 'INTERP_1_CS_Adrs_2' # Interposer #1 CS Address 2 from FPGA # NET 'INTERP_1_CTRL_Reset_B' # Interposer #1 CTRL_Reset_B from FPGA # # # NET 'INTERP_2_SCLK' # Interposer #2 SCLK from FPGA # NET 'INTERP_2_MOSI' # Interposer #2 MOSI from FPGA # NET 'INTERP_2_MISO' # Interposer #2 MISO to FPGA # NET 'INTERP_2_CS_B' # Interposer #2 CS_B from FPGA # # NET 'INTERP_2_CS_Adrs_0' # Interposer #2 CS Address 0 from FPGA # NET 'INTERP_2_CS_Adrs_1' # Interposer #2 CS Address 1 from FPGA # NET 'INTERP_2_CS_Adrs_2' # Interposer #2 CS Address 2 from FPGA # NET 'INTERP_2_CTRL_Reset_B' # Interposer #2 CTRL_Reset_B from FPGA # #